Texas Instruments TMS370 Series, Application Book

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490
output lines from the TMS370 to the EPROM’s E pin. The pins should be software enabled before the
EPROM’s program is entered.
•
Access time from address to valid data:
TMS370 (no wait) requires data t
D(AV–DV)R
1.5 t
c
– 115 185 ns
TMS27C256-17 provides data t
A(A)
170 ns (ok)
•
Access time from enable low to valid data:
TMS370 (no wait) requires t
D(EL–DV)
t
c
– 95 105 ns
TMS27C256-17 provides data t
A(E)
E pin 170 ns (not ok)
TMS27C256-17 provides data t
EN(G)
G pin 75 ns (ok)
Bank Switching Examples
The programs in this section show how memory bank switching can be used by the circuit in Figure 1 (page
482). Memory bank switching allows two or more memory devices to share the same addresses. The
programmable chip-select signals (CSHx, CSEx, and CSPF) enable the memory devices or banks one at
a time during a read or write cycle. Figure 8 and Table 12 define the registers and their addresses used in
these examples.
In the interface example in Figure 1 (page 482), the three EPROM devices (ROM1 – ROM3) each use
addresses 8000h though FFFFh. Only one EPROM device (or bank), selected by CSH1, CSH2, or CSH3,
can be allowed to read data at a single time. The two RAM devices are each mapped at addresses 2000h
through 3FFFh. The write and read cycles affect one RAM device at a time, as determined by the chip-select
signals CSE1 and CSE2. The CSPF signal controls the peripheral memory device, which, in our example,
is unspecified but defined to contain 64 bytes of memory. This device is mapped at addresses 10C0h
through 10FFh.
To use external memory, devices with memory expansion must be configured for the microcomputer mode
so that the chip-select signals are available. The external memory devices must have 3-state outputs
because these devices share the data bus.
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