TMS320F280x SDFlash Programming Utilities
F280x SDFlash Algo V1.1
Texas Instruments Inc. 22
Verify User Option 2 specifies the OTP waitstate register (FOTPWAIT) contents:
FOTPWAIT Register
The sample SDFlash project uses the default
value of 001F. This value is also used if the
option is left blank.
To set the wait state values:
9.2.1. Open the project settings: Project ->
Settings
9.2.2. Click on the Verify tab
9.2.3. For User Options 1 enter the value for
the FBANKWAIT register
9.2.4. For User Options 2 enter the value for
the FOTPWAIT register
9.2.5. Select OK
9.2.6. Save the project: File->Save Project
9.3. CPU Frequency and PLL Multiplier Configuration Toggle Test: User Option 3
User Option 3 turns on and off the frequency configuration toggle test. This test is used to confirm that the
algorithms are properly configured for the CPU frequency and PLL multiplier. Refer to section 7 for information on
how to configure the algorithm for the frequency of your CPU.
The toggle test is available as user option 3 for erase, program and verify because the algorithm file for each of the
operations is a separate compile. At initial setup, it is recommended that the frequency configuration of at least the
erase and program operations are verified via the toggle test.
