TMS320F280x SDFlash Programming Utilities
F280x SDFlash Algo V1.1
Texas Instruments Inc. 14
7. PLL and CPU Clock Rate Configuration
CAUTION
The F280x Flash API used by SDFlash contains several delay parameters that
are implemented as software delays. Timing of these delays is VITAL to proper
operation. To ensure the proper delays, the flash algorithms must be run at the
correct speed.
As shipped, the algorithms are configured for the following:
20 MHz input clock
x10 PLLCR (0x000A)
½ CLKINDIV enabled
This results in a 100 MHz CPU clock (SYSCLKOUT)
If your hardware requires any of the following:
a different CPU rate (SYSCLKOUT) then 100MHz
or requires a different PLLCR setting then 0x000A
or requires the PLL to be disabled
or requires that CLKINDIV is set (1/2 disabled in this case PLLCR must
be set to 0x0000)
then you must modify and re-compile the flash programming algorithms for
your system’s specific requirements as described below:
The following steps describe how to compile a new SDFlash algorithm file for a custom frequency and
PLL Control Register (PLLCR) setting.
7.1.
Using Code Composer Studio (CCS), load the projects for your device. There is one project per
operation and all must be re-compiled for the new PLL configuration. These are the CCS
projects used to build the SDFlash algorithm files. The projects are:
F2801: Install Dir: <SDFlash>\myprojects\tif280x_V1_0\f2801\flash28\
SDFlash2801_Erase.pjt,
SDFlash2801_Program.pjt,
SDFlash2801_Verify.pjt
SDFlash2801_DepRecover.pjt
F2802: Install Dir: <SDFlash>\myprojects\tif280x_V1_0\f2802\flash28\
SDFlash2802_Erase.pjt,
SDFlash2802_Program.pjt,
SDFlash2802_Verify.pjt
SDFlash2802_DepRecover.pjt
F2806: Install Dir: <SDFlash>\myprojects\tif280x_V1_0\f2806\flash28\
SDFlash2806_Erase.pjt,
SDFlash2806_Program.pjt,
SDFlash2806_Verify.pjt
SDFlash2806_DepRecover.pjt
F2808: Install Dir: <SDFlash>\myprojects\tif280x_V1_0\f2808\flash28\
SDFlash2808_Erase.pjt,
SDFlash2808_Program.pjt,
SDFlash2808_Verify.pjt
SDFlash2808_DepRecover.pjt
