Texas Instruments TAS54 4C Series Design Manual Download

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Developer's Guide

SLOA196 – June 2014

TAS54x4C Design Guide

The TAS5414C-Q1 and TAS5424C-Q1 devices are 4-channel class-D amplifiers in one integrated circuit
(IC). The devices were developed for automotive use and are qualified in accordance with the AECQ100
specification. When designing the control code to operate the TAS5414B, TAS524B, TAS5414C,
TAS5424C, and TAS5412 devices through I

C, the unique device characteristics must be taken into

account for proper system function. This design guide includes software development guidelines as well
as hardware instructions to provide the necessary circuit topologies and part types to meet strict OEM-
audio specifications and the EMI standards of CISPR25.

Contents

TAS54x4C Hardware Design Guidelines

.................................................................................

1.1

Circuit Design

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1.2

C Communication

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1.3

Oscillator

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1.4

Output

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1.5

Component Selection

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1.6

Protection

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1.7

Load Diagnostics

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1.8

Power Supply

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1.9

Charge Pump

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1.10

EMI and PCB Layout Considerations

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1.11

Filtering

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1.12

Paralleling Outputs

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1.13

Mute

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1.14

Standby

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1.15

Line Output

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1.16

Harmonic Crosstalk

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1.17

THD+N Versus Frequency

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TAS54x4C Software Design Guidelines

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2.1

Definitions

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2.2

Power Up and Initialization

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2.3

Using the Device to Play Music

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2.4

Using the Device to Stop Playing Musing

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2.5

Load Diagnostics

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2.6

Fault Handling

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2.7

Device Mode Summary

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List of Figures

TAS5414C Input Circuit

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Clock Synchronization Options

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One-Half of the Typical Output Stage With Snubbers

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Typical Output Demodulation Filter

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Inductance Versus Current and Q Factor

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CLIP_OTW Pin Voltage Versus % of THD

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Load-Diagnostic Output-Waveforms Timing Diagram

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Channel 1

→

Channel 3 Harmonic Crosstalk With Default Switching Phase Settings

...........................

THD+N vs Frequency Improvements

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SLOA196 – June 2014

TAS54x4C Design Guide

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Summary of Contents for TAS54 4C Series

Page 1: ...on 12 1 7 Load Diagnostics 13 1 8 Power Supply 15 1 9 Charge Pump 15 1 10 EMI and PCB Layout Considerations 16 1 11 Filtering 16 1 12 Paralleling Outputs 17 1 13 Mute 17 1 14 Standby 17 1 15 Line Output 18 1 16 Harmonic Crosstalk 18 1 17 THD N Versus Frequency 19 2 TAS54x4C Software Design Guidelines 20 2 1 Definitions 20 2 2 Power Up and Initialization 21 2 3 Using the Device to Play Music 22 2 4...

Page 2: ... Handling 25 15 Channel Fault Handling 26 16 Mode Summary Excluding Faults 26 List of Tables 1 Oscillator Configuration and I2 C Addresses 4 2 Recommended Switching Frequencies for AM Mode Operation 7 3 Load Diagnostic Timing 14 2 TAS54x4C Design Guide SLOA196 June 2014 Submit Documentation Feedback Copyright 2014 Texas Instruments Incorporated ...

Page 3: ...apacitor values for the TAS54x4C devices are 0 47 µF or 1 µF For a 0 47 µF capacitor with 20 tolerance the highest cutoff frequency can be calculated using 60 kΩ and 0 38 µF The worst case cutoff frequency for this example is 7 1 Hz which allows for flat gain in the audio band The common mode rejection ratio CMRR is also affected by the input circuit The balanced inputs of the TAS5424C must have e...

Page 4: ...dress is determined by the DC voltage present on the address selection pin The I2 C address pin voltage is sensed when the device is released from standby mode This voltage is then latched at 300 µs Therefore any noise or voltage glitch cannot change the I2 C address during operation Because this pin latches when released from standby a capacitor is not necessary on this pin The charge time on the...

Page 5: ...z These three frequencies synchronize the ICs and are present on the OSC_SYNC pin This oscillator is then divided again by 8 to provide 500 kHz 417 kHz and 357 kHz switching frequency options The divide ratio is set through the I2 C 1 3 1 Oscillator Synchronization Some designs require more than one TAS54xx device As previously mentioned in Section 1 2 one I2 C bus can have up to four separate dev...

Page 6: ...0 offset by 90 which is half of the switching phase 45 Phase 180 Phase Figure 2 Clock Synchronization Options NOTE The PCB layout for the OSC_SYNC should be a direct route or the shortest route from the master to slave devices for best operation A star connection is preferred instead of a daisy chain The REXT resistor that sets the 20 MHz oscillator must still be used in the slave devices The 20 M...

Page 7: ...ality This variation moves the oscillator frequency enough to avoid the AM receiver from locking on the frequency and producing a tone The next design characteristic for dither is to determine the dither frequency or how fast the REXT pin current changes Any change in the PWM frequency is demodulated as an output signal Because the TAS54x4C devices have feedback this change is reduced by the amoun...

Page 8: ... A bypass capacitor C BYPASS must be included in the design because it is part of the current path for snubbing the inductance of the high side FET The terminals of C BYPASS must be close to the PVDD pins and the PGND pins of the IC Rx and Cx should be close to the output pin and the PGND pins of the IC This necessary to reduce the series inductance of the PCB traces The current loops that are for...

Page 9: ... of the calculated Rx Too high a value for the Rx could allow for a spike but too low of a value for Rx could cause the snubber to draw excessive current and overheat Use Equation 5 to calculate the power loss in the resistor P Cx V2 ƒS where V is the voltage at PVDD ƒS is the switching frequency 5 1 4 2 Demodulation Filter Design An output LC demodulation filter is required to reconstruct the aud...

Page 10: ...ance is infinity and therefore the value of Q would be infinity also See Equation 7 7 The peak of the Q value is located at ƒCO The signal at this frequency is greatly amplified and can be measured on an oscilloscope This signal is seen as a sine wave and can be mistaken as an oscillating amplifier 1 5 Component Selection 1 5 1 Inductors When the inductance value has been determined three addition...

Page 11: ... resistance increases less power is delivered to the loudspeakers and more power is dissipated in the voice coil creating more heat in the voice coil increasing RDC further The RDC is determined by the amplifier power and nominal speaker impedance A 25 W rated amplifier into a 4 Ω speaker should use an inductor with a maximum RDC of 25 mΩ When either amplifier power increases or speaker impedance ...

Page 12: ...just the volume level or reduce bass in the system so that the amplifier will not produce more heat This warning can also be used to turn on a system fan 1 6 3 DC Offset In a car environment with extreme temperature and humidity changes electronic components such as electrolytic capacitors can become leaky over time If this capacitor is used in series with the input signal and it becomes leaky and...

Page 13: ...r or speaker wires could be shorted shorted load the speaker wires could be shorted to ground and the speaker wires could be shorted to power or battery The TAS54x4C devices have the ability to test all of the channels at the same time or each channel individually for a proper load The load diagnostics are instigated through an I2 C command See Figure 13 for a flowchart of the load diagnostics In ...

Page 14: ...short to ground failure occurs if any output does not reach either PVDD pin Likewise if any output does not reach the ground a short to power failure occurs If a boosted PVDD is used the S2P test can still detect a short to battery The OL and SL tests derive the signal by charging and discharging the MUTE capacitor This signal is directed to the output pins The signal is measured differentially ac...

Page 15: ... the power supply can be the battery of the vehicle These devices have feedback around the class D amplifier to provide a fixed gain As in many class D amplifiers the gain is dependent on the power supply voltage but with feedback this is not the case Additional circuits have been added to improve the power supply rejection ratio PSRR further The need for wideband PSRR is to remove high frequency ...

Page 16: ...s to use a four layer PCB with all the traces with high current or clocks on the inner layers with vias to connect them to the parts The outer layers are reserved for ground planes which creates a Faraday cage around the whole PCB reducing the EMI emanated from the PCB 1 11 Filtering 1 11 1 Power Supply Filtering The power supply is tested for both conducted and radiated emissions The first test i...

Page 17: ...el 2 The channel 1 input can be left disconnected When channels 3 and 4 are paralleled the input signal is placed on channel 3 and the input on channel 4 can be left disconnected The power is still voltage limited To increase the power specification a lower load impedance is necessary For example one channel into a 4 Ω load at 14 4 VDC can provide 28W at 10 THD By paralleling two channels one chan...

Page 18: ...im channel The harmonic crosstalk is most prevalent on channels that have the respective switching frequencies 90 degrees out of phase This situation arises on alternate channels of the TAS54x4C devices when the default switching phase of 45 degrees between adjacent channels is selected With this default phase setting the pairings of channels 1 and 3 and of channels 2 and 4 exhibits the most notic...

Page 19: ...rrect data 2 Switch to 180 phase difference The amount of cross talk and feedback from other channels are reduced These options can be incorporated individually or together Therefore the best THD N versus frequency data would be to incorporate all of the options at once for example ƒs 357K HZ at 180 phase shift Figure 9 shows a graphical representation of these options V PVDD 14 4 V RL 4 Ω PO 1 W ...

Page 20: ... be controlled before the output stage proceeds to the hi Z mode The low low mode pulls the output stage to ground to drain the stored current Load diagnostics mode The output stage in this mode is controlled internally through special states to measure the condition of the external amplifier load Gain and common mode ramps In addition to the five operating modes for each H Bridge output stage the...

Page 21: ...turn from load diagnostics The device must be powered on and the STANDBY pin must be pulled high before sending I2 C commands to the device Once STANDBY has been pulled high the power on procedure takes approximately 300 µs Power on device STANDBY high www ti com TAS54x4C Software Design Guidelines 2 2 Power Up and Initialization Every time the device is powered up or returns from a POR power on r...

Page 22: ...n MUTE mode The device starts in hi Z mode TAS54x4C Software Design Guidelines www ti com 2 3 Using the Device to Play Music The device is now powered on load diagnostics may have run and the device is configured The output stages are in hi Z mode The output stages must transition from hi Z mode to mute mode and then into play mode to minimize pops or clicks in the speakers The register values sho...

Page 23: ...s reached when register 0x05 is 0x0F www ti com TAS54x4C Software Design Guidelines 2 4 Using the Device to Stop Playing Musing The device requires one command to place all channels into hi Z mode from play mode The device still executes several ramps and transitions during the process as in Figure 12 If desired by the user the device can also be commanded to any state separately but this command ...

Page 24: ...st or can be run every time the audio system is turned on This test can also be run if a channel fault condition is detected In this case only the single channel can run while the other channels are still playing In this mode only a speaker wire shorts to battery and speaker wire shorts to ground are run but the flow is still the same The total time for load diagnostics is about 450 ms Load diagno...

Page 25: ...e the fault If the fault is not a global fault it is a channel fault See note B Optionally run load diagnostics Register 0x04 holds the status of the global faults These will clear when the fault clears When the value is 0x00 there are no faults present see note A Hi Z mode Any mode Hi Z mode www ti com TAS54x4C Software Design Guidelines 2 6 Fault Handling 2 6 1 Global Faults Global faults place ...

Page 26: ...i Z mode see note B From global fault handling Hi Z mode TAS54x4C Software Design Guidelines www ti com 2 6 2 Channel Faults Channel faults are faults that occur on an individual channel These faults are DC offset overcurrent and local overtemperature faults Only the channel that experienced the fault is placed in Hi Z The other channels remain playing The other difference between channel faults a...

Page 27: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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