TAS54x4C Hardware Design Guidelines
1.2.3
I
2
C Register Details
The TAS54x4C devices have several different types of registers. These registers can be broken into four
basic categories: fault registers (0x00 to 0x01, 0x13), load diagnostic registers (0x02 to 0x03), status
registers (0x04 to 0x07), and control registers (0x08 to 0x0D, 0x10).
The fault registers report any faults that occurred in the device. If the fault is no longer present when the
register is read, the register will still report that a fault occurred in the past because these registers are
latched. The registers will only clear the fault after the fault has cleared and being read.
The load diagnostic registers report the results of load diagnostics that are performed. These registers are
also latched and will clear when a successful load diagnostic is run.
The status registers report the current status of the device including faults and the operational mode of
each channel. These registers are not latched and report the present state in the device at all times.
The control registers allow the system to modify the settings of the device. Note that some settings may
only be changed in hi-Z.
See
for more information about the proper usage of the registers.
1.3
Oscillator
The TAS54x4C devices incorporate an internal oscillator to provide all the necessary clocks and the
output PWM switching clock. The oscillator frequency is set by the current on the REXT pin. The current is
set by placing a resister between REXT and ground. The value of the resistor should be 20 k
Ω
with a
tolerance of 1% for proper operation of the IC. This value sets the frequencies correctly as stated in the
data sheet of the device.
The internal oscillator is 20 MHz which is then divided by 5 for 4 MHz, 6 for 3.33 MHz, or 7 for 2.85 MHz.
These three frequencies synchronize the ICs and are present on the OSC_SYNC pin. This oscillator is
then divided again by 8 to provide 500 kHz, 417 kHz, and 357 kHz switching frequency options. The
divide ratio is set through the I
2
C.
1.3.1
Oscillator Synchronization
Some designs require more than one TAS54xx device. As previously mentioned in
, one I
2
C
bus can have up to four separate devices. One device is considered the master and the other devices are
considered the slaves. The master provides an oscillator clock on the OSC_SYNC pin and the slave
devices require an oscillator input on the OSC_SYNC pin. All devices are synchronized to avoid beat
frequencies in the audio spectrum. If the clock is lost on the slave, the internal watchdog places the
outputs into hi-Z.
To synchronize the devices, use the following procedure:
1. Bring all the devices out of standby and into hi-Z mode
2. Send the I
2
C command on the clock master to place the clock signal on the OSC_SYNC pin. Bit 7 in
register 0x0B must be set to 1.
The slave devices are not allowed to enter play mode until the master has sent a clock
For phase synchronization of the devices which minimizes harmonic crosstalk between devices, use the
previous method to synchronize the devices and add these I
2
C commands after step 2:
1. Place the slave devices in sync-receive mode by changing bit 6 in register 0x0A.
2. Send a sync pulse from the master device by changing bit 6 on register 0x0A.
Bit 6 automatically clears when the synchronization is complete on both the master and slave devices.
Phase synchronization applies to the switching phase and not the audio phase because the audio phase
is always aligned. The inverter allows a new sync pulse between each of the devices to align the 45° or
180° switching phases.
To summarize, two options occur between the OSC_SYNC pin and synchronization of the devices.
5
SLOA196 – June 2014
TAS54x4C Design Guide
Copyright © 2014, Texas Instruments Incorporated
