Texas Instruments SWRU197E, User Manual

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6.2 Connecting the CC Debugger to a System on Chip
6.2.1 Minimum connection for debugging
For successful debugging of a TI 8051-based RF System on Chip, connect the two debug signals
Debug Data (DD) and Debug Clock (DC) and the reset signal RESETn to the device. In addition, the
CC Debugger must be connected to GND and Vdd on the board. Vdd is used as an input to the level
shifters on the CC Debugger, thus allowing a different operating voltage on the target than internally
on the debugger.
The DD signal should be connected to pin P2.2 and DC to pin P2.1 on the SoC
– with the exception of
CC2544, where DD is on P1.3 and DC on P1.2. Please refer to the device data sheets for details on
the pin-out.
Note that it is possible to power the target board from the debugger by connecting the 3.3V signal on
pin 9 on the connector to the target board.
2 1
4 3
6 5
8 7
10 9
GND
DC (Debug Clock)
RESETn
3.3V from debugger. Can
optionally be used to
power the target board
DD (Debug Data)
SoC
P2.2
P2.1
RESETn
Vdd
GND
Vdd
CC Debugger
Connector
CCxxxx
System-on-Chip
NOTE 2
Vdd
NOTE 1
1
0
k
Ω
2.7 k
Ω
1
n
F
Note 1: Some early revisions of certain SoCs (CC2430, CC2510 and CC1110) needed an external
pull-up to avoid unwanted transitions on the debug clock line during chip reset
– thus inadvertently
setting the device in debug mode. All new revisions of all SoCs now have an internal pull-up on P2.2,
so this external component is not required.
Note 2: The RESETn pin is sensitive to noise and can cause unintended reset of the chip. For reset
lines susceptible to noise, it is recommended to add an external RC filter. Please refer to the
respective SoC datasheet and reference designs for recommended RESET circuitry. The CC
Debugger supports slow transitions on the reset line, using a 2 ms delay between any transition on the
RESET line and other transitions on the DC and/or DD lines.
6.2.2 Minimum connection for SmartRF Studio
Use the same connection as for debugging the SoC.