Public Version
IVA2.2 Subsystem Register Manual
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5.5.3 IDMA Registers
This section provides information about the IDMA Module. Each register in the module is described
separately below.
5.5.3.1
IDMA Register Mapping Summary
Table 5-53. IDMA Register Summary
Register Name
Type
Register Width
Address Offset
Physical Address
(Bits)
R
32
0x0000 0000
0x0182 0000
RW
32
0x0000 0004
0x0182 0004
RW
32
0x0000 0008
0x0182 0008
RW
32
0x0000 000C
0x0182 000C
RW
32
0x0000 0010
0x0182 0010
R
32
0x0000 0100
0x0182 0100
RW
32
0x0000 0108
0x0182 0108
RW
32
0x0000 010C
0x0182 010C
RW
32
0x0000 0110
0x0182 01100
RW
32
0x0000 0200
0x0182 0200
RW
32
0x0000 0204
0x0182 0204
RW
32
0x0000 0208
0x0182 0208
RW
32
0x0000 020C
0x0182 020C
R
32
0x0000 0300
0x0182 0300
R
32
0x0000 0304
0x0182 0304
W
32
0x0000 0308
0x0182 0308
R
32
0x0000 0400
0x0182 0400
W
32
0x0000 0404
0x0182 0404
5.5.3.2
IDMA Register Descriptions
Table 5-54. IDMA0_STAT
Address Offset
0x0000 0000
Physical address
0x0182 0000
Instance
IVA2.2 GEMIDMA
Description
IDMA Channel 0 Status Register
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
ACTV
PEND
Bits
Field Name
Description
Type
Reset
31:2
Reserved
Reads return 0s
R
0
1
PEND
Pending transfer: Set when control registers are written to by the
R
0
CPU and there is already an active transfer in progress (ACTV = 1)
and cleared when the transfer becomes active.
PEND = 1: Transfer is pending
PEND = 0: No pending transfer
816
IVA2.2 Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated