Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 822 / 3738

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IVA2.2 Subsystem Register Manual
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Table 5-70. IDMA1_COUNT
Address Offset 0x0000 0110
Physical address 0x0182 0110 Instance IVA2.2 GEMIDMA
Description IDMA Channel 0 Count Register
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI Reserved COUNT
INT
FILL
Reserved
Bits Field Name Description Type Reset
31:29 PRI Transfer priority. Used for arbitration between CPU and DMA RW 0x0
accesses when there are conflicts.
PRI = 111b: Low priority
PRI = 000b: High priority
28 INT CPU interrupt enable RW 0
INT = 1: Interrupt CPU (IDMA_INT1) on completion
INT = 0: Do not interrupt CPU on completion
27:17 Reserved Write 0s for future compatibility. RW 0x000
Read returns 0.
16 FILL Block fill: RW 0
FILL = 1: Perform a block fill using the Source address field as the fill
value to the memory buffer pointed to by the Destination address
field.
FILL = 0: Block transfer from the source address to the destination
address.
15:2 COUNT 16-bit byte count. Must be a multiple of 4 bytes. A transfer count of RW 0x0000
zero will not transfer any data, but will generate an interrupt if
requested in the INT field.
1:0 Reserved Write 0s for future compatibility. RW 0x0
Read returns 0.
Table 5-71. Register Call Summary for Register IDMA1_COUNT
IVA2.2 Subsystem Basic Programming Model
• Internal Memory-to-Memory Transfer (IDMA) : [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
[21] [22]
• Internal Memory : [23]
IVA2.2 Subsystem Register Manual
• IDMA Register Mapping Summary : [24]
• IDMA Register Descriptions : [25]
Table 5-72. CPUARBE
Address Offset 0x0000 0200
Physical address 0x0182 0200 Instance IVA2.2 GEMIDMA
Description CPU Arbitration Control
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved PRI Reserved MAXWAIT
822 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
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