Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 821 / 3738

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IVA2.2 Subsystem Register Manual
Table 5-66. IDMA1_SOURCE
Address Offset 0x0000 0108
Physical address 0x0182 0108 Instance IVA2.2 GEMIDMA
Description IDMA Channel 1 Source Address Register
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOURCEADDR
Bits Field Name Description Type Reset
31:0 SOURCEADDR Source Address: Must point to a word-aligned memory location local RW 0x00000000
to GEM. When performing a block fill ( IDMA1_COUNT .FILL = 1) the
source address is the fill value. Note that when performing a Fill
Mode transfer all 32-bits of the SOURCEADDR are writeable and
when performing a linear transfer the two LSBs are implemented as
00b.
Table 5-67. Register Call Summary for Register IDMA1_SOURCE
IVA2.2 Subsystem Basic Programming Model
• Internal Memory-to-Memory Transfer (IDMA) : [0] [1] [2] [3]
IVA2.2 Subsystem Register Manual
• IDMA Register Mapping Summary : [4]
Table 5-68. IDMA1_DEST
Address Offset 0x0000 010C
Physical address 0x0182 010C Instance IVA2.2 GEMIDMA
Description IDMA Channel 1 Destination Address Register
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESTADDR
Reserved
Bits Field Name Description Type Reset
31:2 DESTADDR Destination Address: Must point to a word-aligned memory location RW 0x00000000
local to DSP megamodule.
1:0 Reserved Reads return 0s R 0x00
Write 0 for further compaibility
Table 5-69. Register Call Summary for Register IDMA1_DEST
IVA2.2 Subsystem Basic Programming Model
• Internal Memory-to-Memory Transfer (IDMA) : [0] [1] [2] [3]
IVA2.2 Subsystem Register Manual
• IDMA Register Mapping Summary : [4]
821 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
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