Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 827 / 3738

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IVA2.2 Subsystem Register Manual
Bits Field Name Description Type Reset
28:11 Reserved Write 0s for future compatibility. R 0x00
Read returns 0.
10:8 XID Transaction ID R 0x0
Stores the Transaction ID when an error is detected on the
response. Value should match the command id for the access that
resulted in an error.
7:3 Reserved Write 0s for future compatibility. R 0x00
Read returns 0.
2:0 STAT Transaction Status R 0x0
Stores the non-zero status/error code that wasdetected on the
response to an access
0x0: Success (should not cause error to be latched), or
unrecognized RID/WID (should cause error to be
latched)
0x1: Addressing error
0x2: Privilege error
0x3: Timeout error
0x4: Data error
0x7: Exclusive-operation failure
Table 5-87. Register Call Summary for Register IBUSERR
IVA2.2 Subsystem Basic Programming Model
• Error Reporting for IDMA Module : [0] [1] [2] [3] [4] [5] [6]
IVA2.2 Subsystem Register Manual
• IDMA Register Mapping Summary : [7]
Table 5-88. IBUSERRCLR
Address Offset 0x0000 0404
Physical address 0x0182 0404 Instance IVA2.2 GEMIDMA
Description Bus Access Error Clear
Type W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CLR
Bits Field Name Description Type Reset
31:1 Reserved Write 0s for future compatibility. W 0x00000000
Read returns 0.
0 CLR Clear Error W 0
CLR = 0: Writes of 0 have no effect.
CLR = 1: Write of 1 clears all bits in the IBUSERRregister. Once an
error is detected, the MDMA Error register must be cleared before
additional errors canbe detected/stored.
Table 5-89. Register Call Summary for Register IBUSERRCLR
IVA2.2 Subsystem Basic Programming Model
• Error Reporting for IDMA Module : [0]
IVA2.2 Subsystem Register Manual
• IDMA Register Mapping Summary : [1]
827 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
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