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IVA2.2 Subsystem Basic Programming Model
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For further system dynamic power savings, the sequencer CPU root clock can be independently divided
when sequencer activity is reduced.
The root clock of the sequencer CPU can be divided by writing a value different from the value of the
NOCLKDIV bit in the
register. There is no software precaution to divide the
sequencer CPU clock internally, in terms of traffic or idle conditions. However, this setting is static; that is,
it is defined based on whether the sequencer MHz budget must run at full speed, based on a particular
task or scenario. The
value must not be changed twice within 16 sequencer clock
cycles, or the second request can be ignored. This has no other side effect. Because of the requirement
that the setting be static, it is acceptable to make this sequence uninterruptible, pad it with NOPs (or
useful operations), or check for change effect, after changing the sequencer clock ratio.
The sequencer CPU clock can be independently divided by 2, 3, or 4, or not divided at all. By default, this
clock is not divided.
5.4.11 Error Identification Process
Several mechanisms are available in the IVA2.2 subsystem to report errors at different levels.
5.4.11.1 Error Reporting for IDMA Module
The IDMA has its own error-reporting mechanism. The DSP megamodule implements an error register in
EMC (IVA_IDMA.
) that latches errors for external invalid transactions on either the DMA
(MDMA) bus or the configuration (CFG) bus. Errors are detected on the CFG and MDMA write status or
read status interfaces. If an error is received and the corresponding command is an invalid transaction, the
IVA_IDMA.
[31:29] ERR, IVA_IDMA.
[10:8] XID, and IVA_IDMA.
[2:0] STAT
fields are updated accordingly. An error signaled through a non-0 read status is detected on the read
data/status interface or a non-0 write status on the write status interface. Alternately, the EMC records an
error if a read or write status response is detected for an unrecognized write ID.
NOTE:
The user must ensure that the EMC detects/stores error information only for the first
detected error on either the MDMA or CFG bus, regardless of whether it is a read or write
status. In other words, a single error register (IVA_IDMA.
) is shared by read and
write errors and by the MDMA bus and the CFG bus, and only the first error is stored. If a
read error and a write error are detected at the same time, the write status error is given
higher priority and is latched into the IVA_IDMA.
register.
When an error is detected and stored in the IVA_IDMA.
register, the EMC_BUSERR event
(EVT127, see
) is available as a system event that can be selected as either a DSP CPU
interrupt or an exception event.
The user can clear latched errors by writing 1 to the IVA_IDMA.
[0] CLR bit.
5.4.11.2 Error Reporting for EDMA Module
The TPTC and TPCC blocks of the EDMA module also contain registers to inform the user of a problem
during IVA2.2 external DMA communication.
TPCC Block
The TPCC provides a single error interrupt output CCERRINT (EVT38, see
) that consolidates
the error conditions:
•
QDMA missed events (stored in the
register)
•
DMA missed events (stored in the
register)
•
Transfer completion code error (stored in the
[16] TCCERR bit)
•
Queue threshold error events (stored in the
[n] QTHRXCDn bit, n = {0,1}]
When an error is detected, the CCERRINT event is asserted, because error events do not have enables.
802
IVA2.2 Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
