Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 819 / 3738

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IVA2.2 Subsystem Register Manual
Table 5-57. Register Call Summary for Register IDMA0_MASK
IVA2.2 Subsystem Basic Programming Model
• Starting the Transfer : [0]
IVA2.2 Subsystem Register Manual
• IDMA Register Mapping Summary : [1]
Table 5-58. IDMA0_SOURCE
Address Offset 0x0000 0008
Physical address 0x0182 0008 Instance IVA2.2 GEMIDMA
Description IDMA Channel 0 Source Address Register
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOURCEADDR Reserved
Bits Field Name Description Type Reset
31:5 SOURCEADDR Source Address: Must point to a 32-byte-aligned (e.g. window-aligned) RW 0x0000000
memory location local to DSP megamodule or to a valid configuration register
space.
4:0 Reserved Write 0s for future compatibility. RW 0x00
Read returns 0.
Table 5-59. Register Call Summary for Register IDMA0_SOURCE
IVA2.2 Subsystem Basic Programming Model
• Starting the Transfer : [0]
IVA2.2 Subsystem Register Manual
• IDMA Register Mapping Summary : [1]
Table 5-60. IDMA0_DEST
Address Offset 0x0000 000C
Physical address 0x0182 000C Instance IVA2.2 GEMIDMA
Description IDMA Channel 0 Destination Address Register
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESTADDR Reserved
Bits Field Name Description Type Reset
31:5 DESTADDR Destination Address: Must point to a 32-byte-aligned (e.g. RW 0x0000000
windowaligned) memory location local to DSP megamodule or to a
valid configuration register space.
4:0 Reserved Write 0s for future compatibility. RW 0x00
Read returns 0.
Table 5-61. Register Call Summary for Register IDMA0_DEST
IVA2.2 Subsystem Basic Programming Model
• Starting the Transfer : [0]
IVA2.2 Subsystem Register Manual
• IDMA Register Mapping Summary : [1]
819 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
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