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IVA2.2 Subsystem Basic Programming Model
QCHMAP[1] = (QCHMAP[1] & ~(0x1FF<<5)) | 0x5<<5;
/* ---------------------------------------------------- */
/* Define DST parameter (0x3) to be trigger word of LCH */
/* ---------------------------------------------------- */
QCHMAP[1] = (QCHMAP[1] & ~( 0x7<<2)) | 0x3<<2;
In addition, the IDMA can be used to offload the CPU of the DMA configuration. See
,
Offloaded Configuration (Using IDMA).
5.4.4.6.5 Offloaded Configuration (Using IDMA)
The IVA2.2 allows quick programming of DMA transfers by offloading the CPU of most of the DMA
transfer issue time. To do so, the user typically maintains a copy of the logical channel contexts (PaRAM
entries) in L1D SRAM. A CPU update of a logical channel context is very fast in L1D SRAM. After
completing a logical channel context update, the CPU can page the context from L1D to DMA PaRAM
entries using another simple DMA, internal-to-DSP megamodule (IDMA). For example:
disable_interrupts();
while(IDMA0_STATUS & 0x3);// previous IDMA completion/*
------------------------------------------------------- */
/* Update of logical channels definition table in L1D */
/* ---------------------------------------------------- */
LCTable->OPT = opt;
LCTable->SRC = src;
LCTable->ACNT = num_bytes;
LCTable->BCNT = num_arrays;
LCTable->DST = dst;
LCTable->DSTBIDX = dbidx;
LCTable->SRCBIDX = sbidx;
LCTable->LINK = 0xFFFF;
LCTable->BCNTRLD = bcntrld;
LCTable->DSTCIDX = dcidx;
LCTable->SRCCIDX = scidx;
LCTable->CCNT = num_frames;
/* ---------------------------------------------------- */
/* initiate IDMA transfer */
/* ---------------------------------------------------- */
= &LCTable[0];
= &PaRAM[0];
= 0xFFFFFF00;
= 0x0;
enable_interrupts();
5.4.4.6.6 Direct Configuration to Transfer Channel (Not Recommended)
The registers of the physical channels are memory-mapped, primarily to enable, clear, and read status for
error interrupts generated by the physical channel. For more information, see
, Error
Identification Process.
763
SWPU177N – December 2009 – Revised November 2010
IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated