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PRCM Register Manual
Bits
Field Name
Description
Type
Reset
31:11
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x000000
10
EN_IVA2_DPLL_LPMODE
This bit allows to enable or disable the LP mode of the
RW
0x0
IVA2 DPLL. Writting this bit to switch the mode between
LP or normal mode will take effect only when the DPLL
will have transition into the bypass or stop state, followed
by a lock or re-lock of the DPLL.
0x0: Disables the DPLL LP mode to re-enter the normal
mode at the following lock or re-lock sequence.
0x1: Enables the DPLL LP mode to enter the LP mode at
the following lock or re-lock sequence.
9:8
RESERVED
RW
0x0
7:4
RESERVED
Reserved
RW
0x1
3
EN_IVA2_DPLL_DRIFTGUARD
This bit allows to enable or disable the automatic
RW
0x0
recalibration feature of the IVA2 DPLL. The IVA2 DPLL
will automatically start a recalibration process upon
assertion of the recal flag if this bit is set.
0x0: Disables the IVA2 DPLL automatic recalibration
mode
0x1: Enables the IVA2 DPLL automatic recalibration
mode
2:0
EN_IVA2_DPLL
IVA2 DPLL control; Other enums: Reserved
RW
0x1
0x1: Put the IVA2 DPLL in low power stop mode
0x5: Put the IVA2 DPLL in low power bypass mode
0x7: Enables the IVA2 DPLL in lock mode
Table 3-100. Register Call Summary for Register CM_CLKEN_PLL_IVA2
PRCM Functional Description
•
:
•
•
•
:
PRCM Basic Programming Model
•
CM_CLKEN_PLL_<processor_name> (Processor DPLL Clock Enable Register)
PRCM Register Manual
•
Table 3-101. CM_IDLEST_IVA2
Address Offset
0x0000 0020
Physical Address
0x4800 4020
Instance
IVA2_CM
Description
IVA2 standby status and access availability monitoring. This register is read only and automatically
updated.
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
ST_IVA2
Bits
Field Name
Description
Type
Reset
31:1
RESERVED
Read returns 0.
R
0x00000000
0
ST_IVA2
IVA2 standby status.
R
0x1
0x0: IVA2 sub-system is active.
0x1: IVA2 sub-system is in standby mode.
461
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated