Texas Instruments OMAP36 Series, Technical Reference Manual

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Camera ISP Register Manual
Bits Field Name Description Type Reset
18:10 DIVC Sets the clock divisor value for the CNTCLK clock RW 0x000
generation based on the CAM.MCLK input clock.
CNTCLK is an internal clock used by the TIMING CTRL
module counters. Usually, CNTCLK = CAM.MCLK /
DIVC, except for some particular values shown hereafter.
0x0: No clock. CNTCLK is gated.
9:5 DIVB Sets the clock divisor value for the CAM.XCLKB clock RW 0x00
generation based on the CAM.MCLK input clock. Usually,
CAM.XCLKB = CAM.MCLK / DIVB, except for some
particular values shown hereafter.
This bit field is not reset by a soft reset; a hard reset is
required. It enables to keep the clock configuration stable
through a soft reset.
0x0: CAM.XCLKB = stable low level. Divider disabled.
0x1: CAM.XCLKB = stable high level. Divider disabled.
0x1F: CAM.XCLKB = CAM.XCLK. Bypass.
4:0 DIVA Sets the clock divisor value for the CAM.XCLKA clock RW 0x00
generation based on the CAM.MCLK input clock. Usually,
CAM.XCLKA = CAM.MCLK / DIVA, except for some
particular values shown hereafter.
This bit field is not reset by a soft reset; a hard reset is
required. It enables to keep the clock configuration stable
through a soft reset.
0x0: CAM.XCLKA = stable low level. Divider disabled.
0x1: CAM.XCLKA = stable high level. Divider disabled.
0x1F: CAM.XCLKA = CAM.XCLK. Bypass.
Table 6-103. Register Call Summary for Register TCTRL_CTRL
Camera ISP Integration
• Camera ISP Clock Configuration : [0] [1]
Camera ISP Functional Description
• Camera ISP Timing Control Control-Signal Generator : [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
Camera ISP Basic Programming Model
• Camera ISP Timing CTRL Timing Generator : [13] [14] [15] [16]
• Camera ISP Timing CTRL Camera-Control Signal Generator : [17] [18] [19]
• Camera ISP Timing CTRL Vertical Synchro-Based Control-Signal Generation or Externally-Generated cam_global_reset : [20]
[21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32]
• Camera ISP Timing CTRL Internally-Generated cam_global_reset-Based Control-Signal Generation : [33] [34] [35] [36] [37]
[38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54]
• Camera ISP Timing CTRL STROBE and PRESTROBE Signal Generation for Red-Eye Removal : [55]
Camera ISP Register Manual
• Camera ISP Registers Summary : [56]
• Camera ISP Register Description : [57] [58] [59] [60] [61] [62] [63] [64] [65] [66] [67] [68] [69] [70] [71]
Table 6-104. TCTRL_FRAME
Address Offset 0x0000 0054
Physical Address Instance ISP
See Table 6-81
Description TIMING CONTROL - FRAME REGISTER
This register is used by the TIMING CTRL module to generate the SHUTTER, PRESTROBE and
STROBE signals.
Type RW
1325 SWPU177N – December 2009 – Revised November 2010 Camera Image Signal Processor
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