Public Version
Camera ISP Functional Description
www.ti.com
and on both output ports: video port and shared-buffer-logic (SBL) port.
•
If the CSI2A or CSI1/CCP2B/CSI2C interface is selected, control-signal generation works on both
output ports: video port and interconnect port.
The cam_global_reset signal can also be generated internally by the control-signal generator under
software control. In this case, the prestrobe and shutter signals are synchronized on the internally
generated cam_global_reset signal. The multiplexer controls whether control-signal generation must be
triggered by the internal or external cam_global_reset signal.
The prestrobe-, strobe-, and shutter-control signals can be individually enabled at any time. These signals
must not be disabled by software.
The clock divider generates the CNTCLK clock based on the cam_mclk clock. The clock divider is
programmable.
summarizes the possible frequencies as a function of the divisor values.
Table 6-34. Camera ISP Timing Control Control-Signal Generator: CNTCLK Frequencies
Divisor Value
[18:10] DIVC
CNTCLK Clock
0 (default)
Clock gated. No clock.
1
216 MHz, free-running.
2
108 MHz
3
72 MHz
4
54 MHz
...
...
510
0.424 MHz
511
0.423 MHz
There are three counters per control signal, for a total of nine counters. Each counter is programmable.
•
The frame counter is decreased each time a full new frame is received, based on the EOF events from
the CCDC or from receiver modules.
–
A new frame is detected in the CSI2A, CSI1/CCP2B, CSI2C receivers on detection of a frame-start
code (FSC) followed by a frame-end code (FEC).
–
A new frame is detected in the CCDC module by using the falling edge of the vertical
synchronization signal at the input of the CCDC module.
NOTE:
The rising edge of the vertical synchronization signal and the vertical synchronization
polarity settings inside the CCDC cannot be used. The modules have no effect on this
detection.
–
The frame counter determines how many whole frames must be ignored before the delay counter is
triggered. The frame counters can be set to 0 to bypass them.
•
The delay counter determines the control-signal activation delay. The counter is decreased at every
CNTCLK clock cycle. When the counter reaches 0, the control signal is asserted. If the delay counter is
set to 0, the control signal is asserted immediately.
•
The activation-length counter determines the control-signal assertion length. The counter is decreased
at every CNTCLK clock cycle. When the counter reaches 0, the signal is deasserted and the
control-signal enable bit is disabled. If the activation length is set to 0, the control signal is not asserted
and the control-signal enable bit is disabled.
The polarity of the following signals can be individually selected:
•
[26] STRBPSTRBPOL for the prestrobe and strobe signals
•
[24] SHUTPOL for the shutter signal
•
[30] GRESETPOL for the cam_global_reset signal
The software can trigger the generation of the cam_global_reset signal to the camera module. The
1190
Camera Image Signal Processor
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated