Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 1262 / 3738

Public Version
Camera ISP Basic Programming Model
www.ti.com
6.5.5.2.1 Camera ISP Timing CTRL Vertical Synchro-Based Control-Signal Generation or
Externally-Generated cam_global_reset
Before enabling the control-signal generation, the following registers must be set:
• Select the input that triggers the control signals. The trigger signal can come from the PARALLEL,
CSI2A, CSI2C or CSI1/CCP2B interface, or the externally-generated cam_global_reset signal.
– TCTRL_CTRL [28:27] INSEL
• The signal must be set to INPUT:
– TCTRL_CTRL [31] GRESETDIR = 0x0
– Writes to TCTRL_CTRL [29] GRESETEN bit do not trigger the PRESTROBE, STROBE, and
SHUTTER signals, and do not generate the cam_global_reset signal.
• The following bits are cleared automatically to 0 after the signal assertion:
– TCTRL_CTRL [21] SHUTEN
– TCTRL_CTRL [22] PSTRBEN
– TCTRL_CTRL [23] STRBEN
• The following bits set the polarity of the SHUTTER, STROBE/PRESTROBE, and cam_global_reset
signals. The signals can be active high or active low:
– TCTRL_CTRL [24] SHUTPOL
– TCTRL_CTRL [26] STRBPSTRBPOL
– TCTRL_CTRL [30] GRESETPOL
• The following bit sets the clock divisor value, which generates the CNTCLK clock:
– TCTRL_CTRL [18:10] DIVC
The clock is set by CNTCLK = cam_mclk/ TCTRL_CTRL [18:10] DIVC. The possible values are 0 to
511. Setting DIVC = 0 disables the CNTCLK clock generation.
• The frame counters are set with (possible values are 0 to 63 frames):
– TCTRL_FRAME [5:0] SHUT
– TCTRL_FRAME [11:6] PSTRB
– TCTRL_FRAME [17:12] STRB
NOTE: If the value is 0, the timing control module does not delay any frame in input.
• The delay counters are set with:
– TCTRL_SHUT_DELAY
– TCTRL_PSTRB_DELAY
– TCTRL_STRB_DELAY
The possible values are 0 to 2
25
- 1 cycles. The cycles are at the CNTCLK clock frequency. The
maximum signal duration is (2
25
-1) x 2.366 s = 79 s ( TCTRL_CTRL [18:10] DIVC = 511).
• The signal durations are set with:
– TCTRL_SHUT_LENGTH
– TCTRL_PSTRB_LENGTH
– TCTRL_STRB_LENGTH
The possible values are 0 to 2
24
-1 cycles. The cycles are at the CNTCLK clock frequency. The
maximum signal duration is (2
24
-1) x 2.366 s = 39.69 s ( TCTRL_CTRL [18:10] DIVC = 511).
6.5.5.2.2 Camera ISP Timing CTRL Internally-Generated cam_global_reset-Based Control-Signal
Generation
Before enabling the cam_global_reset control-signal generation by writing TCTRL_CTRL [29] GRESETEN
= 1, the following registers must be set:
1262 Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated