Texas Instruments OMAP36 Series, Technical Reference Manual

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camisp-102
cam_strobe
cam_shutter
cam_mclk
CS2A_EOF
CSI1_EOF
VS
Timing control module
cam_global_reset
cam_xclka
cam_xclkb
Control signal generator
Timing generator
cam_global_reset
CS2C_EOF
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Camera ISP Functional Description
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6.4.4 Camera ISP Timing Control
6.4.4.1 Camera ISP Timing Control Features
The timing-control module provides two clocks (cam_xclka and cam_xclkb) that can be used by external
camera modules. It also generates the control signals (cam_strobe and cam_shutter) for the flash
prestrobe, flash strobe, and mechanical shutters.
The timing-control module includes a timing generator and a control-signal generator.
6.4.4.2 Camera ISP Timing Control Overview
Figure 6-75 shows a block diagram of the timing-control module.
Figure 6-75. Camera ISP Timing Control block diagram
6.4.4.2.1 Camera ISP Timing Control Generator
The timing coontrol generates the cam_xclka and cam_xclkb clocks based on the CAM_MCLK frequency,
which can be up to 216 MHz. The cam_mclk is used only by the clock generator; the cam_xclka and
cam_xclkb clocks are not used internally by the camera ISP. The clock divider is programmable.
The possible frequencies of cam_xclka and cam_xclkb and their respective configurations are described in
Section 6.3.1.1.3 , Clock Configuration.
Table 6-34 summarizes the possible frequencies as a function of the divisor values.
6.4.4.2.2 Camera ISP Timing Control Control-Signal Generator
The control-signal generator generates the prestrobe, strobe, and shutter signals: cam_strobe and
cam_shutter.
Figure 6-76 shows the principle of control-signal generation.
1188 Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated