Texas Instruments MSP430FG4618 Manual Download Page 9

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MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

www.ti.com

SLAS508J – APRIL 2006 – REVISED JUNE 2015

Table 4-1. Signal Descriptions (continued)

PIN NO.

SIGNAL NAME

I/O

DESCRIPTION

ZQW

P10.5

General-purpose digital I/O

I/O

LCD segment output 4

P10.4

General-purpose digital I/O

I/O

LCD segment output 5

P10.3

General-purpose digital I/O

I/O

LCD segment output 6

P10.2

General-purpose digital I/O

I/O

LCD segment output 7

P10.1

General-purpose digital I/O

I/O

LCD segment output 8

P10.0

General-purpose digital I/O

I/O

LCD segment output 9

P9.7

General-purpose digital I/O

I/O

S10

LCD segment output 10

P9.6

General-purpose digital I/O

I/O

S11

LCD segment output 11

P9.5

General-purpose digital I/O

I/O

S12

LCD segment output 12

P9.4

General-purpose digital I/O

I/O

S13

LCD segment output 13

P9.3

General-purpose digital I/O

I/O

S14

LCD segment output 14

P9.2

General-purpose digital I/O

I/O

S15

LCD segment output 15

P9.1

General-purpose digital I/O

I/O

S16

LCD segment output 16

P9.0

General-purpose digital I/O

I/O

S17

LCD segment output 17

P8.7

General-purpose digital I/O

I/O

S18

LCD segment output 18

P8.6

General-purpose digital I/O

I/O

S19

LCD segment output 19

P8.5

General-purpose digital I/O

I/O

S20

LCD segment output 20

P8.4

General-purpose digital I/O

I/O

S21

LCD segment output 21

P8.3

General-purpose digital I/O

I/O

S22

LCD segment output 22

P8.2

General-purpose digital I/O

I/O

S23

LCD segment output 23

P8.1

General-purpose digital I/O

I/O

S24

LCD segment output 24

P8.0

General-purpose digital I/O

I/O

S25

LCD segment output 25

P7.7

General-purpose digital I/O

I/O

S26

LCD segment output 26

Terminal Configuration and Functions

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MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

MSP430CG4618 MSP430CG4617 MSP430CG4616

Summary of Contents for MSP430FG4618

Page 1: ...ompare 8KB of RAM With Shadow Registers MSP430FG4618 MSP430CG4618 On Chip Comparator 116KB 256B of Flash or ROM Supply Voltage Supervisor and Monitor With 8KB of RAM Programmable Level Detection MSP430FG4619 MSP430CG4619 Serial Communication Interface USART1 Select 120KB 256B of Flash or ROM Asynchronous UART or Synchronous SPI by 4KB of RAM Software For Complete Module Descriptions see the MSP430...

Page 2: ...DB MAB Enhanced Emulation FG only MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 SLAS508J APRIL 2006 REVISED JUNE 2015 www ti com Device Information 1 PART NUMBER PACKAGE BODY SIZE 2 MSP430FG4619IPZ LQFP 100 14 mm 14 mm MSP430FG4619IZQW MicroStar Junior BGA 113 7 mm 7 mm 1 For the most current part package and ordering information for all av...

Page 3: ...r Mode OAFCx 6 46 JTAG TCK TMS TDI TCLK TDO TDI 18 5 45 Flash Memory FG461x Devices Only 47 5 7 Inputs Px x TAx TBX 18 5 46 JTAG Interface 47 5 8 Leakage Current Ports P1 to P10 18 5 47 JTAG Fuse 47 5 9 Outputs Ports P1 to P10 18 6 Detailed Description 48 5 10 Output Frequency 19 6 1 CPU 48 5 11 Typical Characteristics Outputs 20 6 2 Instruction Set 49 5 12 Wake up Timing From LPM3 21 6 3 Operatin...

Page 4: ...gure 5 33 43 Added Table 6 19 and moved P4 6 and P4 7 from Table 6 18 to insert correct LCDS32 control bit name 75 Added Table 6 29 and moved P7 2 and P7 3 from Table 6 28 to insert correct LCDS28 control bit name 88 Added Table 6 31 and moved P7 6 and P7 7 from Table 6 30 to insert correct LCDS24 control bit name 89 Added Table 6 33 and moved P8 2 to P8 5 from Table 6 32 to insert correct LCDS20 ...

Page 5: ...P430FG4616 92 4 1 TA3 TB7 12 3 2 2 1 A0 B0 80 ZQW 113 PZ 100 MSP430CG4619 120 4 TA3 TB7 12 3 2 2 1 A0 B0 80 ZQW 113 PZ 100 MSP430CG4618 116 8 TA3 TB7 12 3 2 2 1 A0 B0 80 ZQW 113 PZ 100 MSP430CG4617 92 8 TA3 TB7 12 3 2 2 1 A0 B0 80 ZQW 113 PZ 100 MSP430CG4616 92 4 TA3 TB7 12 3 2 2 1 A0 B0 80 ZQW 113 1 For the most current device package and ordering information for all available devices see the Pac...

Page 6: ... S8 P10 0 S9 P9 7 S10 P9 6 S11 P9 5 S12 P9 4 S13 P2 4 UCA0TXD P2 5 UCA0RXD P2 6 CAOUT P2 7 ADC12CLK DMAE0 P3 0 UCB0STE P3 1 UCB0SIMO UCB0SDA P3 2 UCB0SOMI UCB0SCL P3 3 UCB0CLK P3 4 TB3 P3 5 TB4 P3 6 TB5 P3 7 TB6 P4 0 UTXD1 P4 1 URXD1 DVSS2 DVCC2 LCDCAP R33 P5 7 R23 P5 6 LCDREF R13 P5 5 R03 P5 4 COM3 P5 3 COM2 P5 2 COM1 COM0 P4 2 STE1 S39 P8 6 S19 P8 3 S22 P8 2 S23 P7 0 UCA0STE S33 P7 1 UCA0SIMO S3...

Page 7: ...5 4 P5 2 N A MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 www ti com SLAS508J APRIL 2006 REVISED JUNE 2015 Figure 4 2 shows the pinout for the 113 pin ZQW package This figure shows only the default pin assignments for all pin assignments see Table 4 1 N A Not Assigned All unassigned ball locations on the ZQW package should be electrically ...

Page 8: ...the ADC 10 E2 I O DAC0 DAC12 0 output VREF Internal reference voltage negative terminal for the ADC reference voltage 11 E4 I VeREF External applied reference voltage negative terminal for the ADC reference voltage P5 1 General purpose digital I O S0 1 LCD segment output 0 12 F1 I O A12 Analog input A12 for 12 bit ADC DAC1 DAC12 1 output P5 0 General purpose digital I O S1 1 LCD segment output 1 1...

Page 9: ...al purpose digital I O 26 M2 I O S14 LCD segment output 14 P9 2 General purpose digital I O 27 K2 I O S15 LCD segment output 15 P9 1 General purpose digital I O 28 L3 I O S16 LCD segment output 16 P9 0 General purpose digital I O 29 M3 I O S17 LCD segment output 17 P8 7 General purpose digital I O 30 H4 I O S18 LCD segment output 18 P8 6 General purpose digital I O 31 L4 I O S19 LCD segment output...

Page 10: ... P4 6 General purpose digital I O UCA0TXD 47 M9 I O Transmit data out USCI_A0 in UART or IrDA mode S35 LCD segment output 35 P4 5 General purpose digital I O UCLK1 External clock input USART1 in UART or SPI mode 48 L9 I O Clock output USART1 in SPI MODE S36 LCD segment output 36 P4 4 General purpose digital I O SOMI1 49 H7 I O Slave out master in of USART1 in SPI mode S37 LCD segment output 37 P4 ...

Page 11: ...CI3A CCI3B input compare Out3 output P3 3 General purpose digital I O 68 E11 I O UCB0CLK External clock input USCI_B0 in UART or SPI mode Clock output USCI_B0 in SPI mode P3 2 General purpose digital I O UCB0SOMI 69 F9 I O Slave out master in of USCI_B0 in SPI mode UCB0SCL I2 C clock USCI_B0 in I2 C mode P3 1 General purpose digital I O UCB0SIMO 70 D12 I O Slave in master out of USCI_B0 in SPI mod...

Page 12: ...al oscillator XT2 XT2IN 89 B6 I Input port for crystal oscillator XT2 Only standard crystals can be connected TDO Test data output port TDO TDI data output 90 A6 I O TDI Programming data input terminal TDI Test data input 91 D6 I TCLK Test clock input The device protection fuse is connected to TDI TCLK TMS 92 E6 I Test mode select TMS is used as an input port for device programming and test TCK 93...

Page 13: ...ned ball locations on the ZQW package should be electrically tied to the ground Not Assigned G8 H8 supply The shortest ground return path to the device should be established to ball location J4 J9 B3 DVSS1 L2 L11 M1 M12 Copyright 2006 2015 Texas Instruments Incorporated Terminal Configuration and Functions 13 Submit Documentation Feedback Product Folder Links MSP430FG4619 MSP430FG4618 MSP430FG4617...

Page 14: ... safe manufacturing with a standard ESD control process Pins listed as 250 V may actually have higher performance 5 3 Recommended Operating Conditions Typical values are specified at VCC 3 3 V and TA 25 C unless otherwise noted MIN NOM MAX UNIT During program execution 1 1 8 3 6 AVCC DVCC1 2 VCC During flash memory programming FG461x VCC Supply voltage 2 7 3 6 V AVCC DVCC1 2 VCC 1 During program e...

Page 15: ...4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 www ti com SLAS508J APRIL 2006 REVISED JUNE 2015 Figure 5 1 Frequency vs Supply Voltage Copyright 2006 2015 Texas Instruments Incorporated Specifications 15 Submit Documentation Feedback Product Folder Links MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP43...

Page 16: ...0 TA 40 C 1 5 5 5 TA 25 C 1 5 5 5 VCC 2 2 V Low power mode LPM3 TA 60 C 2 8 7 0 f MCLK f SMCLK 0 MHz TA 85 C 7 2 17 0 f ACLK 32768 Hz SCG0 1 I LPM3 µA Basic Timer1 enabled ACLK selected TA 40 C 2 5 6 5 LCD_A enabled LCDCPEN 0 TA 25 C 2 5 6 5 4 mux mode fLCD f ACLK 32 3 4 2 VCC 3 V TA 60 C 3 2 8 0 TA 85 C 8 5 20 0 TA 40 C 0 13 1 0 TA 25 C 0 22 1 0 VCC 2 2 V TA 60 C 0 9 2 5 Low power mode LPM4 TA 85...

Page 17: ...o board thermal characterization parameter 21 2 C W ΨJT Junction to top thermal characterization parameter 0 2 C W 1 The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC standard High K board as specified in JESD51 7 in an environment described in JESD51 2a 2 The junction to case top thermal resistance is obtained by simulating a cold plate tes...

Page 18: ...e met It may be set even with trigger signals shorter than t int 5 8 Leakage Current Ports P1 to P10 1 over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS MIN MAX UNIT V Px y 2 Ilkg Px y Leakage current Port Px VCC 2 2 V 3 V 50 nA 1 10 0 y 7 1 The leakage current is measured with VSS or VCC applied to the corresponding pins ...

Page 19: ...K P1 4 TBCLK SMCLK CL 20 pF MHz f ACLK P1 5 TACLK ACLK VCC 3 V DC 12 f ACLK f LFXT1 f XT1 40 60 P1 5 TACLK ACLK f ACLK f LFXT1 f LF 30 70 CL 20 pF VCC 2 2 V 3 V f ACLK f LFXT1 50 f MCLK f XT1 40 60 Duty cycle of output P1 1 TA0 MCLK t Xdc 50 50 frequency CL 20 pF VCC 2 2 V 3 V f MCLK f DCOCLK 50 15 ns 15 ns f SMCLK f XT2 40 60 P1 4 TBCLK SMCLK 50 50 CL 20 pF VCC 2 2 V 3 V f SMCLK f DCOCLK 50 15 ns...

Page 20: ...T 85 C A MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 SLAS508J APRIL 2006 REVISED JUNE 2015 www ti com 5 11 Typical Characteristics Outputs over recommended ranges of supply voltage and operating free air temperature unless otherwise noted Figure 5 2 Typical Low Level Output Current vs Typical Low Figure 5 3 Typical Low Level Output Curren...

Page 21: ...cy 1 1 kHz VLCDx 0000 VCC VLCDx 0001 2 60 VLCDx 0010 2 66 VLCDx 0011 2 72 VLCDx 0100 2 78 VLCDx 0101 2 84 VLCDx 0110 2 90 VLCDx 0111 2 96 VLCD LCD voltage 4 V VLCDx 1000 3 02 VLCDx 1001 3 08 VLCDx 1010 3 14 VLCDx 1011 3 20 VLCDx 1100 3 26 VLCDx 1101 3 32 VLCDx 1110 3 38 VLCDx 1111 3 44 3 60 RLCD VLCD 3 V CPEN 1 LCD driver output impedance 2 2 V 10 kΩ VLCDx 1000 ILOAD 10 µΑ 1 Refer to the supply cu...

Page 22: ...TA 85 C Common mode input VIC CAON 1 2 2 V 3 V 0 VCC 1 V voltage range Vp VS Offset voltage 2 2 2 V 3 V 30 30 mV Vhys Input hysteresis CAON 1 2 2 V 3 V 0 0 7 1 4 mV 2 2 V 160 210 300 TA 25 C ns Overdrive 10 mV without filter CAF 0 3 V 80 150 240 t response LH 2 2 V 1 4 1 9 3 4 TA 25 C µs Overdrive 10 mV without filter CAF 1 3 V 0 9 1 5 2 6 t response HL 2 2 V 130 210 300 TA 25 C ns Overdrive 10 mV...

Page 23: ...MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 www ti com SLAS508J APRIL 2006 REVISED JUNE 2015 5 16 Typical Characteristics Comparator_A Figure 5 6 Reference Voltage vs Free Air Temperature Figure 5 7 Reference Voltage vs Free Air Temperature Figure 5 8 Block Diagram of Comparator_A Module Figure 5 9 Overdrive Definition Copyright 2006 2015 Texas Instru...

Page 24: ...at RST NMI pin to accepted t reset 2 µs reset internally VCC 2 2 V 3 V 1 The current consumption of the brownout module is already included in the ICC current consumption data 2 The voltage level V B_IT Vhys B_IT 1 89 V 3 During power up the CPU begins code execution following a period of td BOR after VCC V B_IT Vhys B_IT The default FLL settings must not be changed until VCC VCC min where VCC min...

Page 25: ... s see Figure 5 13 external voltage VLD 15 4 4 20 mV applied on A7 VLD 1 1 8 1 9 2 05 VLD 2 1 94 2 1 2 23 VLD 3 2 05 2 2 2 35 VLD 4 2 14 2 3 2 46 VLD 5 2 24 2 4 2 58 VLD 6 2 33 2 5 2 69 VLD 7 2 46 2 65 2 84 VCC dt 3 V s see Figure 5 13 VLD 8 2 58 2 8 2 97 V SVS_IT V VLD 9 2 69 2 9 3 10 VLD 10 2 83 3 05 3 26 VLD 11 2 94 3 2 3 39 VLD 12 3 11 3 35 3 58 2 VLD 13 3 24 3 5 3 73 2 VLD 14 3 43 3 7 2 3 96 ...

Page 26: ...uit is Active From VLD to VCC V B_IT SVSOut Vhys B_IT MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 SLAS508J APRIL 2006 REVISED JUNE 2015 www ti com Figure 5 13 SVS Reset SVSR vs Supply Voltage Figure 5 14 VCC drop with a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal 26 Specifications Copyright 2006 2015 Texas In...

Page 27: ...Hz 3 V 1 3 2 2 3 5 2 2 V 9 15 5 25 f DCO 27 FN_8 FN_4 0 FN_3 1 FN_2 x DCOPLUS 1 MHz 3 V 10 3 17 9 28 5 2 2 V 1 8 2 8 4 2 f DCO 2 FN_8 0 FN_4 1 FN_3 FN_2 x DCOPLUS 1 MHz 3 V 2 1 3 4 5 2 2 2 V 13 5 21 5 33 f DCO 27 FN_8 0 FN_4 1 FN_3 FN_2 x DCOPLUS 1 MHz 3 V 16 26 6 41 2 2 V 2 8 4 2 6 2 f DCO 2 FN_8 1 FN_4 1 FN_3 FN_2 x DCOPLUS 1 MHz 3 V 4 2 6 3 9 2 2 2 V 21 32 46 f DCO 27 FN_8 1 FN_4 1 FN_3 FN_2 x ...

Page 28: ...S n S tepsize R atio betw een D C O Taps Min Max 1 07 1 06 MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 SLAS508J APRIL 2006 REVISED JUNE 2015 www ti com Figure 5 16 DCO Tap Step Size Figure 5 17 Five Overlapping DCO Ranges Controlled by FN_x Bits 28 Specifications Copyright 2006 2015 Texas Instruments Incorporated Submit Documentation Feed...

Page 29: ...the JTAG header to support the serial programming adapter as shown in other documentation This signal is no longer required for the serial programming adapter 3 TI recommends external capacitance for precision real time clock applications OSCCAPx 0h 4 Applies only when using an external logic level clock source XTS_FLL must be set Not applicable when using a crystal or resonator 5 21 Crystal Oscil...

Page 30: ...commended ranges of supply voltage and operating free air temperature unless otherwise noted see Figure 5 20 and Figure 5 21 PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT STE lead time tSTE LEAD 2 2 V 3 V 50 ns STE low to clock STE lag time tSTE LAG 2 2 V 3 V 10 ns Last clock to STE high STE access time tSTE ACC 2 2 V 3 V 50 ns STE low to SOMI data out STE disable time tSTE DIS 2 2 V 3 V 50 ns ST...

Page 31: ... MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 www ti com SLAS508J APRIL 2006 REVISED JUNE 2015 Figure 5 18 SPI Master Mode CKPH 0 Figure 5 19 SPI Master Mode CKPH 1 Copyright 2006 2015 Texas Instruments Incorporated Specifications 31 Submit Documentation Feedback Product Folder Links MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP4...

Page 32: ...SP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 SLAS508J APRIL 2006 REVISED JUNE 2015 www ti com Figure 5 20 SPI Slave Mode CKPH 0 Figure 5 21 SPI Slave Mode CKPH 1 32 Specifications Copyright 2006 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG...

Page 33: ... STOP 2 2 V 3 V 4 µs 2 2 V 50 150 600 Pulse duration of spikes suppressed by tSP ns input filter 3 V 50 100 600 Figure 5 22 I2 C Mode Timing 5 26 USART1 over recommended ranges of supply voltage and operating free air temperature unless otherwise noted 1 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC 2 2 V SYNC 0 UART mode 200 430 800 t τ USART1 deglitch time ns VCC 3 V SYNC 0 UART mode 150 280 50...

Page 34: ...trol bit unless a conversion is active The REFON bit enables to settle the built in reference before starting an A D conversion 5 28 12 Bit ADC External Reference over recommended ranges of supply voltage and operating free air temperature unless otherwise noted 1 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Positive external reference VeREF VeREF VREF VeREF 2 1 4 VAVCC V voltage input Negative exte...

Page 35: ... Analog input voltage 1 25 V VCC 3 V 2 REF2_5V 1 IVREF 100 µA 900 µA Load current regulation VREF IDL VREF CVREF 5 µF Ax 0 5 VREF VCC 3 V 20 ns terminal Error of conversion result 1 LSB REFON 1 CVREF Capacitance at pin VREF 1 VCC 2 2 V 3 V 5 10 µF 0 mA IVREF IVREF max Temperature coefficient of built IVREF is a constant in the range of TREF VCC 2 2 V 3 V 100 ppm C in reference 0 mA IVREF 1 mA Sett...

Page 36: ...Internal Reference V REF V or V REF eREF V V REF eREF MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 SLAS508J APRIL 2006 REVISED JUNE 2015 www ti com Figure 5 24 Supply Voltage and Reference Voltage Design VREF VeREF External Supply Figure 5 25 Supply Voltage and Reference Voltage Design VREF VeREF AVSS Internally Connected 36 Specifications...

Page 37: ...roximately ten Tau τ are needed to get an error of less than 0 5 LSB tSample ln 2n 1 RS RI x CI 800 ns where n ADC resolution 12 RS external source resistance 5 31 12 Bit ADC Linearity Parameters over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 1 4 V VeREF VREF VeREF min 1 6 V 2 Integral linearity EI ...

Page 38: ...ture sensor 3 The typical equivalent impedance of the sensor is 51 kΩ The sample time required includes the sensor on time tSENSOR on 4 No additional current is needed The VMID is used during sampling 5 The on time tVMID on is included in the sampling time tVMID sample no additional on time is needed 5 33 12 Bit DAC Supply Specifications over recommended ranges of supply voltage and operating free...

Page 39: ... error temperature coefficient 1 2 2 V 3 V 30 µV C VREF 1 5 V 2 2 V EG Gain error 1 3 5 FSR VREF 2 5 V 3 V ppm of dE G dT Gain temperature coefficient 1 2 2 V 3 V 10 FSR C DAC12AMPx 2 100 tOffset_Cal Time for offset calibration 3 DAC12AMPx 3 5 2 2 V 3 V 32 ms DAC12AMPx 4 6 7 6 1 Parameters calculated from the best fit curve from 0x0A to 0xFFF The best fit curve method is used to deliver coefficien...

Page 40: ...INL Integral Nonlinearity Error LSB MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 SLAS508J APRIL 2006 REVISED JUNE 2015 www ti com Figure 5 27 Typical INL Error vs Digital Input Data Figure 5 28 Typical DNL Error vs Digital Input Data 40 Specifications Copyright 2006 2015 Texas Instruments Incorporated Submit Documentation Feedback Product ...

Page 41: ...amplifier Figure 5 29 DAC12_x Output Resistance Tests 5 36 12 Bit DAC Reference Input Specifications over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT DAC12IR 0 1 2 AVCC 3 AVCC 0 2 Reference input voltage VeREF 2 2 V 3 V V range DAC12IR 1 3 4 AVCC AVCC 0 2 DAC12_0 IR DAC12_1 IR 0 20 MΩ DAC12_0 IR 1 DAC...

Page 42: ...DAC12AMPx 0 7 6 12 DAC12AMPx 2 100 200 DAC12_xDAT tS FS Settling time full scale DAC12AMPx 3 5 2 2 V 3 V 40 80 µs 80h F7Fh 80h DAC12AMPx 4 6 7 15 30 DAC12AMPx 2 5 DAC12_xDAT tS C C Settling time code to code 3F8h 408h 3F8h DAC12AMPx 3 5 2 2 V 3 V 2 µs BF8h C08h BF8h DAC12AMPx 4 6 7 1 DAC12AMPx 2 0 05 0 12 DAC12_xDAT SR Slew rate DAC12AMPx 3 5 2 2 V 3 V 0 35 0 7 V µs 80h F7Fh 80h 2 DAC12AMPx 4 6 7 ...

Page 43: ...andwidth DAC12AMPx 5 6 DAC12SREFx 2 BW 3dB VDC 1 5 V VAC 0 1 VPP 2 2 V 3 V 180 kHz DAC12IR 1 DAC12_xDAT 800h see Figure 5 32 DAC12AMPx 7 DAC12SREFx 2 550 DAC12IR 1 DAC12_xDAT 800h DAC12_0DAT 800h No Load DAC12_1DAT 80h F7Fh RLoad 3 kΩ 80 Channel to channel fDAC12_1OUT 10 kHz at 50 50 duty cycle crosstalk 2 2 V 3 V dB DAC12_0DAT 80h F7Fh RLoad 3 kΩ see Figure 5 33 1 DAC12_1DAT 800h No Load 80 fDAC1...

Page 44: ...leakage current I P 1 2 nA TA 55 to 85 C 20 5 20 Fast Mode 50 80 Medium Mode fV I P 1 kHz 140 Slow Mode Vn Voltage noise density I P nV HZ Fast Mode 30 Medium Mode fV I P 10 kHz 50 Slow Mode 65 VIO Offset voltage I P 2 2 V 3 V 10 mV Offset temperature drift I P 3 2 2 V 3 V 10 µV C Offset voltage drift with supply 0 3 V VIN VCC 0 3 V 2 2 V 3 V 1 5 mV V I P ΔVCC 10 TA 25 C Fast Mode ISOURCE 500 µA 2...

Page 45: ...TER TEST CONDITIONS VCC MIN TYP MAX UNIT Fast Mode 1 2 SR Slew rate Medium Mode 0 8 V µs Slow Mode 0 3 Open loop voltage gain 100 dB φm Phase margin CL 50 pF 60 deg Gain margin CL 50 pF 20 dB 2 2 Noninverting Fast Mode RL 47 kΩ CL 50 pF Gain bandwidth product 1 4 GBW see Figure 5 35 and 2 2 V 3 V MHz Noninverting Medium Mode RL 300 kΩ CL 50 pF Figure 5 36 0 5 Noninverting Slow Mode RL 300 kΩ CL 50...

Page 46: ...faster 5 44 Operational Amplifier OA Feedback Network Inverting Amplifier Mode OAFCx 6 1 over recommended operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT OAFBRx 1 0 371 0 335 0 298 OAFBRx 2 1 031 1 002 0 972 OAFBRx 3 1 727 1 668 1 609 G Gain OAFBRx 4 2 2 V 3 V 3 142 3 00 2 856 OAFBRx 5 4 581 4 33 4 073 OAFBRx 6 7 529 6 97 6 379 OAFBRx 7 17 040 1...

Page 47: ...ry erased 2 All flash memory erased 3 The cumulative program time must not be exceeded during a block write operation This parameter is only relevant if the block write feature is used 4 These values are hardwired into the flash controller state machine tFTG 1 fFTG 5 46 JTAG Interface over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST...

Page 48: ...unction with seven addressing modes for source operand and four addressing modes for destination operand The CPU is integrated with 16 registers that provide reduced instruction execution time The register to register operation execution time is one cycle of the CPU clock Four of the registers R0 to R3 are dedicated as program counter stack pointer status register and constant generator respective...

Page 49: ...R4 R5 R4 R5 R5 Single operands destination only CALL R8 PC TOS R8 PC Relative jump un conditional JNE Jump on equal bit 0 Table 6 2 Address Mode Descriptions ADDRESS MODE S 1 D 1 SYNTAX EXAMPLE OPERATION Register MOV Rs Rd MOV R10 R11 R10 R11 Indexed MOV X Rn Y Rm MOV 2 R5 6 R6 M 2 R5 M 6 R6 Symbolic PC relative MOV EDE TONI M EDE M TONI Absolute MOV MEM TCDAT M MEM M TCDAT Indirect MOV Rn Y Rm MO...

Page 50: ...is disabled FLL loop control remains active Low power mode 1 LPM1 CPU is disabled FLL loop control is disabled ACLK and SMCLK remain active MCLK is disabled Low power mode 2 LPM2 CPU is disabled MCLK FLL loop control and DCOCLK are disabled DCO DC generator remains enabled ACLK remains active Low power mode 3 LPM3 CPU is disabled MCLK FLL loop control and DCOCLK are disabled DCO DC generator is di...

Page 51: ...A3 TACCR0 CCIFG0 4 Maskable 0FFECh 22 TACCR1 CCIFG1 and TACCR2 CCIFG2 Timer_A3 Maskable 0FFEAh 21 TAIFG 1 4 I O Port P1 Eight Flags P1IFG 0 to P1IFG 7 1 4 Maskable 0FFE8h 20 USART1 Receive URXIFG1 Maskable 0FFE6h 19 USART1 Transmit UTXIFG1 Maskable 0FFE4h 18 I O Port P2 Eight Flags P2IFG 0 to P2IFG 7 1 4 Maskable 0FFE2h 17 Basic Timer 1 RTC BTIFG Maskable 0FFE0h 16 DMA DMA0IFG DMA1IFG DMA2IFG 1 4 ...

Page 52: ... by POR SFR bit is not present in device 6 5 1 Interrupt Enable 1 and 2 WDTIE Watchdog timer interrupt enable Inactive if watchdog mode is selected Active if watchdog timer is configured as a general purpose timer OFIE Oscillator fault interrupt enable NMIIE Nonmaskable interrupt enable ACCVIE Flash access violation interrupt enable UCA0RXIE USCI_A0 receive interrupt enable UCA0TXIE USCI_A0 transm...

Page 53: ...scillator fault NMIIFG Set by the RST NMI pin UCA0RXIFG USCI_A0 receive interrupt flag UCA0TXIFG USCI_A0 transmit interrupt flag UCB0RXIFG USCI_B0 receive interrupt flag UCB0TXIFG USCI_B0 transmit interrupt flag URXIFG0 USART1 UART and SPI receive flag UTXIFG0 USART1 UART and SPI transmit flag BTIFG Basic timer flag 6 5 3 Module Enable Registers 1 and 2 URXE1 USART1 UART mode receive enable UTXE1 ...

Page 54: ...bit 01FFh 0100h 01FFh 0100h 01FFh 0100h 01FFh 0100h 8 bit 0FFh 010h 0FFh 010h 0FFh 010h 0FFh 010h 8 bit SFR 0Fh 00h 0Fh 00h 0Fh 00h 0Fh 00h Table 6 5 MSP430CG461x Memory Organization MSP430CG4616 MSP430CG4617 MSP430CG4618 MSP430CG4619 Memory Size 92KB 92KB 116KB 120KB Main interrupt vector ROM 0FFFFh 0FFC0h 0FFFFh 0FFC0h 0FFFFh 0FFC0h 0FFFFh 0FFC0h Main code memory ROM 018FFFh 002100h 019FFFh 0031...

Page 55: ...s of information memory A and B of 128 bytes each Each segment in main memory is 512 bytes in size Segments 0 to n may be erased in one step or each segment may be individually erased Segments A and B can be erased individually or as a group with segments 0 n Segments A and B are also called information memory New devices may have some bytes programmed in the information memory needed for test dur...

Page 56: ...ine when VCC reaches VCC min 6 9 4 Digital I O There are ten 8 bit I O ports implemented ports P1 through P10 All individual I O bits are independently programmable Any combination of input output and interrupt conditions is possible Edge selectable interrupt input capability for all the eight bits of ports P1 and P2 Read and write access to port control registers is supported by all instructions ...

Page 57: ...igned multiplication as well as signed and unsigned multiply and accumulate operations The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers No additional clock cycles are required 6 9 11 Timer_A3 Timer_A3 is a 16 bit timer counter with three capture compare registers Timer_A3 can support multiple capture compares PWM outputs and i...

Page 58: ...mer NA SMCLK SMCLK 83 B8 P1 4 TBCLK INCLK 78 D8 P2 1 TB0 CCI0A 78 D8 P2 1 78 D8 P2 1 TB0 CCI0B ADC12 internal CCR0CCR0 TB0TB0 DVSS GND DVCC VCC 77 E8 P2 2 TB1 CCI1A 77 E8 P2 2 77 E8 P2 2 TB1 CCI1B ADC12 internal CCR1 TB1 DVSS GND DVCC VCC 76 A11 P2 3 TB2 CCI2A 76 A11 P2 3 76 A11 P2 3 TB2 CCI2B CCR2 TB2 DVSS GND DVCC VCC 67 E12 P3 4 TB3 CCI3A 67 E12 P3 4 67 E12 P3 4 TB3 CCI3B CCR3 TB3 DVSS GND DVCC...

Page 59: ...430xG461x has three configurable low current general purpose operational amplifiers Each OA input and output terminal is software selectable and offer a flexible choice of connections for various applications The OA op amps primarily support front end analog signal conditioning before analog to digital conversion Table 6 8 OA Signal Connections INPUT PIN OUTPUT PIN DEVICE INPUT MODULE INPUT MODULE...

Page 60: ... TAR 0170h Capture compare control 2 TACCTL2 0166h Capture compare control 1 TACCTL1 0164h Capture compare control 0 TACCTL0 0162h Timer_A control TACTL 0160h Timer_A interrupt vector TAIV 012Eh Hardware Multiplier Sum extend SUMEXT 013Eh Result high word RESHI 013Ch Result low word RESLO 013Ah Second operand OP2 0138h Multiply signed accumulate operand1 MACS 0136h Multiply accumulate operand1 MAC...

Page 61: ...n memory 3 ADC12MEM3 0146h Conversion memory 2 ADC12MEM2 0144h Conversion memory 1 ADC12MEM1 0142h Conversion memory 0 ADC12MEM0 0140h Interrupt vector word register ADC12IV 01A8h Inerrupt enable register ADC12IE 01A6h Inerrupt flag register ADC12IFG 01A4h Control register 1 ADC12CTL1 01A2h Control register 0 ADC12CTL0 01A0h DAC12 DAC12_1 data DAC12_1DAT 01CAh DAC12_1 control DAC12_1CTL 01C2h DAC1...

Page 62: ...emory control register 5 ADC12MCTL5 085h ADC memory control register 4 ADC12MCTL4 084h ADC memory control register 3 ADC12MCTL3 083h ADC memory control register 2 ADC12MCTL2 082h ADC memory control register 1 ADC12MCTL1 081h ADC memory control register 0 ADC12MCTL0 080h USART1 Transmit buffer U1TXBUF 07Fh Receive buffer U1RXBUF 07Eh Baud rate U1BR1 07Dh Baud rate U1BR0 07Ch Modulation control U1MC...

Page 63: ...tion P10DIR 00Dh Port P10 output P10OUT 00Bh Port P10 input P10IN 009h Port P9 Port P9 selection P9SEL 00Eh Port P9 direction P9DIR 00Ch Port P9 output P9OUT 00Ah Port P9 input P9IN 008h Port P8 Port P8 selection P8SEL 03Fh Port P8 direction P8DIR 03Dh Port P8 output P8OUT 03Bh Port P8 input P8IN 039h Port P7 Port P7 selection P7SEL 03Eh Port P7 direction P7DIR 03Ch Port P7 output P7OUT 03Ah Port ...

Page 64: ...024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h Special functions SFR module enable 2 ME2 005h SFR module enable 1 ME1 004h SFR interrupt flag 2 IFG2 003h SFR interrupt flag 1 IFG1 002h SFR interrupt enable 2 IE2 001h SFR interrupt enable 1 IE1 000h 64 Detailed Description Copyright 2006 2015 Texas Instruments Incorporated Submi...

Page 65: ...ES x P1IFG x P1IE x MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 www ti com SLAS508J APRIL 2006 REVISED JUNE 2015 6 10 Input Output Schematics 6 10 1 Port P1 P1 0 to P1 5 Input Output With Schmitt Trigger Copyright 2006 2015 Texas Instruments Incorporated Detailed Description 65 Submit Documentation Feedback Product Folder Links MSP430FG46...

Page 66: ... P1 1 I O I 0 O 1 0 Timer_A3 CCI0B 0 1 MCLK 1 1 P1 2 TA1 2 P1 2 I O I 0 O 1 0 Timer_A3 CCI1A 0 1 Timer_A3 TA1 1 1 P1 3 TBOUTH SVSOUT 3 P1 3 I O I 0 O 1 0 Timer_B7 TBOUTH 0 1 SVSOUT 1 1 P1 4 TBCLK SMCLK 4 P1 4 I O I 0 O 1 0 Timer_B7 TBCLK 0 1 SMCLK 1 1 P1 5 TACLK ACLK 5 P1 5 I O I 0 O 1 0 Timer_A3 TACLK 0 1 ACLK 1 1 66 Detailed Description Copyright 2006 2015 Texas Instruments Incorporated Submit D...

Page 67: ...430CG4616 www ti com SLAS508J APRIL 2006 REVISED JUNE 2015 6 10 2 Port P1 P1 6 P1 7 Input Output With Schmitt Trigger Table 6 12 Port P1 P1 6 and P1 7 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P1 x x FUNCTION CAPD x P1DIR x P1SEL x P1 6 CA0 6 P1 6 I O 0 I 0 O 1 0 CA0 1 X X P1 7 CA1 7 P1 7 I O 0 I 0 O 1 0 CA1 1 X X 1 X don t care Copyright 2006 2015 Texas Instruments Incorporated Detailed De...

Page 68: ...S x P2IFG x P2IE x MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 SLAS508J APRIL 2006 REVISED JUNE 2015 www ti com 6 10 3 Port P2 P2 0 to P2 3 P2 6 to P2 7 Input Output With Schmitt Trigger 68 Detailed Description Copyright 2006 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links MSP430FG4619 MSP430FG4618 M...

Page 69: ...CCI0B 0 1 Timer_B7 TB0 1 1 1 P2 2 TB1 2 P2 2 I O I 0 O 1 0 Timer_B7 CCI1A and Timer_B7 CCI1B 0 1 Timer_B7 TB1 1 1 1 P2 3 TB3 3 P2 3 I O I 0 O 1 0 Timer_B7 CCI2A and Timer_B7 CCI2B 0 1 Timer_B7 TB3 1 1 1 P2 6 CAOUT 6 P2 6 I O I 0 O 1 0 CAOUT 1 1 P2 7 ADC12CLK DMAE0 7 P2 7 I O I 0 O 1 0 ADC12CLK 1 1 DMAE0 0 1 1 Setting TBOUTH causes all Timer_B outputs to be set to high impedance Copyright 2006 2015...

Page 70: ...E 2015 www ti com 6 10 4 Port P2 P2 4 to P2 5 Input Output With Schmitt Trigger Table 6 14 Port P2 P2 4 and P2 5 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P2 x x FUNCTION P2DIR x P2SEL x P2 4 I O I 0 O 1 0 P2 4 UCA0TXD 4 USCI_A0 UCA0TXD 2 X 1 P2 5 I O I 0 O 1 0 P2 5 UCA0RXD 5 USCI_A0 UCA0RXD 2 X 1 1 X don t care 2 When in USCI mode P2 4 is set to output P2 5 is set to input 70 Detailed Desc...

Page 71: ... CONTROL BITS OR SIGNALS 1 PIN NAME P3 x x FUNCTION P3DIR x P3SEL x P3 0 UCB0STE 0 P3 0 I O I 0 O 1 0 UCB0STE 2 X 1 P3 1 UCB0SIMO UCB0SDA 1 P3 1 I O I 0 O 1 0 UCB0SIMO UCB0SDA 2 3 X 1 P3 2 UCB0SOMI UCB0SCL 2 P3 2 I O I 0 O 1 0 UCB0SOMI UCB0SCL 2 3 X 1 P3 3 UCB0CLK 3 P3 3 I O I 0 O 1 0 UCB0CLK 2 X 1 1 X don t care 2 The pin direction is controlled by the USCI module 3 If the I2 C functionality is s...

Page 72: ... P3 x x FUNCTION P3DIR x P3SEL x P3 4 TB3 4 P3 4 I O I 0 O 1 0 Timer_B7 CCI3A and Timer_B7 CCI3B 0 1 Timer_B7 TB3 1 1 1 P3 5 TB4 5 P3 5 I O I 0 O 1 0 Timer_B7 CCI4A and Timer_B7 CCI4B 0 1 Timer_B7 TB4 1 1 1 P3 6 TB5 6 P3 6 I O I 0 O 1 0 Timer_B7 CCI5A and Timer_B7 CCI5B 0 1 Timer_B7 TB5 1 1 1 P3 7 TB6 7 P3 7 I O I 0 O 1 0 Timer_B7 CCI6A and Timer_B7 CCI6B 0 1 Timer_B7 TB6 1 1 1 1 Setting TBOUTH ca...

Page 73: ...P4 0 to P4 1 Input Output With Schmitt Trigger Table 6 17 Port P4 P4 0 to P4 1 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P4 x x FUNCTION P4DIR x P4SEL x P4 0 UTXD1 0 P4 0 I O I 0 O 1 0 USART1 UTXD1 2 X 1 P4 1 URXD1 1 P4 1 I O I 0 O 1 0 USART1 URXD1 2 X 1 1 X don t care 2 When in USART1 mode P4 0 is set to output P4 1 is set to input Copyright 2006 2015 Texas Instruments Incorporated Detaile...

Page 74: ...ith Schmitt Trigger Table 6 18 Port P4 P4 2 to P4 5 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P4 x x FUNCTION P4DIR x P4SEL x LCDS36 P4 2 I O I 0 O 1 0 0 P4 2 STE1 S39 2 USART1 STE1 X 1 0 S39 X X 1 P4 3 I O I 0 O 1 0 0 P4 3 SIMO S38 3 USART1 SIMO1 2 X 1 0 S38 X X 1 P4 4 I O I 0 O 1 0 0 P4 4 SOMI S37 4 USART1 SOMI1 2 X 1 0 S37 X X 1 P4 5 I O I 0 O 1 0 0 P4 5 SOMI S36 5 USART1 UCLK1 2 X 1 0 S...

Page 75: ... x LCDS32 P4 6 I O I 0 O 1 0 0 P4 6 UCA0TXD S35 6 USCI_A0 UCA0TXD 2 X 1 0 S35 X X 1 P4 7 I O I 0 O 1 0 0 P4 7 UCA0RXD S34 7 USCI_A0 UCA0RXD 2 X 1 0 S34 X X 1 1 X don t care 2 When in USCI mode P4 6 is set to output P4 7 is set to input Copyright 2006 2015 Texas Instruments Incorporated Detailed Description 75 Submit Documentation Feedback Product Folder Links MSP430FG4619 MSP430FG4618 MSP430FG4617...

Page 76: ...NTROL BITS OR SIGNALS 1 PIN NAME P5 x x FUNCTION OAPx OA1 P5DIR x P5SEL x INCHx LCDS0 OANx OA1 P5 0 S1 A13 OA1I1 0 P5 0 I O I 0 O 1 0 X X 0 OAI11 0 X X 1 0 A13 2 X 1 13 X X S1 enabled X 0 X X 1 S1 disabled X 1 X X 1 1 X don t care 2 Setting the P5SEL x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals 76 Detailed Descripti...

Page 77: ...d DAC 12 1OPS 1 Note x 1 y 0 MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 www ti com SLAS508J APRIL 2006 REVISED JUNE 2015 6 10 10 Port P5 P5 1 Input Output With Schmitt Trigger Copyright 2006 2015 Texas Instruments Incorporated Detailed Description 77 Submit Documentation Feedback Product Folder Links MSP430FG4619 MSP430FG4618 MSP430FG461...

Page 78: ... X 0 DAC1 high impedance X X X 1 0 X DVSS X X X 1 1 X DAC1 output X X X 1 1 X A12 2 X 1 12 0 X 0 S0 enabled X 0 X 0 X 1 S0 disabled X 1 X 0 X 1 1 X don t care 2 Setting the P5SEL x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals 78 Detailed Description Copyright 2006 2015 Texas Instruments Incorporated Submit Documentati...

Page 79: ...P5 2 to P5 4 Input Output With Schmitt Trigger Table 6 22 Port P5 P5 2 to P5 4 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P5 x x FUNCTION P5DIR x P5SEL x P5 2 COM1 2 P5 2 I O I 0 O 1 0 COM1 X 1 P5 3 COM2 3 P5 3 I O I 0 O 1 0 COM2 X 1 P5 4 COM3 4 P5 4 I O I 0 O 1 0 COM3 X 1 1 X don t care Copyright 2006 2015 Texas Instruments Incorporated Detailed Description 79 Submit Documentation Feedback ...

Page 80: ...23 Port P5 P5 5 to P5 7 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P5 x x FUNCTION P5DIR x P5SEL x P5 5 R03 5 P5 5 I O I 0 O 1 0 R03 X 1 P5 6 LCDREF R13 6 P5 6 I O I 0 O 1 0 R13 or LCDREF 2 X 1 P5 7 R03 7 P5 7 I O I 0 O 1 0 R03 X 1 1 X don t care 2 External reference for the LCD_A charge pump is applied when VLCDREFx 01 Otherwise R13 is selected 80 Detailed Description Copyright 2006 2015 Te...

Page 81: ...LS 1 PIN NAME P6 x x FUNCTION OAPx OA0 OAPx OA1 P6DIR x P6SEL x INCHx OANx OA0 OANx OA1 P6 0 A0 OA0I0 0 P6 0 I O I 0 O 1 0 X X X OA0I0 0 X 0 X X A0 2 X 1 X X 0 P6 2 A2 OA0I1 2 P6 2 I O I 0 O 1 0 X X X OA0I1 0 X 1 X X A2 2 X 1 X X 2 P6 4 A4 OA1I0 4 P6 4 I O I 0 O 1 0 X X X OA1I0 0 X X 0 X A4 2 X 1 X X 4 1 X don t care 2 Setting the P6SEL x bit disables the output driver and the input Schmitt trigge...

Page 82: ...1 A1 OA0O 1 P6 1 I O I 0 O 1 0 X 0 X OA0O 2 X X 1 0 X A1 3 X 1 X 0 1 P6 3 A3 OA1O 3 P6 3 I O I 0 O 1 0 X 0 X OA1O 2 X X 1 0 X A3 3 X 1 X 0 3 P6 5 A5 OA2O 5 P6 5 I O I 0 O 1 0 X 0 X OA2O 2 X X 1 0 X A5 3 X 1 X 0 5 1 X don t care 2 Setting the OAADC1 bit or setting OAFCx 00 will cause the operational amplifier to be present at the pin as well as internally connected to the corresponding ADC12 input ...

Page 83: ... 0 DVSS Note x 6 Signal from or to ADC12 MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 www ti com SLAS508J APRIL 2006 REVISED JUNE 2015 6 10 15 Port P6 P6 6 Input Output With Schmitt Trigger Copyright 2006 2015 Texas Instruments Incorporated Detailed Description 83 Submit Documentation Feedback Product Folder Links MSP430FG4619 MSP430FG4618...

Page 84: ...P6 6 I O I 0 O 1 0 X 1 X X DAC0 high impedance X X X 0 0 X DVSS X X X 0 1 X DAC0 output X X X 0 1 X A6 2 X 1 6 X X X OA2I0 0 X 0 X X 0 1 X don t care 2 Setting the P6SEL x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals 84 Detailed Description Copyright 2006 2015 Texas Instruments Incorporated Submit Documentation Feedba...

Page 85: ...ux VLD 15 DVSS Note x 7 Signal from or to ADC12 MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 www ti com SLAS508J APRIL 2006 REVISED JUNE 2015 6 10 16 Port P6 P6 7 Input Output With Schmitt Trigger Copyright 2006 2015 Texas Instruments Incorporated Detailed Description 85 Submit Documentation Feedback Product Folder Links MSP430FG4619 MSP43...

Page 86: ... I O I 0 O 1 0 X 1 X DAC1 high impedance X X X 0 0 DVSS X X X 0 1 DAC1 output X X X 0 1 A7 2 X 1 7 X X SVSIN 2 0 1 0 1 X 1 X don t care 2 Setting the P6SEL x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals 86 Detailed Description Copyright 2006 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Fol...

Page 87: ... 3 y 30 31 32 33 MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 www ti com SLAS508J APRIL 2006 REVISED JUNE 2015 6 10 17 Port P7 P7 0 to P7 3 Input Output With Schmitt Trigger Copyright 2006 2015 Texas Instruments Incorporated Detailed Description 87 Submit Documentation Feedback Product Folder Links MSP430FG4619 MSP430FG4618 MSP430FG4617 MS...

Page 88: ...don t care 2 The pin direction is controlled by the USCI module Table 6 29 Port P7 P7 2 and P7 3 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P7 x x FUNCTION P7DIR x P7SEL x LCDS28 P7 2 UCA0SOMI S31 2 P7 2 I O I 0 O 1 0 0 USCI_A0 UCA0SOMI 2 X 1 0 S31 X X 1 P7 3 UCA0CLK S30 3 P7 3 I O I 0 O 1 0 0 USCI_A0 UCA0CLK 2 X 1 0 S30 X X 1 1 X don t care 2 The pin direction is controlled by the USCI modu...

Page 89: ... Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P7 x x FUNCTION P7DIR x P7SEL x LCDS28 P7 4 S29 4 P7 4 I O I 0 O 1 0 0 S29 X X 1 P7 5 S28 5 P7 5 I O I 0 O 1 0 0 S28 X X 1 1 X don t care Table 6 31 Port P7 P7 6 and P7 7 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P7 x x FUNCTION P7DIR x P7SEL x LCDS24 P7 6 S27 6 P7 6 I O I 0 O 1 0 0 S27 X X 1 P7 7 S26 7 P7 7 I O I 0 O 1 0 0 S26 X X 1 1 X don...

Page 90: ...ns CONTROL BITS OR SIGNALS 1 PIN NAME P8 x x FUNCTION P8DIR x P8SEL x LCDS16 P8 0 S18 0 P8 0 I O I 0 O 1 0 0 S18 X X 1 P8 1 S19 0 P8 0 I O I 0 O 1 0 0 S19 X X 1 1 X don t care Table 6 33 Port P8 P8 2 to P8 5 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P8 x x FUNCTION P8DIR x P8SEL x LCDS20 P8 2 S20 2 P8 2 I O I 0 O 1 0 0 S20 X X 1 P8 3 S21 3 P8 3 I O I 0 O 1 0 0 S21 X X 1 P8 4 S22 4 P8 4 I O ...

Page 91: ...CONTROL BITS OR SIGNALS 1 PIN NAME P8 x X FUNCTION P8DIR x P8SEL x LCDS24 P8 6 S24 6 P8 6 I O I 0 O 1 0 0 S24 X X 1 P8 7 S25 7 P8 7 I O I 0 O 1 0 0 S25 X X 1 1 X don t care Copyright 2006 2015 Texas Instruments Incorporated Detailed Description 91 Submit Documentation Feedback Product Folder Links MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG46...

Page 92: ...s CONTROL BITS OR SIGNALS 1 PIN NAME P9 x x FUNCTION P9DIR x P9SEL x LCDS16 P9 0 S17 0 P9 0 I O I 0 O 1 0 0 S17 X X 1 P9 1 S16 1 P9 1 I O I 0 O 1 0 0 S16 X X 1 1 X don t care Table 6 36 Port P9 P9 2 to P9 5 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P9 x x FUNCTION P9DIR x P9SEL x LCDS12 P9 2 S15 2 P9 2 I O I 0 O 1 0 0 S15 X X 1 P9 3 S14 3 P9 3 I O I 0 O 1 0 0 S14 X X 1 P9 4 S13 4 P9 4 I O I...

Page 93: ...CONTROL BITS OR SIGNALS 1 PIN NAME P9 x x FUNCTION P9DIR x P9SEL x LCDS8 P9 6 S11 6 P9 6 I O I 0 O 1 0 0 S11 X X 1 P9 7 S10 7 P9 7 I O I 0 O 1 0 0 S10 X X 1 1 X don t care Copyright 2006 2015 Texas Instruments Incorporated Detailed Description 93 Submit Documentation Feedback Product Folder Links MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG461...

Page 94: ... SIGNALS 1 PIN NAME P10 x x FUNCTION P10DIR x P10SEL x LCDS8 P10 0 S9 0 P10 0 I O I 0 O 1 0 0 S9 X X 1 P10 1 S8 1 P10 1 I O I 0 O 1 0 0 S8 X X 1 1 X don t care Table 6 39 Port P10 P10 2 to P10 5 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P10 x x FUNCTION P10DIR x P10SEL x LCDS4 P10 2 S7 2 P10 2 I O I 0 O 1 0 0 S7 X X 1 P10 3 S6 3 P10 3 I O I 0 O 1 0 0 S6 X X 1 P10 4 S5 4 P10 4 I O I 0 O 1 0 ...

Page 95: ...P10 6 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P10 x x FUNCTION P10DIR x P10SEL x INCHx LCDS0 P10 6 S3 A15 P5 0 I O I 0 O 1 0 X 0 A15 2 X 1 15 0 6 S3 enabled X 0 X 1 S3 disabled X 1 X 1 1 X don t care 2 Setting the P10SEL x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals Copyright 2006 2015 Texas Instruments Inco...

Page 96: ...ONTROL BITS OR SIGNALS 1 PIN NAME P10 x x FUNCTION OAPx OA1 P10DIR x P10SEL x INCHx LCDS0 OANx OA1 P10 7 S2 A14 OA2I1 7 P10 7 I O I 0 O 1 0 X X 0 A14 2 X 1 14 X 0 OA2I1 2 0 X X 1 0 S2 enabled X 0 X X 1 S2 disabled X 1 X X 1 1 X don t care 2 Setting the P10SEL x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals 96 Detailed ...

Page 97: ... the DAC0 output is fed back to its own reference input DAC0_2_OA DAC12 0OPS 1 0 P6 6 A6 DAC0 OA2I0 MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 www ti com SLAS508J APRIL 2006 REVISED JUNE 2015 6 10 24 VeREF DAC0 Copyright 2006 2015 Texas Instruments Incorporated Detailed Description 97 Submit Documentation Feedback Product Folder Links MS...

Page 98: ...SP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 SLAS508J APRIL 2006 REVISED JUNE 2015 www ti com 6 10 25 JTAG Pins TMS TCK TDI TCLK TDO TDI Input Output With Schmitt Trigger or Output 98 Detailed Description Copyright 2006 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4...

Page 99: ...h the first negative edge on the TMS pin after power up or if the TMS is being held low during power up The second positive edge on the TMS pin deactivates the fuse check mode After deactivation the fuse check mode remains inactive until another POR occurs After each POR the fuse check mode has the potential to be activated The fuse check current only flows when the fuse check mode is active and t...

Page 100: ...ncluded The following table shows the compatible target boards and the supported packages Package Target Board and Programmer Bundle Target Board Only 100 pin LQFP PZ MSP FET430U100 MSP TS430PZ100 7 1 2 2 2 Experimenter Boards Experimenter Boards and Evaluation kits are available for some MSP430 devices These kits feature additional hardware components and connectivity for full system evaluation a...

Page 101: ...ools with MSP for devices and MSP for tools Device development evolutionary flow XMS Experimental device that is not necessarily representative of the electrical specifications for the final device PMS Final silicon die that conforms to the electrical specifications for the device but has not completed quality and reliability verification MSP Fully qualified production device Support tool developm...

Page 102: ...0 C to 50 C C to 70 C I 40 C to 85 C T 40 C to 105 C C 0 Packaging http www ti com packaging Optional Tape and Reel T Small Reel R Large Reel No Markings Tube or Tray Optional Additional Features EP Enhanced Product 40 C to 105 C HT Extreme Temperature Parts 55 C to 150 C Q1 Automotive Q100 Qualified MSP 430 F 5 438 A I ZQW T XX Processor Family Series Optional Temperature Range 430 MCU Platform P...

Page 103: ...ns to the functional specifications for all silicon revisions of the device SLAZ121 MSP430CG4617 Device Erratasheet Describes the known exceptions to the functional specifications for all silicon revisions of the device SLAZ120 MSP430CG4616 Device Erratasheet Describes the known exceptions to the functional specifications for all silicon revisions of the device 7 3 Related Links Table 7 1 lists qu...

Page 104: ...riate precautions Failure to observe proper handling and installation procedures can cause damage ESD damage can range from subtle performance degradation to complete device failure Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications 7 7 Export Control Notice Recipient agrees to not kn...

Page 105: ...nformation is the most current data available for the designated devices This data is subject to change without notice and revision of this document For browser based versions of this data sheet refer to the left hand navigation Copyright 2006 2015 Texas Instruments Incorporated Mechanical Packaging and Orderable Information 105 Submit Documentation Feedback Product Folder Links MSP430FG4619 MSP43...

Page 106: ...PZR ACTIVE LQFP PZ 100 1000 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 85 M430FG4617 MSP430FG4617IZQWR ACTIVE BGA MICROSTAR JUNIOR ZQW 113 2500 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 85 M430FG4617 MSP430FG4618IPZ ACTIVE LQFP PZ 100 90 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 85 M430FG4618 MSP430FG4618IPZR ACTIVE LQFP PZ 100 1000 Green RoHS no Sb Br CU NIPD...

Page 107: ...pursuant to a specific EU RoHS exemption Green TI defines Green to mean the content of Chlorine Cl and Bromine Br based flame retardants meet JS709B low halogen requirements of 1000ppm threshold Antimony trioxide based flame retardants must also meet the 1000ppm threshold requirement 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and ...

Page 108: ...UM www ti com 31 May 2017 Addendum Page 3 In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis ...

Page 109: ... 0 2 1 20 0 24 0 Q2 MSP430FG4617IZQWR BGA MI CROSTA R JUNI OR ZQW 113 2500 330 0 16 4 7 3 7 3 1 5 12 0 16 0 Q1 MSP430FG4618IPZR LQFP PZ 100 1000 330 0 24 4 17 0 17 0 2 1 20 0 24 0 Q2 MSP430FG4618IZQWR BGA MI CROSTA R JUNI OR ZQW 113 2500 330 0 16 4 7 3 7 3 1 5 12 0 16 0 Q1 MSP430FG4618IZQWT BGA MI CROSTA R JUNI OR ZQW 113 250 180 0 16 4 7 3 7 3 1 5 12 0 16 0 Q1 MSP430FG4619IPZR LQFP PZ 100 1000 33...

Page 110: ... 45 0 MSP430FG4616IZQWR BGA MICROSTAR JUNIOR ZQW 113 2500 336 6 336 6 28 6 MSP430FG4617IPZR LQFP PZ 100 1000 367 0 367 0 45 0 MSP430FG4617IZQWR BGA MICROSTAR JUNIOR ZQW 113 2500 336 6 336 6 28 6 MSP430FG4618IPZR LQFP PZ 100 1000 367 0 367 0 45 0 MSP430FG4618IZQWR BGA MICROSTAR JUNIOR ZQW 113 2500 336 6 336 6 28 6 MSP430FG4618IZQWT BGA MICROSTAR JUNIOR ZQW 113 250 213 0 191 0 55 0 MSP430FG4619IPZR ...

Page 111: ...age Type Package Drawing Pins SPQ Length mm Width mm Height mm JUNIOR MSP430FG4619IZQWT BGA MICROSTAR JUNIOR ZQW 113 250 213 0 191 0 55 0 PACKAGE MATERIALS INFORMATION www ti com 15 Jun 2017 Pack Materials Page 3 ...

Page 112: ......

Page 113: ...QUAD FLATPACK 4040149 B 11 96 50 26 0 13 NOM Gage Plane 0 25 0 45 0 75 0 05 MIN 0 27 51 25 75 1 12 00 TYP 0 17 76 100 SQ SQ 15 80 16 20 13 80 1 35 1 45 1 60 MAX 14 20 0 7 Seating Plane 0 08 0 50 M 0 08 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 026 ...

Page 114: ......

Page 115: ...oduct s identified in such TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN including but not limited to any patent right copyright mask work right or other intellectual property right relating to any combination machine or p...

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