SDA
SCL
t
LOW
t
HD , DAT
t
SU , DAT
t
HD , STA
t
SU , STA
t
HD , STA
t
HIGH
t
SU , STO
t
SP
t
BUF
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
5.25
USCI (I
2
C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see
Figure 5-22
)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
f
USCI
USCI input clock frequency
External: UCLK
f
SYSTEM
MHz
Duty Cycle = 50% ±10%
f
SCL
SCL clock frequency
2.2 V, 3 V
0
400
kHz
f
SCL
≤
100 kHz
2.2 V, 3 V
4
t
HD,STA
Hold time (repeated) START
µs
f
SCL
> 100 kHz
2.2 V, 3 V
0.6
f
SCL
≤
100 kHz
2.2 V, 3 V
4.7
t
SU,STA
Setup time for a repeated START
µs
f
SCL
> 100 kHz
2.2 V, 3 V
0.6
t
HD,DAT
Data hold time
2.2 V, 3 V
0
ns
t
SU,DAT
Data setup time
2.2 V, 3 V
250
ns
t
SU,STO
Setup time for STOP
2.2 V, 3 V
4
µs
2.2 V
50
150
600
Pulse duration of spikes suppressed by
t
SP
ns
input filter
3 V
50
100
600
Figure 5-22. I
2
C Mode Timing
5.26
USART1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
CC
= 2.2 V, SYNC = 0, UART mode
200
430
800
t
(
τ
)
USART1 deglitch time
ns
V
CC
= 3 V, SYNC = 0, UART mode
150
280
500
(1)
The signal applied to the USART1 receive signal (terminal) (URXD1) must meet the timing requirements of t
(
τ
)
to ensure that the URXS
flip-flop is set. The URXS flip-flop is set with negative pulses that meet the minimum-timing condition of t
(
τ
)
. The operating conditions to
set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the
URXD1 line.
Copyright © 2006–2015, Texas Instruments Incorporated
Specifications
33
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