Positive
Negative
VR+
Gain Error
Offset Error
DAC Code
DAC VOUT
Ideal transfer
function
RLoad =
AVCC
CLoad = 100pF
2
DAC Output
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
www.ti.com
SLAS508J – APRIL 2006 – REVISED JUNE 2015
5.34
12-Bit DAC, Linearity Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see
Figure 5-26
)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
Resolution
12-bit monotonic
12
bits
V
ref
= 1.5 V,
2.2 V
DAC12AMPx = 7, DAC12IR = 1
INL
Integral nonlinearity
(1)
±2.0
±8.0
LSB
V
ref
= 2.5 V,
3 V
DAC12AMPx = 7, DAC12IR = 1
V
ref
= 1.5 V,
2.2 V
DAC12AMPx = 7, DAC12IR = 1
DNL
Differential nonlinearity
(1)
±0.4
±1.0
LSB
V
ref
= 2.5 V,
3 V
DAC12AMPx = 7, DAC12IR = 1
V
ref
= 1.5 V,
2.2 V
DAC12AMPx = 7, DAC12IR = 1
Offset voltage without calibration
(1) (2)
±21
V
ref
= 2.5 V,
3 V
DAC12AMPx = 7, DAC12IR = 1
E
O
mV
V
ref
= 1.5 V,
2.2 V
DAC12AMPx = 7, DAC12IR = 1
Offset voltage with calibration
(1) (2)
±2.5
V
ref
= 2.5 V,
3 V
DAC12AMPx = 7, DAC12IR = 1
d
E(O)
/d
T
Offset error temperature coefficient
(1)
2.2 V, 3 V
±30
µV/°C
V
REF
= 1.5 V
2.2 V
E
G
Gain error
(1)
±3.5
%FSR
V
REF
= 2.5 V
3 V
ppm of
d
E(G)
/d
T
Gain temperature coefficient
(1)
2.2 V, 3 V
10
FSR/°C
DAC12AMPx = 2
100
t
Offset_Cal
Time for offset calibration
(3)
DAC12AMPx = 3, 5
2.2 V, 3 V
32
ms
DAC12AMPx = 4, 6, 7
6
(1)
Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and “b” of
the first order equation: y = a + b × x. V
DAC12_xOUT
= E
O
+ (1 + E
G
) × (Ve
REF+
/4095) × DAC12_xDAT, DAC12IR = 1.
(2)
The offset calibration works on the output operational amplifier. Offset calibration is triggered by setting bit DAC12CALON.
(3)
The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx =
{0, 1}. TI recommends that the DAC12 module be configured before initiating calibration. Port activity during calibration may effect
accuracy and is not recommended.
Figure 5-26. Linearity Test Load Conditions and Gain and Offset Definition
Copyright © 2006–2015, Texas Instruments Incorporated
Specifications
39
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