Texas Instruments MSP430FG4618, Manual

Page: 35 / 115

C
VREF+
1
m
F
0
1 ms
10 ms
100 ms t
REFON
t
REFON
»
.66 x C [ms] with C in
VREF+ VREF+
m
F
100
m
F
10
m
F
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
www.ti.com SLAS508J – APRIL 2006 – REVISED JUNE 2015
5.29 12-Bit ADC, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REF2_5V = 1 for 2.5 V,
V
CC
= 3 V 2.4 2.5 2.6
I
VREF+
max ≤ I
VREF+
≤ I
VREF+
min
Positive built in reference voltage
V
REF+
V
output
REF2_5V = 0 for 1.5 V,
V
CC
= 2.2 V, 3 V 1.44 1.5 1.56
I
VREF+
max ≤ I
VREF+
≤ I
VREF+
min
REF2_5V = 0, I
VREF+
max ≤ I
VREF+
≤ I
VREF+
min 2.2
AV
CC
minimum voltage, Positive
AV
CC(min)
REF2_5V = 1, I
VREF+
min ≥ I
VREF+
≥ –0.5 mA 2.8 V
built in reference active
REF2_5V = 1, I
VREF+
min
≥
I
VREF+
≥
– 1 mA 2.9
V
CC
= 2.2 V 0.01 –0.5
Load current out of V
REF+
I
VREF+
mA
terminal
V
CC
= 3 V 0.01 –1
I
VREF+
= 500 µA ±100 µA, V
CC
= 2.2 V ±2
Analog input voltage ≈ 0.75 V,
V
CC
= 3 V ±2
REF2_5V = 0
Load-current regulation, V
REF+
I
L(VREF+)
LSB
terminal
I
VREF+
= 500 µA ±100 µA,
Analog input voltage ≈ 1.25 V, V
CC
= 3 V ±2
REF2_5V = 1
I
VREF+
= 100 µA
→
900 µA,
Load current regulation, VREF+
I
DL(VREF+)
C
VREF+
= 5 µF, Ax ≈ 0.5 × V
REF+
, V
CC
= 3 V 20 ns
terminal
Error of conversion result
≤
1 LSB
REFON = 1,
C
VREF+
Capacitance at pin V
REF+
(1)
V
CC
= 2.2 V, 3 V 5 10 µF
0 mA ≤ I
VREF+
≤ I
VREF+
max
Temperature coefficient of built- I
VREF+
is a constant in the range of
T
REF+
V
CC
= 2.2 V, 3 V ±100 ppm/°C
in reference 0 mA ≤ I
VREF+
≤ 1 mA
Settling time of internal reference I
VREF+
= 0.5 mA, C
VREF+
= 10 µF,
t
REFON
17 ms
voltage (see Figure 5-23 )
(2)
V
REF+
= 1.5 V, V
AVCC
= 2.2 V
(1) The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two
capacitors between pins V
REF+
and AV
SS
and V
REF-–
/Ve
REF–
and AV
SS
: 10-µF tantalum and 100-nF ceramic.
(2) The condition is that the error in a conversion started after t
REFON
is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
Figure 5-23. Typical Settling Time of Internal Reference t
REFON
vs External Capacitor on V
REF+
Copyright © 2006–2015, Texas Instruments Incorporated
Specifications 35
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