V
CC
0
0.5
1
1.5
2
V
CC(drop)
t
pw
tpw - Pulse Width -
m
s
V
C
C
(d
ro
p
)
-
V
3 V
0.001
1
1000
t
f
t
r
tpw - Pulse Width -
m
s
t = t
f
r
Typical Conditions
V
= 3 V
CC
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
www.ti.com
SLAS508J – APRIL 2006 – REVISED JUNE 2015
Figure 5-12. V
CC(drop)
Level With a Triangle Voltage Drop to Generate a POR or BOR Signal
5.18
SVS (Supply Voltage Supervisor and Monitor)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dV
CC
/dt > 30 V/ms (see
Figure 5-13
)
5
150
t
(SVSR)
µs
dV
CC
/dt
≤
30 V/ms
2000
t
d(SVSon)
SVS on, switch from VLD = 0 to VLD
≠
0, V
CC
= 3 V
150
300
µs
t
settle
VLD
≠
0
(1)
12
µs
V
(SVSstart)
VLD
≠
0, V
CC
/dt
≤
3 V/s (see
Figure 5-13
)
1.55
1.7
V
VLD = 1
70
120
155
mV
V
CC
/dt
≤
3 V/s (see
Figure 5-13
)
V
(SVS_IT–)
V
(SVS_IT–)
VLD = 2 to 14
V
hys(SVS_IT–)
× 0.001
× 0.016
V
CC
/dt
≤
3 V/s (see
Figure 5-13
), external voltage
VLD = 15
4.4
20
mV
applied on A7
VLD = 1
1.8
1.9
2.05
VLD = 2
1.94
2.1
2.23
VLD = 3
2.05
2.2
2.35
VLD = 4
2.14
2.3
2.46
VLD = 5
2.24
2.4
2.58
VLD = 6
2.33
2.5
2.69
VLD = 7
2.46
2.65
2.84
V
CC
/dt
≤
3 V/s (see
Figure 5-13
)
VLD = 8
2.58
2.8
2.97
V
(SVS_IT–)
V
VLD = 9
2.69
2.9
3.10
VLD = 10
2.83
3.05
3.26
VLD = 11
2.94
3.2
3.39
VLD = 12
3.11
3.35
3.58
(2)
VLD = 13
3.24
3.5
3.73
(2)
VLD = 14
3.43
3.7
(2)
3.96
(2)
V
CC
/dt
≤
3 V/s (see
Figure 5-13
), external voltage
VLD = 15
1.1
1.2
1.3
applied on A7
I
CC(SVS)
(3)
VLD
≠
0, V
CC
= 2.2 V, 3 V
10
15
µA
(1)
t
settle
is the settling time that the comparator output needs to have a stable level after VLD is switched from VLD
≠
0 to a different VLD
value from 2 to 15. The overdrive is assumed to be > 50 mV.
(2)
The recommended operating voltage range is limited to 3.6 V.
(3)
The current consumption of the SVS module is not included in the I
CC
current consumption data.
Copyright © 2006–2015, Texas Instruments Incorporated
Specifications
25
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