Texas Instruments MSP430F4132IPM Manual Download Page 68

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

POST OFFICE BOX 655303



DALLAS, TEXAS 75265

APPLICATION INFORMATION

Port P7 pin schematic: P7.0 to P7.3, input/output with Schmitt trigger

Direction
0: Input
1: Output

P7SEL.x

P7DIR.x

P7IN.x

P7OUT.x

Pad Logic

Bus

Keeper

LCDS32

To JTAG

From JTAG

P7.0/TDO/TDI/S32
P7.1/TDI/TCLK/S33
P7.2/TMS/S34
P7.3/TCK/S35

0/1

Port P7 (P7.0 to P7.3) pin functions

PIN NAME (P7 X)

FUNCTION

CONTROL BITS / SIGNALS

PIN NAME (P7.X)

FUNCTION

JTAG Mode

P7DIR.x

P7SEL.x

LCDS32

P7.0/TDO/TDI/S32

P7.x (I/O)

I: 0, O: 1

TDO/TDI (see Note 1)

S32

P7.1/TDI/TCLK/S33

P7.x (I/O)

I: 0, O: 1

TDI/TCLK (see Note 1)

S33

P7.2/TMS/S34

P7.x (I/O)

I: 0, O: 1

TMS (see Note 1)

S34

P7.3/TCK/S35

P7.3 (I/O)

I: 0, O: 1

TCK (see Note 1)

S35

NOTES: 1. In JTAG Mode the internal pullup/pulldown resistors are disabled.

2. X: Don’t care.

Summary of Contents for MSP430F4132IPM

Page 1: ...eral devices featuring different sets of peripherals targeted for various applications The architecture combined with five low power modes is optimized to achieve extended battery life in portable mea...

Page 2: ...e end of this document or see the TI web site at www ti com Package drawings thermal data and symbolization are available at www ti com packaging DEVELOPMENT TOOL SUPPORT All MSP430 microcontrollers i...

Page 3: ...3 R03 P5 2 R13 LCDREF P5 1 R23 R33 LCDCAP AV CC P6 0 TA1 2 A2 CA4 P7 5 TA1 3 A1 CA3 P7 4 TA1 4 A0 CA2 RST NMI SBWTDIO P7 3 TCK S35 P7 2 TMS S34 P7 1 TDI TCLK S33 P7 0 TDO TDI S32 P1 0 TA0 0 S31 P1 1 T...

Page 4: ...P5 1 R23 R33 LCDCAP AV CC RST NMI SBWTDIO P4 7 ADC10CLK S0 TEST SBWTCLK AV SS DVCC DVSS 48 pin RGZ PACKAGE TOP VIEW 36 35 48 47 46 45 44 43 42 41 40 39 38 37 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6...

Page 5: ...JTAG Interface Basic Timer Real Time Clock LCD_A 144 Segments 1 2 3 4 Mux Comparator _A AVCC AVSS P1 x P2 x 2x8 P3 x P4 x 2x8 SMCLK ACLK MDB MAB Ports P1 P2 2x8 I O Interrupt capability XIN XOUT RAM 5...

Page 6: ...S26 48 35 I O General purpose digital I O pin Timer0_A3 clock signal TACLK input Comparator_A output LCD segment output P1 6 ACLK CA0 47 34 I O General purpose digital I O pin Comparator_A input 0 ACL...

Page 7: ...ut P3 7 S16 28 I O General purpose digital I O pin LCD segment output P4 0 S7 19 15 I O General purpose digital I O pin LCD segment output P4 1 S6 18 14 I O General purpose digital I O pin LCD segment...

Page 8: ...in I2C mode P6 3 UCB0STE UCA0CLK A3 CA5 Veref Vref 3 I O General purpose digital I O pin USCI B0 slave transmit enable USCI A0 clock input output ADC10 analog input A3 negative reference Comparator_A...

Page 9: ...General purpose digital I O pin Timer0_A3 capture CCI2A input compare Out2 output LCD segment output AVCC 64 48 Analog supply voltage positive terminal AVSS 62 46 Analog supply voltage negative termi...

Page 10: ...of the CPU clock Four of the registers R0 to R3 are dedicated as program counter stack pointer status register and constant generator respectively The remaining registers are general purpose registers...

Page 11: ...ive mode AM All clocks are active D Low power mode 0 LPM0 CPU is disabled ACLK and SMCLK remain active FLL loop control remains active D Low power mode 1 LPM1 CPU is disabled ACLK and SMCLK remain act...

Page 12: ...AIFG see Notes 1 and 2 Maskable 0xFFF8 12 Comparator_A CAIFG Maskable 0xFFF6 11 Watchdog Timer WDTIFG Maskable 0xFFF4 10 USCI_A0 B0 Receive UCA0RXIFG see Note 1 UCB0RXIFG SPI mode or UCB0STAT UCALIFG...

Page 13: ...dress 7 6 5 4 3 2 1 0 00h ACCVIE NMIIE OFIE WDTIE rw 0 rw 0 rw 0 rw 0 WDTIE Watchdog timer interrupt enable Inactive if watchdog mode is selected Active if watchdog timer is configured in interval tim...

Page 14: ...rupt flag Set on a reset condition at RST NMI pin in reset mode Reset on VCC power up PORIFG Power on interrupt flag Set on VCC power up NMIIFG Set via RST NMI pin Address 7 6 5 4 3 2 1 0 03h BTIFG UC...

Page 15: ...via the BSL is protected by user defined password For complete description of the features of the BSL and its implementation see the MSP430 Memory Programming User s Guide literature number SLAU265 BS...

Page 16: ...igh frequency crystal or a very low power LF oscillator D Main clock MCLK the system clock used by the CPU D Sub Main clock SMCLK the sub system clock used by the peripheral modules D ACLK n the buffe...

Page 17: ...on and segment signals are generated as defined by the mode Static 2 MUX 3 MUX and 4 MUX LCDs are supported by this peripheral The module can provide a LCD voltage independent of the supply voltage vi...

Page 18: ...1B CCR1 TA1 27 P2 0 23 P2 0 DVSS GND CCR1 TA1 ADC10 internal ADC10 internal DVCC VCC 35 P3 0 TA1 2 CCI2A 35 P3 0 ACLK internal CCI2B CCR2 TA2 26 P2 1 22 P2 1 DVSS GND CCR2 TA2 63 P6 0 47 P6 0 DVCC VCC...

Page 19: ...IV 012Eh Timer1_A5 Capture compare register 4 C t i t 3 TA1CCR4 TA1CCR3 019A 0198 Capture compare register 3 Capture compare register 2 TA1CCR3 TA1CCR2 0198 0196h Capture compare register 2 Capture co...

Page 20: ...0x0062 USCI A0 control 1 UCA0CTL1 0x0061 USCI A0 control 0 UCA0CTL0 0x0060 USCI A0 IrDA receive control UCA0IRRCTL 0x005F USCI A0 IrDA transmit control UCA0IRTCTL 0x005E USCI B0 transmit buffer UCB0TX...

Page 21: ...RTCCTL BTCTL 04Fh 04Eh 04Dh 04Ch 047h 046h 045h 044h 043h 042h 041h 040h Port P7 Port P7 selection P7SEL 03Bh Port P7 direction P7DIR 03Ah Port P7 output P7OUT 039h Port P7 input P7IN 038h Port P6 Por...

Page 22: ...enable P1IE 025h Port P1 interrupt edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h Special functions SFR interr...

Page 23: ...use blow voltage VFB is allowed to exceed the absolute maximum rating The voltage is applied to the TEST pin when blowing the JTAG fuse recommended operating conditions MIN NOM MAX UNIT Supply voltage...

Page 24: ...3 0 A I LPM3 Basic Timer1 enabled ACLK selected LCD A enabled LCDCPEN 0 40 C 1 0 1 5 A LCD_A enabled LCDCPEN 0 static mode fLCD f ACLK 32 25 C 3 V 1 1 1 5 LCD ACLK see Notes 2 and 3 60 C 3 V 1 4 1 9 8...

Page 25: ...303 DALLAS TEXAS 75265 typical characteristics LPM4 current 0 0 0 5 1 0 1 5 2 0 2 5 3 0 40 0 20 0 0 0 20 0 40 0 60 0 80 0 100 0 TA Temperature C ILPM4 Low power mode current uA Vcc 3 6V TA Temperature...

Page 26: ...2 V 62 ns t int External interrupt timing Port P1 P2 P1 x to P2 x external trigger signal for the interrupt flag see Note 1 3 V 50 ns t Timer A capture timing TA0 TA1 TA2 2 2 V 62 ns t cap Timer_A ca...

Page 27: ...output voltage IOL max 6 mA VCC 2 2 V see Note 2 VSS VSS 0 6 V VOL Low level output voltage IOL max 1 5 mA VCC 3 V see Note 1 VSS VSS 0 25 V IOL max 6 mA VCC 3 V see Note 2 VSS VSS 0 6 NOTES 1 The ma...

Page 28: ...10 15 20 25 30 35 40 45 50 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 VCC 3 V P1 0 TYPICAL LOW LEVEL OUTPUT CURRENT vs LOW LEVEL OUTPUT VOLTAGE TA 25 C TA 85 C OL I Typical Low level Output Current mA TA 40 C Fi...

Page 29: ...Figure 7 1 71 V Vhys B_IT see Note 2 dVCC dt 3 V s see Figure 7 mV t reset Pulse length needed at RST NMI pin to accepted reset internally VCC 2 2 V 3 V 2 s NOTES 1 The current consumption of the bro...

Page 30: ...stics continued VCC min VCC 3 V tpw 0 0 5 1 1 5 2 0 001 1 1000 Typical Conditions 1 ns 1 ns tpw Pulse Width s V CC min V tpw Pulse Width s VCC 3 V Figure 8 V CC min Level With a Square Voltage Drop to...

Page 31: ...20 mV VLD 1 1 8 1 9 2 05 VLD 2 1 94 2 1 2 25 VLD 3 2 05 2 2 2 37 VLD 4 2 14 2 3 2 48 VLD 5 2 24 2 4 2 6 VLD 6 2 33 2 5 2 71 V dt 3 V s see Figure 10 and Figure 11 VLD 7 2 46 2 65 2 86 V SVS IT VCC dt...

Page 32: ...ned Vhys SVS_IT 0 1 td BOR Brownout 0 1 td SVSon td BOR 0 1 Set POR Brown out Region SVS Circuit is Active From VLD to VCC V B_IT SVS out Vhys B_IT Figure 10 SVS Reset SVSR vs Supply Voltage 0 0 5 1 1...

Page 33: ...15 5 25 MH f DCO27 FN_8 FN_4 0 FN_3 1 FN_2 x DCOPLUS 1 see Note 1 3 V 10 3 17 9 28 5 MHz f FN 8 0 FN 4 1 FN 3 FN 2 DCOPLUS 1 2 2 V 1 8 2 8 4 2 MH f DCO2 FN_8 0 FN_4 1 FN_3 FN_2 x DCOPLUS 1 3 V 2 1 3 4...

Page 34: ...DCO Tap S n Stepsize Ratio between DCO Taps Min Max 1 07 1 06 Figure 13 DCO Tap Step Size DCO Frequency Adjusted by Bits 29 to 25 in SCFI1 N DCO FN_2 0 FN_3 0 FN_4 0 FN_8 0 FN_2 1 FN_3 0 FN_4 0 FN_8 0...

Page 35: ...Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency For a correct setup the effective load capacitance should always match the speci...

Page 36: ...e ACLK frequency For a correct setup the effective load capacitance should always match the specification of the used crystal 2 Requires external capacitors at both terminals Values are specified by c...

Page 37: ...e VLCDx 0010 2 66 V VLCD LCD voltage VLCDx 0011 2 72 V VLCD LCD voltage VLCDx 0100 2 78 V VLCD LCD voltage VLCDx 0101 2 84 V VLCD LCD voltage VLCDx 0110 2 90 V VLCD LCD voltage VLCDx 0111 2 96 V VLCD...

Page 38: ...6 CA0 and P1 7 CA1 2 2 V 390 480 540 mV V RefVT See Figure 15 and Figure 16 No load at P1 6 CA0 and P1 7 CA1 TA 85 C 3 V 400 490 550 mV VIC Common mode input voltage range CAON 1 2 2 V 3 V 0 VCC 1 V V...

Page 39: ...95 VCC 3 V Figure 15 V RefVT vs Temperature V REF Reference Voltage mV Typical REFERENCE VOLTAGE vs FREE AIR TEMPERATURE Figure 16 V RefVT vs Temperature TA Free Air Temperature C 400 450 500 550 600...

Page 40: ...REFON 1 REFOUT 0 3 V 0 25 0 4 mA I Reference buffer supply current with fADC10CLK 5 MHz ADC10ON 0 REFON 1 REF2 5V 0 2 2 V 3 V 1 1 1 4 mA IREFB 0 current with ADC10SR 0 see Note 4 REFON 1 REF2_5V 0 REF...

Page 41: ...EF2_5V 1 3 V 2 LSB VREF load regulation response IVREF 100 A 900 A V 0 5 x V Error of ADC10SR 0 3 V 400 ns VREF load regulation response time VAx 0 5 x VREF Error of conversion result 1 LSB ADC10SR 1...

Page 42: ...tatic input current into VeREF 0V VeREF VCC 2 2 V 3 V 1 A NOTES 1 The external reference is used during conversion to charge and discharge the capacitance array The input capacitance CI is also the dy...

Page 43: ...e ADC See Note 1 100 ns NOTE 1 The condition is that the error in a conversion started after tADC10ON is less than 0 5 LSB The reference and input signals are already settled 10 bit ADC linearity para...

Page 44: ...INCHx 0Bh 2 2 V 1 06 1 1 1 14 V VMID VCC divider at channel 11 ADC10ON 1 INCHx 0Bh VMID is 0 5 x VCC 3 V 1 46 1 5 1 54 V t Sample time required if channel 11 is selected ADC10ON 1 INCHx 0Bh 2 2 V 1400...

Page 45: ...ns tHD MI SOMI input data hold time 3 V 0 ns t SIMO output data valid time UCLK edge to SIMO valid 2 2 V 30 ns tVALID MO SIMO output data valid time UCLK edge to SIMO valid CL 20 pF 3 V 20 ns NOTE fU...

Page 46: ...cteristics over recommended ranges of supply voltage and operating free air temperature unless otherwise noted continued UCLK CKPL 0 CKPL 1 SIMO 1 fUCxCLK tLO HI tLO HI SOMI tSU MI tHD MI tVALID MO Fi...

Page 47: ...pply voltage and operating free air temperature unless otherwise noted continued STE UCLK CKPL 0 CKPL 1 SOMI tSTE ACC tSTE DIS 1 fUCxCLK tLO HI tLO HI SIMO tSU SI tHD SI tVALID SO tSTE LEAD tSTE LAG F...

Page 48: ...SCL clock frequency 2 2 V 3 V 0 400 kHz t Hold time repeated START fSCL 100kHz 2 2 V 3 V 4 0 us tHD STA Hold time repeated START fSCL 100kHz 2 2 V 3 V 0 6 us t Set p time for a repeated START fSCL 10...

Page 49: ...xceeded when writing to a 64 byte flash block This parameter applies to all programming methods individual word byte write and block write modes 2 The mass erase duration generated by the flash timing...

Page 50: ...otherwise noted continued JTAG fuse see Note 1 PARAMETER TEST CONDITIONS VCC MIN MAX UNIT VCC FB Supply voltage during fuse blow condition TA 25 C 2 5 V VFB Voltage level on TDI TCLK for fuse blow 6 7...

Page 51: ...in schematic P1 0 to P1 4 input output with Schmitt trigger Direction 0 Input 1 Output P1SEL x P1DIR x P1IN x P1IRQ x D EN Module X IN Module X OUT P1OUT x Interrupt Edge Select Q EN Set P1SEL x P1IES...

Page 52: ...0 0 Timer0_A3 CCI0A 0 1 0 Timer0_A3 TA0 1 1 0 S31 x x 1 LCDS28 P1 1 TA0 0 MCLK S30 1 P1 x I O I 0 O 1 0 0 Timer0_A3 CCI0B 0 1 0 MCLK 1 1 0 S30 x x 1 LCDS28 P1 2 TA0 1 S29 2 P1 x I O I 0 O 1 0 0 Timer...

Page 53: ...Interrupt Edge Select Q EN Set P1SEL x P1IES x P1IFG x P1IE x Pad Logic 1 0 1 0 Bus Keeper EN P1 5 TA0CLK CAOUT S26 Segment Sy LCDS24 from TA0CLK of P1 7 Port P1 P1 5 pin functions CONTROL BITS SIGNAL...

Page 54: ...tion 0 Input 1 Output P1SEL x P1DIR x P1IN x D EN Module X IN Module Out P1OUT x Pad Logic 1 0 1 0 Bus Keeper EN CAPD y From Comparator_A To Comparator_A P1IRQ x Interrupt Edge Select Q EN Set P1SEL x...

Page 55: ...x Pad Logic 1 0 1 0 Bus Keeper EN CAPD y From Comparator_A To Comparator_A P1IRQ x Interrupt Edge Select Q EN Set P1SEL x P1IES x P1IFG x P1IE x Port P1 P1 7 pin functions PIN NAME P1 X X FUNCTION CON...

Page 56: ...schematic P2 0 to P2 7 input output with Schmitt trigger Direction 0 Input 1 Output P2SEL x P2DIR x P2IN x P2IRQ x D EN Module X IN Module X OUT P2OUT x Interrupt Edge Select Q EN Set P2SEL x P2IES x...

Page 57: ...Timer1_A5 TA1 1 1 0 S15 x x 1 LCDS12 P2 1 TA1 2 S14 1 P2 x I O I 0 O 1 0 0 Timer1_A5 TA2 1 1 0 S14 x x 1 LCDS12 P2 2 TA1 3 S13 2 P2 x I O I 0 O 1 0 0 Timer1_A5 TA3 1 1 0 S13 x x 1 LCDS12 P2 3 TA1 4 S...

Page 58: ...ON INFORMATION Port P3 pin schematic P3 0 to P3 7 input output with Schmitt trigger Direction 0 Input 1 Output P3SEL x P3DIR x P3IN x D EN Module X IN Module X OUT P3OUT x Pad Logic 1 0 1 0 Bus Keeper...

Page 59: ...P3 1 TA1 3 S22 1 P3 x I O I 0 O 1 0 0 Timer1_A5 CCI3A 0 1 0 Timer1_A5 TA3 1 1 0 S22 x x 1 LCDS20 P3 2 TA1 4 S21 2 P3 x I O I 0 O 1 0 0 Timer1_A5 CCI4A 0 1 0 Timer1_A5 TA4 1 1 0 S21 x x 1 LCDS20 P3 3 T...

Page 60: ...EN Pad Logic Segment Sy LCDS0 4 Module X Out Port P4 P4 0 to P4 7 pin functions CONTROL BITS SIGNALS PIN NAME P4 X X FUNCTION P4DIR x P4SEL x LCDS4 LCDS0 P4 0 S7 0 P4 x I O I 0 O 1 0 0 S7 x x 1 LCDS4...

Page 61: ...mitt trigger Direction 0 Input 1 Output P5SEL x P5DIR x P5IN x D EN Module X IN Module X OUT P5OUT x Pad Logic 1 0 1 0 Bus Keeper EN P5 0 TA1 1 S24 Segment Sy LCDS24 Port P5 P5 0 pin functions PIN NAM...

Page 62: ...ut P5SEL x P5DIR x P5IN x 0 1 P5OUT x 1 0 1 0 Bus Keeper EN Pad Logic LCD Signal Port P5 P5 1 to P5 7 pin functions PIN NAME P5 X X FUNCTION CONTROL BITS SIGNALS PIN NAME P5 X X FUNCTION P5DIR x P5SEL...

Page 63: ...ction 0 Input 1 Output P6SEL x P6DIR x P6IN x Module Out P6OUT x Pad Logic 1 0 1 0 Bus Keeper EN To ADC10 ADC10AE0 2 INCH 2 CAPD 4 From Comparator_A To Comparator_A D EN Module X IN Port P6 P6 0 pin f...

Page 64: ...x D EN Module X IN Module X OUT P6OUT x Pad Logic 1 0 1 0 P6 1 UCB0SOMI UCB0SCL P6 2 UCB0SIMO UCB0SDA Module direction Port P6 P6 1 and P6 2 pin functions PIN NAME P6 X X FUNCTION CONTROL BITS SIGNALS...

Page 65: ...3 4 INCH 3 4 CAPD 5 6 From Comparator_A To Comparator_A from Module P6IN x D EN Module X IN Port P6 P6 3 and P6 4 pin functions PIN NAME P6 X X FUNCTION CONTROL BITS SIGNALS PIN NAME P6 X X FUNCTION C...

Page 66: ...Direction 0 Input 1 Output P6SEL x P6DIR x P6IN x P6OUT x Pad Logic 1 0 1 0 Bus Keeper EN D EN Module X IN ADC10AE0 5 6 Port P6 P6 5 and P6 6 pin functions PIN NAME P6 X X FUNCTION CONTROL BITS SIGNAL...

Page 67: ...ction 0 Input 1 Output P6SEL x P6DIR x P6IN x P6OUT x Pad Logic 1 0 1 0 Bus Keeper EN To ADC10 ADC10AE0 7 INCH 7 CAPD 7 From Comparator_A To Comparator_A to SVS Mux VLD 15 0 1 Port P6 P6 7 pin functio...

Page 68: ...3 P7 2 TMS S34 P7 3 TCK S35 0 1 Port P7 P7 0 to P7 3 pin functions PIN NAME P7 X X FUNCTION CONTROL BITS SIGNALS PIN NAME P7 X X FUNCTION JTAG Mode P7DIR x P7SEL x LCDS32 P7 0 TDO TDI S32 0 P7 x I O 0...

Page 69: ...d Logic 1 0 1 0 Bus Keeper EN To ADC10 ADC10AE0 0 1 INCH 0 1 CAPD 2 3 From Comparator_A To Comparator_A D EN Module X IN Port P7 P7 4 and P7 5 pin functions PIN NAME P7 X X FUNCTION CONTROL BITS SIGNA...

Page 70: ...mitt trigger Direction 0 Input 1 Output P7SEL x P7DIR x P7IN x D EN Module X IN Module X OUT P7OUT x Pad Logic 1 0 1 0 Bus Keeper EN P7 6 TA0 2 S25 Segment Sy LCDS24 Port P7 P7 6 pin functions PIN NAM...

Page 71: ...ulation Module Burn Test Fuse Controlled by JTAG Controlled by JTAG Controlled by JTAG DVCC DVCC DVCC During Programming Activity and During Blowing of the Fuse Pin TDO TDI Is Used to Apply the Test I...

Page 72: ...page 23 SLAS648B Corrected Timer_A3 Signal Connections and Timer_A5 Signal Connections tables pages 17 18 Removed bullet indicating that Segment A contains calibration data page 15 SLAS648C Added note...

Page 73: ...device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part...

Page 74: ...this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as...

Page 75: ...64 1000 330 0 24 4 13 0 13 0 2 1 16 0 24 0 Q2 MSP430F4132IRGZR VQFN RGZ 48 2500 330 0 16 4 7 3 7 3 1 5 12 0 16 0 Q2 MSP430F4132IRGZT VQFN RGZ 48 250 180 0 16 4 7 3 7 3 1 5 12 0 16 0 Q2 MSP430F4152IPM...

Page 76: ...2IPMR LQFP PM 64 1000 367 0 367 0 45 0 MSP430F4132IRGZR VQFN RGZ 48 2500 367 0 367 0 38 0 MSP430F4132IRGZT VQFN RGZ 48 250 210 0 185 0 35 0 MSP430F4152IPMR LQFP PM 64 1000 350 0 350 0 43 0 MSP430F4152...

Page 77: ...IEW Images above are just a representation of the package family actual package may vary Refer to the product data sheet for package details VQFN 1 mm max height RGZ 48 PLASTIC QUADFLAT PACK NO LEAD 7...

Page 78: ...rmal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance PACKAGE OUTLINE 4219044 A 05 2018 www ti com VQFN 1 mm max height PLASTIC QUADFLAT PACK NO LEAD RG...

Page 79: ...ias under paste be filled plugged or tented EXAMPLE BOARD LAYOUT 4219044 A 05 2018 www ti com VQFN 1 mm max height RGZ0048A PLASTIC QUADFLAT PACK NO LEAD SYMM SYMM LAND PATTERN EXAMPLE SCALE 15X 5 15...

Page 80: ...sign recommendations EXAMPLE STENCIL DESIGN 4219044 A 05 2018 www ti com VQFN 1 mm max height RGZ0048A PLASTIC QUADFLAT PACK NO LEAD SOLDER PASTE EXAMPLE BASED ON 0 125 mm THICK STENCIL EXPOSED PAD 67...

Page 81: ...3 NOM 0 25 0 45 0 75 Seating Plane 0 05 MIN Gage Plane 0 27 33 16 48 1 0 17 49 64 SQ SQ 10 20 11 80 12 20 9 80 7 50 TYP 1 60 MAX 1 45 1 35 0 08 0 50 M 0 08 0 7 NOTES A All linear dimensions are in mil...

Page 82: ......

Page 83: ...e resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reprod...

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