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Texas Instruments LM5064EVK User Manual Download Page 3

UVLO/EN

SCL

PWR

VEE_K

TIMER

PGD

GATE

SDAO

SMBA

ADR0
ADR1
ADR2

VAUX

VDD

OVLO

CL

DIODE

SDAI

VCC

OUT

RETRY

VEE

SENSE

SENSE_ K

VAUXH

VEE_OUT (-)

 

LM5064

200 k

Ÿ

16.9 k

Ÿ

0.15 µF 1 µF

30.1 k

Ÿ

0.003

FDB047N10

GND2 (+)

+

100 µF

10 nF

60V

5.0SMDJ60A

CMPT3904 

191 k

Ÿ

8.25 k

Ÿ

J1

SCL_ISO

SDA_ISO

SMBA_ISO

PGD

1

SWITCHES

CONNECTORS

ADR2

ADR1

ADR0

CL

RETRY

VDD

HIGH-Z

OVLO

TIMER

VDD

CT

CVDD

RPWR

VREF

CREF

1 µF

RS-

RS+

+

CO1

CO2

100 µF

VAUXH

PGD

VEE

OPEN

R1

R2

R2a

R3

R4

280 k

Ÿ

10.0 k

Ÿ

R5

R6

10 k

Ÿ

RP1

ASCL

ASDA

AGND

AVDD

BSCL

BSDA

BGND

BVDD

VEE

VDD

1 µF

10 k

Ÿ

RP2

VEE

SDAI/ 

SDAO

SCL

DGND

DVDD

1 µF

DGND

SDA_ISO

SCL_ISO

C1

C2

Si4800

PS2501-1-A

PS2501-1-A

DGND

DGND

RP4

DVDD

39.0 k

Ÿ

ISOLATION

U3

U4

U1

U1

DGND

DGND

VEE

RP5

DVDD

39.0 k

Ÿ

PGOOD_ISO

SMBA_ISO

RP6

VDD

10.0 k

Ÿ

RP3

VDD

4.99 k

Ÿ

DVDD

J2

SCL_ISO

SDA_ISO

SMBA_ISO

1

DGND

DGND

DVDD

0

Ÿ

RS

0

Ÿ

RS2

CS

OPEN

D1

B3100-13-F

DRAIN

VEE_OUT_S

GND2_S

GND1 (+)

GND1_S

VEE (-)

VEE_S

UVLO/ 

EN

R8

0

Ÿ

R7

0

Ÿ

PGD

VEE

PGOOD

SMBA

GATE

CAXH

OPEN

0

Ÿ

RAXH

DTEMP

0

Ÿ

RIN

CIN

Q1

RS1

VAUX

1

1

1

1000 pF

CD

www.ti.com

Getting Started

3

SNVA481B – October 2011 – Revised January 2020

Submit Documentation Feedback

Copyright © 2011–2020, Texas Instruments Incorporated

AN-2143 LM5064 Evaluation Kit

Figure 2. Full Evaluation Board Schematic

The schematic for the LM5064 evaluation board is shown in

Figure 2

. Connections to the PMBus interface

are provided by J2. Banana connectors provide input and output connections. Pins ADR0, ADR1, and
ADR2 are connected to switches that set the PMBus address of the device to one of 27 unique
addresses. Pins RETRY and CL are also connected to switches, allowing for hardware programmability of
the retry and current limit parameters, respectively. Test points are provided to conveniently probe signals
of interest.

4

Getting Started

The LM5064 evaluation kit hardware is shown in

Figure 3

.

Summary of Contents for LM5064EVK

Page 1: ...s for a specific application Use of the advanced telemetry and monitoring capabilities of this device requires the installation of the Intelligent Power Manager GUI however the LM5064 is capable of acting as a hot swap and protection circuit without any software installation Please check the LM5064 Negative Voltage System Pwr Mgmt Protection IC with PMBus SNVS718 for the latest software and data s...

Page 2: ...100 µF 60V 5 0SMDJ60A CMPT3904 191 kŸ 8 25 kŸ CT CVDD RPWR VREF CREF 1 µF CO1 CO2 100 µF R1 R2 R3 R4 280 kŸ 10 0 kŸ R5 R6 D1 B3100 13 F GND1 VEE DTEMP Q1 VAUX RS Simplified Schematic www ti com 2 SNVA481B October 2011 Revised January 2020 Submit Documentation Feedback Copyright 2011 2020 Texas Instruments Incorporated AN 2143 LM5064 Evaluation Kit 3 Simplified Schematic Figure 1 Simplified Schemat...

Page 3: ...ND DVDD 0Ÿ RS 0Ÿ RS2 CS OPEN D1 B3100 13 F DRAIN VEE_OUT_S GND2_S GND1 GND1_S VEE VEE_S UVLO EN R8 0Ÿ R7 0Ÿ PGD VEE PGOOD SMBA GATE CAXH OPEN 0Ÿ RAXH DTEMP 0Ÿ RIN CIN Q1 RS1 VAUX 1 1 1 1000 pF CD www ti com Getting Started 3 SNVA481B October 2011 Revised January 2020 Submit Documentation Feedback Copyright 2011 2020 Texas Instruments Incorporated AN 2143 LM5064 Evaluation Kit Figure 2 Full Evaluat...

Page 4: ...r the first time the user will be prompted to install the device drivers For the most current driver installation procedure refer to the README TXT file in the installation directory For a hot swap circuit to function reliably a low inductance connection to the input supply is recommended Its purpose is to minimize voltage transients which occur when the load current changes or is shut off If not ...

Page 5: ... be connected check the USB connection to the PCB FTDI connection to the evaluation module and verify that the power is present on the evaluation PCB by measuring the voltage between the GND1_s and VEE_s testpoints Ignoring the detection message allows use of the integrated design tool without the hardware connected Figure 6 LM5064 Block Level Representation Double click on the detected device ID ...

Page 6: ...re OT There is also an indicator if the output is in the latched off state LO The device will latch the output off after the number of user programmable retries is exceeded To clear the latched off condition the output can be toggled off and on by the red power button icon located in the top right of the LM5064 block representation To show a repetitive update of the device telemetry and status cli...

Page 7: ... them if they occur The device is capable of masking various faults and this functionality can be setup in the device configuration panel 7 GUI Event Log A GUI event log is provided to keep track of GUI configuration changes and device fault events To display the event log select View from the main menu bar and then View Event Log The event log will appear on the left side of the main GUI window T...

Page 8: ...rameters may be plotted at the same time as shown in Figure 8 Figure 8 LM5064 GUI with Telemetry Plotting Tool Enabled Device telemetry data is plotted as a black line that continually updates as the device is queried In addition to the device data the relevant warning and fault thresholds are also plotted Warning thresholds are shown as orange lines while fault thresholds are shown in red and blu...

Page 9: ...iguring the LM5064 Device 9 SNVA481B October 2011 Revised January 2020 Submit Documentation Feedback Copyright 2011 2020 Texas Instruments Incorporated AN 2143 LM5064 Evaluation Kit Figure 9 Device Configuration Panel ...

Page 10: ...cycled the device will default to values dictated by the hardware Current limit power up values are also set by the hardware The values for current limit can be set to either 26 mV CL VDD or 50 mV CL VEE The circuit breaker threshold can also be set in software to either 1 9 times or 3 9 times the current limit value Fault masking is possible for many of the device fault conditions Fault condition...

Page 11: ...re configured for a particular address power to the device needs to be cycled and the GUI restarted in order for the new address to take affect When invalid or incorrect inputs are given to the design tool text associated with the faulty input will turn red Positioning the mouse cursor over the red text will give additional information about any design conflict Component and parametric results are...

Page 12: ...ernal power measurement circuitry and used to calculate PEAK PIN The output can be turned off and on using the OPERATION button and the Identification Information can be obtained by clicking the Update ID Information button The rest of this page is used to monitor and diagnose warning and fault conditions The SMBA and PGOOD interrupts will indicate if a warning or fault has occurred and if the out...

Page 13: ...e VAUX and Temperature Additional functions include under and over voltage lock outs UVLO OVLO to ensure voltage is supplied to the load only when the system input voltage is within a specified range power limiting of the series pass MOSFET Q1 during turn on and a Power Good logic output PGD to indicate the output voltage status Upon applying the input voltage to the LM5064 Q1 is initially held of...

Page 14: ...oring the load current to determine if the fault is still present After the fault is removed the circuit powers up to normal operation at the next restart If the retry setting is changed to a limited number of retrys the LM5064 will stop retrying after the programmed number of retrys occur and keep Q1 shut off until UVLO EN is toggled or the output is turned off and then on via PMBus In a sudden o...

Page 15: ...button on the LM5064 block representation in the GUI 16 Board Layout and Probing Cautions Refer to the product datasheet for detailed layout guidelines For most applications the layout of this evaluation module as detailed in the PC Board Layout section of this document should be sufficient to provide a working solution with accurate telemetry The following should be kept in mind when the board is...

Page 16: ...ti com 16 SNVA481B October 2011 Revised January 2020 Submit Documentation Feedback Copyright 2011 2020 Texas Instruments Incorporated AN 2143 LM5064 Evaluation Kit LM5064 is conneced to the VEE plane 5 All testpoint signals are referenced to the VEE voltage 17 Performance Characteristics Figure 15 Insertion Time Delay 40 ms div Figure 16 Turn On Sequence into a 40Ω Load 40 ms div Figure 17 Circuit...

Page 17: ...6 0 4 0 2 0 0 0 2 0 4 0 6 0 8 1 0 PIN ERROR TEMPERATURE C CL VEE www ti com Performance Characteristics 17 SNVA481B October 2011 Revised January 2020 Submit Documentation Feedback Copyright 2011 2020 Texas Instruments Incorporated AN 2143 LM5064 Evaluation Kit Figure 21 IIN Error vs Temperature Figure 22 PIN Error vs Temperature ...

Page 18: ...40V 0 2A SOT 23 NXP Semiconductor PMS3904 1 Q1 MOSFET N CH 100V 120A DDPAK Fairchild FDB047N10 1 R1 200 kΩ RES 200 kΩ 1 0 1W 0603 Vishay Dale CRCW0603200KFKEA 1 R3 191 kΩ RES 191 kΩ 1 0 1W 0603 Vishay Dale CRCW0603191KFKEA 1 R2 16 9 kΩ RES 16 9 kΩ 1 0 1W 0603 Vishay Dale CRCW060316K9FKEA 1 R2a N A OPEN N A N A N A R4 3a 8 25 kΩ RES 8 25 kΩ 1 0 1W 0603 Vishay Dale CRCW06038K25FKEA 1 R5 280 kΩ RES 2...

Page 19: ...E_S Test Point TH Miniature Keystone Electronics 5015 20 ADR0 ADR1 ADR2 CLIMIT RETRY SWITCH SLIDE SPDT SMD J LEAD 50 V 100 mA Copal CJS 1201TA 5 GND1 GND2 VEE VEE_OUT Standard Banana Jack Uninsulated Keystone Electronics 575 8 1 H1 H2 H5 H6 Standoff Hex 0 5 L 4 40 Nylon Keystone Electronics 1902C 4 H3 H4 H7 H8 Machine Screw Round 4 40 x 1 4 Nylon Philips panhead B Fastener Supply NY PMS 440 0025 P...

Page 20: ...tober 2011 Revised January 2020 Submit Documentation Feedback Copyright 2011 2020 Texas Instruments Incorporated AN 2143 LM5064 Evaluation Kit 19 PC Board Layout Figure 23 Board Top Layer Figure 24 Board Mid Layer 1 Figure 25 Board Mid Layer 2 ...

Page 21: ... Board Layout 21 SNVA481B October 2011 Revised January 2020 Submit Documentation Feedback Copyright 2011 2020 Texas Instruments Incorporated AN 2143 LM5064 Evaluation Kit Figure 26 Board Bottom Layer viewed from top ...

Page 22: ...2 SNVA481B October 2011 Revised January 2020 Submit Documentation Feedback Copyright 2011 2020 Texas Instruments Incorporated Revision History Revision History Changes from A Revision May 2013 to B Revision Page Updated Figure 2 3 ...

Page 23: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Page 24: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Page 25: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Page 26: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Page 27: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Page 28: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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