Load
Current
GATE
Pin
TIMER
Pin
3.9V
1.2V
1
2
3
7
8
4.1 mA
pulldown
52
P
A
Gate Charge
74
P
A
2.4
P
A
Fault Timeout
Period
0.3V
Fault
Detection
I
LIMIT
t
RESTART
Fault Detection & Restart
14
SNVA481B – October 2011 – Revised January 2020
Copyright © 2011–2020, Texas Instruments Incorporated
AN-2143 LM5064 Evaluation Kit
If the power across Q1 does not exceed the programmed power limit, the LM5064 will also limit the drain
current to the current limit value determined by the sense resistance and the selected current limit voltage
threshold, 26 mV or 50 mV. The current limit will be maintained constant as the output voltage continues
to increase. During the current limit period, the voltage at the TIMER pin will be rising. If the TIMER
voltage reaches 3.9V before the current limit time has expired, the device will shut down and retry
according to the programmed retry configuration. If the TIMER does not expire, the output voltage will rise
and the drain current needed to charge the output capacitance will reduce. The output voltage will
continue to rise towards the the input voltage (V
DS
decreases to near zero), and the drain current then
reduces to a value determined by the load. Q1’s gate-to-source voltage then increases to its final value.
The circuit is now in normal operation mode.
Monitoring of the load current for faults during normal operation is accomplished using the current limit
circuit described above. If the load current increases to 8.7 Amps (26 mV across RS), Q1’s gate is
controlled to prevent the current from increasing further. When current limiting takes effect, the fault timer
limits the duration of the fault. At the end of the fault time-out period Q1 is shut off, denying current to the
load. The LM5064 then initiates a restart every 1.4 seconds. The restart consists of turning on Q1 and
monitoring the load current to determine if the fault is still present. After the fault is removed, the circuit
powers up to normal operation at the next restart. If the retry setting is changed to a limited number of
retrys, the LM5064 will stop retrying after the programmed number of retrys occur, and keep Q1 shut off
until UVLO/EN is toggled or the output is turned off and then on via PMBus.
In a sudden overload condition (e.g. when the output is shorted to VEE), it is possible that the current
could increase faster than the response time of the current limit circuit. In this case, the circuit breaker
sensor shuts off Q1’s gate rapidly when the voltage across RS reaches 49 mV. When the current reduces
to the current limit threshold, the current limit circuitry then takes over.
The PGD logic level output is low during turn-on and switches high when the VDS of the MOSFET is
below 1.25V. PGD switches low when the VDS of the MOSFET is above 2.5V. The high level voltage at
PGD can be any appropriate voltage up to +80V above VEE and can be higher or lower than the voltages
at VCC and OUT.
The UVLO thresholds are set by resistors R1 and R2, the OVLO thresholds are set by R3 and R4.
Optional resistor R2a can be added to set the UVLO and OVLO thresholds with only three resistors as
outlined in the LM5064 datasheet. Internal current sources at UVLO/EN and OVLO are used to set the
hysteresis levels.
13
Fault Detection & Restart
If the load current increases to the fault level (the typical current limit threshold of 8.7A), an internal current
source charges the timing capacitor at the TIMER pin. When the voltage at the TIMER pin reaches 3.9V,
the fault time-out period is complete and the LM5064 shuts off Q1. The restart sequence then begins,
consisting of seven cycles at the TIMER pin between 3.9V and 1.2V, as shown in
. When the
voltage at the TIMER pin reaches 0.3V during the eighth high-to-low ramp, Q1 is turned on. If the fault is
still present, the fault time-out period and the restart sequence repeat.
Figure 13. Fault Time-out and Restart Sequence