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7 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from July 14, 2021 to August 27, 2021

Page

• TB25 was added to the errata documentation....................................................................................................

• TB25 Description was updated.........................................................................................................................

• TB25 Workaround was updated.......................................................................................................................

Revision History

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MSP430FG6426 Microcontroller

SLAZ669P – MAY 2015 – REVISED AUGUST 2021

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Summary of Contents for Errata MSP430FG6426

Page 1: ...dvisories 2 4 Fixed by Compiler Advisories 3 5 Nomenclature Package Symbolization and Revision Identification 4 5 1 Device Nomenclature 4 5 2 Package Markings 4 5 3 Memory Mapped Hardware Revision TLV...

Page 2: ...CI39 USCI40 2 Preprogrammed Software Advisories Advisories that affect factory programmed software The check mark indicates that the issue is present in the specified revision Errata Number Rev A BSL1...

Page 3: ...or more details about the CPU bugs workarounds TI MSP430 Compiler Tools Code Composer Studio IDE MSP430 Optimizing C C Compiler Check the silicon_errata option MSP430 Assembly Language Tools MSP430 GN...

Page 4: ...Fully qualified development support product XMS devices and X development support tools are shipped against the following disclaimer Developmental product is intended for internal evaluation purposes...

Page 5: ...her guidance on how to locate the TLV structure and read out the HW_ID can be found in the device User s Guide www ti com Nomenclature Package Symbolization and Revision Identification SLAZ669P MAY 20...

Page 6: ...the device is in Active Mode CEOUT pin becomes low when the device enters LPM3 LPM4 modes Workaround When the comparator is disabled ensure at least one of the following 1 Output inversion is disable...

Page 7: ...fix implementation information IDE Compiler Version Number Notes IAR Embedded Workbench Not affected TI MSP430 Compiler Tools Code Composer Studio v4 0 x or later User is required to add the compiler...

Page 8: ...data in flash memory or data variable in RAM then the PC value is auto incremented by 2 after the jump instruction is executed therefore branching to a wrong address location in code and leading to w...

Page 9: ...eously set while CTSD16 module is inactive Description The CTSD16CTL CTSD16OFFG bit is erroneously set when the CTSD16 module is disabled and not actively converting CTSD16CCTLx CTSD16SC 0 This CTSD16...

Page 10: ...that no DMA access interrupts 20 bit wide accesses to the DMA address registers OR 2 When accessing the DMA address registers enable the Read Modify Write disable bit DMARMWDIS 1 or temporarily disab...

Page 11: ...y any previously executed instruction multiple times Workaround Do not enable the state storage display when executing instructions that require wait states Instead set a breakpoint after the instruct...

Page 12: ...watch point state storage and breakpoint functionality Workaround None Note This erratum affects debug mode only LCDB5 LCDB Module Category Functional Function Static DC charge can built up on dedicat...

Page 13: ...wakes from the low power mode Following the wakeup fromthe low power mode wait 32 48 80 or 100 cycles for core voltage levels 0 1 2 and 3 respectively before resetting DIVM xto zero and running MCLK a...

Page 14: ...m LPM2 LPM3 or LMP4 if an interrupt occurs within 1 us after the entry to the specified LPMx entry can be caused either by user code or automatically for example after a previous ISR is completed Devi...

Page 15: ...LPMx Note that this will cause increased power consumption when in LPMx Refer to the MSP430 Driver Library MSPDRIVERLIB for proper PMM configuration functions Use the following function PMM15Check vo...

Page 16: ...0 PMM Module Category Functional Function Unexpected SVSL SVML event during wakeup from LPM2 3 4 in fast wakeup mode Description If PMM low side is configured to operate in fast wakeup mode during wak...

Page 17: ...et function after access to SVSMHCTL or SVSMLCTL To prevent lock up caused by use case 2 a timeout for the SVSMLDLYIFG flag check should be implemented to 300us PORT15 PORT Module Category Functional...

Page 18: ...ode 1 Set TBxCCTLn CLLD 0x00 2 Enable the Timer B interrupt TBIE in TBxCTL 3 Update TBxCCRn value within interrupt routine Timer B Interrupt would need to be serviced in a timely manner to mitigate di...

Page 19: ...n an I2C multi master system UCMM 1 under the following conditions 1 the master is configured as a transmitter UCTR 1 AND 2 the start bit is set UCTXSTT 1 if the I2C bus is unavailable then the USCI m...

Page 20: ...CSTTIFG UCSTPIFG UCNACKIFG Description Unpredictable code execution can occur if one of the hardware clear able IFGs UCSTTIFG UCSTPIFG or UCNACKIFG is set while the global interrupt enable is set by s...

Page 21: ...tting pre loaded asynchronously when writing to the USCIA TXBUF register TX data in the internal buffer is shifted by one bit after the RX data is received Workaround Reinitialize TXBUF before using S...

Page 22: ...from July 14 2021 to August 27 2021 Page TB25 was added to the errata documentation 6 TB25 Description was updated 18 TB25 Workaround was updated 18 Revision History www ti com 22 MSP430FG6426 Microc...

Page 23: ...are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and...

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