Texas Instruments Errata MSP430FG6426, Manual

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USCI34
(continued)
USCI Module
if (PTxData < = PTxDataEnd) // Check TX byte counter
{
UCB0TXBUF = *+; // Load TX buffer
}
else
{
UCB0CTL1 |= UCTXSTP; // I2C stop condition
IFG2 &= ~UCB0TXIFG; // Clear USCI_B0 TX int flag
__bic_SR_register_on_exit(CPUOFF); // Exit LPM0
}
}
}
USCI35 USCI Module
Category Functional
Function Violation of setup and hold times for (repeated) start in I2C master mode
Description In I2C master mode, the setup and hold times for a (repeated) START, t
SU,STA
and t
HD,STA
respectively, can be violated if SCL clock frequency is greater than 50kHz in standard
mode (100kbps). As a result, a slave can receive incorrect data or the I2C bus can be
stalled due to clock stretching by the slave.
Workaround If using repeated start, ensure SCL clock frequencies is < 50kHz in I2C standard mode
(100 kbps).
USCI39 USCI Module
Category
Functional
Function USCI I2C IFGs UCSTTIFG, UCSTPIFG, UCNACKIFG
Description Unpredictable code execution can occur if one of the hardware-clear-able IFGs
UCSTTIFG, UCSTPIFG or UCNACKIFG is set while the global interrupt enable is set
by software (GIE=1). This erratum is triggered if ALL of the following events occur in
following order:
1. Pending Interrupt: One of the UCxIFG=1 AND UCxIE=1 while GIE=0
2. The GIE is set by software (e.g. EINT)
3. The pending interrupt is cleared by hardware (external I2C event) in a time window of 1
MCLK clock cycle after the "EINT" instruction is executed.
Workaround Disable the UCSTTIE, UCSTPIE and UCNACKIE before the GIE is set. After GIE is set,
the local interrupt enable flags can be set again.
Assembly example:
bic #UUCSTTIE, UCBxIE ; disable all self-clearing interrupts
NOP
EINT
bis #UUCSTTIE, UCBxIE ; enable all self-clearing interrupts
Advisory Descriptions www.ti.com
20 MSP430FG6426 Microcontroller SLAZ669P – MAY 2015 – REVISED AUGUST 2021
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