Texas Instruments DRA76xP-ACD, User Manual, Page: 8 / 38

D
C
AN
1
QSPI-Mux A:
SCLK, CS0, D[3:0],
RTCLK
VOUT1
R
G
MI
I0
R
G
MI
I1
Q
SPI
UART1
G
PMC
VIN2A
I2C1
I2C3
EMI
F
1
EMU
60-pin MIPI JTAG
CAN PHY
DCAN1:
TX, RX
CAN/CAN-FD
Headers
DCAN2-
Mux L:
TX, RX
D
C
AN
2
MMC
1
MMC1:
CLK, CMD,
D[3:0, SDCD]
SD/MMC
Socket
VOUT1:
CLK, DE, HS,
VS, D[23:0]
Display Expansion
CSI2_0
VIN2A-Mux D: CLK, VS, HS,
D[11:0]
SPI1/GPIO: CLK,
FSX, D[1:0]
Leopard Imaging
(Parallel)
GPMC-Mux A:
A[18:13], CS[2]
GPMC-Mux C:
A[27:19], CS[1]
GPMC-Mux B:
A[12:0], AD[15:0], CS[3]
GPMC:
CLK, BEN[1:0], ADVN/ALE,
OEN/REN, WEN, CS0, WAIT0
NOR QSPI DDR3L
EMIF1:
All
EMU-Mux ?:
EMU[19:2]
JTAG:
TCK, RTCK, TMS,
TDI, TDO,
TRSTN, EMU[1:0]
JT
AG
RGMII0-Mux J:
TXC, TXCTL,
TXD[3:0], RXC,
RXCTL, RXD[3:0]
MD
IO
EMAC PHY
MDIO-
Mux J::
CLK, D
RGMII1-Mux F:
TXC, TXCTL,
TXD[3:0], RXC,
RXCTL, RXD[3:0]
RJ-45
UART1:
TX, RX
UART3-Mux K:
TX, RX, RTS,
CTS
USART
Temp
PMIC(s)
EEPROM
I2C1: SCL, SDA
Micro-USB
USB3.0 (DR)
Expansion
Connector
SoC
I2C3: SCL, SDA
EMAC PHY
RJ-45
CAN PHY
EMI
F
2
DDR3L
EMIF2:
All
NAND
EMMC-Mux C:
CLK, CMD,
D[7:0]
MMC
2
QSPI
U
AR
T
3
COM8Q
MMC
4
McASP
7
McASP7-Mux H:
CLK, FSX, D[1:0]
MMC4:
CLK, CMD, D[3:0]
VOUT3B
VOUT3-Mux B:
CLK, DE, HS, VS,
D[23:0]
Display Panel
FPD Link
PHY
SPI1
HDMI
PCIe
USB2
SATA
USB1
DDC
Leopard Imaging
(Parallel)
CSI2 Expansion
CSI2_0: DX[4:0],
DY[4:0]
CSI2_1
CSI2_1: DX[2:0],
DY[2:0]
CLK GEN
USB HUB
MLB
McASP3
McASP3-Mux H:
CLK, FSX, D[1:0]
CODEC
Audio Jacks
O
SC
0
O
SC
1
OSC0:
XI, XO
OSC1:
XI, XO
USB2.0 (Host)
USB2:
(To Display Panel)
USB2:
(From Hub)
USB2: DP, DN
USB1: DP/N, TXP/N,
RXP/N
SATA: TXP/N, RXP/N
PCIe: TX0P/N, RX0P/N
I2C5
MLB: CLKP/N, SIGP/
N, DP/N
HDMI
HDMI:
CLKP/N, D0P/N, D1P/N, D2P/
N
DDC-Mux L:
SCL, SDA
Codec
IO EXP(s)
CLK CLN
Disp Exp
FPD Disp
LI-S Cam
CSI2 Exp
LI-P Cam
I2C5: SCL, SDA
PMIC(s)
Power
Pwr Meas
Copyright © 2017, Texas Instruments Incorporated
Hardware
www.ti.com
8 SPRUII5A – December 2017 – Revised November 2018
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Copyright © 2017–2018, Texas Instruments Incorporated
DRA77xP/DRA76xP-ACD CPU EVM Board
3 Hardware
3.1 Hardware Architecture
Figure 4 shows the CPU board’s functional block diagram.
Figure 4. CPU Board Block Diagram