Texas Instruments DRA76xP-ACD, User Manual, Page: 25 / 38

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Signal Multiplex Logic
25 SPRUII5A – December 2017 – Revised November 2018
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DRA77xP/DRA76xP-ACD CPU EVM Board
4.2 GPMC/VOUT3 Selection (Mux B)
Table 17 is part of the SoC pinmux table for GPMC. The SoC device supports additional functions not
shown in Table 17 . The functions shown are intended to reflect those supported on the EVM. These
include:
• Memory Bus (GPMC): AD[15:0], A[12:0], CS[3]
• General Purpose I/O (GPIO2): GPIO2_2
• Video Output Port (VOUT3): CLK, HSYNC, VSYNC, DE, D[23:0]
• Boot Mode Selection (SYSBOOT): SYSBOOT[15:0]
Table 17. SoC Pinmux for GPMC/VOUT3
Pad Name Function 1 Function 4 Function 15 Function 16
gpmc_ad[15] GPMC gpmc_ad[15] DSS vout3_d[15] CHIPGLUE sysboot15
gpmc_ad[14] GPMC gpmc_ad[14] DSS vout3_d[14] CHIPGLUE sysboot14
gpmc_ad[13] GPMC gpmc_ad[13] DSS vout3_d[13] CHIPGLUE sysboot13
gpmc_ad[12] GPMC gpmc_ad[12] DSS vout3_d[12] CHIPGLUE sysboot12
gpmc_ad[11] GPMC gpmc_ad[11] DSS vout3_d[11] CHIPGLUE sysboot11
gpmc_ad[10] GPMC gpmc_ad[10] DSS vout3_d[10] CHIPGLUE sysboot10
gpmc_ad[9] GPMC gpmc_ad[9] DSS vout3_d[9] CHIPGLUE sysboot9
gpmc_ad[8] GPMC gpmc_ad[8] DSS vout3_d[8] CHIPGLUE sysboot8
gpmc_ad[7] GPMC gpmc_ad[7] DSS vout3_d[7] CHIPGLUE sysboot7
gpmc_ad[6] GPMC gpmc_ad[6] DSS vout3_d[6] CHIPGLUE sysboot6
gpmc_ad[5] GPMC gpmc_ad[5] DSS vout3_d[5] CHIPGLUE sysboot5
gpmc_ad[4] GPMC gpmc_ad[4] DSS vout3_d[4] CHIPGLUE sysboot4
gpmc_ad[3] GPMC gpmc_ad[3] DSS vout3_d[3] CHIPGLUE sysboot3
gpmc_ad[2] GPMC gpmc_ad[2] DSS vout3_d[2] CHIPGLUE sysboot2
gpmc_ad[1] GPMC gpmc_ad[1] DSS vout3_d[1] CHIPGLUE sysboot1
gpmc_ad[0] GPMC gpmc_ad[0] DSS vout3_d[0] CHIPGLUE sysboot0
gpmc_a[0] DSS vout3_d[16]
gpmc_a[1] GPMC gpmc_a[1] DSS vout3_d[17]
gpmc_a[2] GPMC gpmc_a[2] DSS vout3_d[18]
gpmc_a[3] GPMC gpmc_a[3] DSS vout3_d[19]
gpmc_a[4] GPMC gpmc_a[4] DSS vout3_d[20]
gpmc_a[5] GPMC gpmc_a[5] DSS vout3_d[21]
gpmc_a[6] GPMC gpmc_a[6] DSS vout3_d[22]
gpmc_a[7] GPMC gpmc_a[7] DSS vout3_d[23]
gpmc_a[8] GPMC gpmc_a[8] DSS vout3_hsync
gpmc_a[9] GPMC gpmc_a[9] DSS vout3_vsync
gpmc_a[10] GPMC gpmc_a[10] DSS vout3_de
gpmc_a[11] GPMC gpmc_a[11] DSS vout3_fld
gpmc_a[12] GPMC gpmc_a[12] GPIO2 gpio2_2
gpmc_cs[3] DSS vout3_clk
Mux B: The selector bit and selects between on-board memories and FPD-Link LCD panel. The selection
is made using the IO expander #2, bit P0. The defaults are set to enable GPMC to NOR/NAND
memories – which is required for SYSBOOT mode latching.
If booting from NOR/NAND memories, the selection for chip select 0 is made using switch SW6 position 1
(NOR) and position 2 (NAND).
NOTE: Only one of these boot devices can be enabled at any time