Hardware
14
SPRUII5A – December 2017 – Revised November 2018
Copyright © 2017–2018, Texas Instruments Incorporated
DRA77xP/DRA76xP-ACD CPU EVM Board
3.7
JTAG/Emulator and Trace
The JTAG emulation interface is supported through the MIPI 60 pin interfaces. The EVM kit includes an
adapter(s) for supporting other JTAG interfaces, including TI’s 20 pin cJTAG interface. Reset (warm reset)
via the emulator is supported.
TRACE/Debug is also support through the MIPI-60 connector. The EVM supports up to 20 trace bits. At
the SoC and EVM level, the trace pins are muxed with VOUT1 function. Therefore, these interfaces
cannot be used simultaneously. When using TRACE, it is recommended to disconnect any
peripheral/expansion board that might be connected to VOUT1 (connected using J19). This is done to
minimized the loading/signal integrity impact on TRACE interface.
3.8
UART Terminal
The EVM supports a single UART connection to be used for user terminal. A FT232 device is used to
transport the UART information over USB to a host PC. The EVM is designed to use SoC’s UART1 as the
primary terminal connection, and is connected to port A of the USART transceiver. The USB-side of the
FT2232 device is powered from the USB port, and the connection will stay active regardless of power
state of the EVM. The green LED (DS6) is used to indicate the USB connection is available.
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USART device to be used: FTD Chip FT232RQ
A USB cable (mini-B to type A) is used to connect the EVM to a PC, and is included as part of the EVM
kit.
The EVM can support a second UART connection the FT232 device and is intended to be used for
peripheral booting. However, this configuration requires board modifications, and is recommended only for
specific users.
3.9
DCAN/CAN Interfaces
The EVM supports access to two DCAN interfaces though pin headers: JP1 and JP2. The SoC supports
CAN-FD on either DCAN interface. Both interfaces are connected to 10-pin CAN/CAN-FD headers (J20,
J21) through a CAN/CAN-FD transceiver.
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CAN-FD device used: Texas Instruments TCAN1042HGVQ1
3.10 Universal Serial Bus (USB)
The SoC includes two integrated USB transceivers, both supported on the EVM. USB3.0 super-speed bus
(USB1) is supported using port USB1 to a mini-AB type connector (P8). This interface supports rates up to
5 Gbps and can operate in host or device mode. The EVM includes capabilities to set and read the
connector’s ID pin. This supported using the IO expander (EXP2 P1 for USB1). In addition, DIP switch
SW2 provides ability to manual set the individual ID value either high (OFF) or low (ON).
USB2.0 interface is connected to high speed USB Hub, and can support rates up to 480 Mbps. The hub
provides 2 downstream USB Host ports. One port is connected to Type-A Host connecter, and is available
for user to attached external USB devices. The second port is connected to the LCD panel interface, and
it is expected to be used for USB-based touch controllers.
All USB interfaces can supply VBUS to peripheral when in host mode by enabling the VBUS switch
(controlled via the SoC). However, the EVM cannot be powered from VBUS when operating in device
mode.
3.11 Wired Ethernet
Dual Gigabit Ethernet ports are supported on the EVM. RGMII ports 0 and 1 drive the Texas Instruments
DP83867 Gigabit PHYs. The PHYs are configured through the Management Data Input/Output (MDIO)
bus, with the address set to 0x2 (port 0) and 0x3 (port 1). PHYs are reset at Power-on, but can also be
independently reset using the IO expander. Both ports share a common interrupt signal (GPIO6_16).
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IO Expander Control: EXP1, P10 (PHY 0 Reset), P11 (PHY 1 Reset)