Hardware
15
SPRUII5A – December 2017 – Revised November 2018
Copyright © 2017–2018, Texas Instruments Incorporated
DRA77xP/DRA76xP-ACD CPU EVM Board
NOTE:
For the PHY configuration, configure DP83867’s RGMII Control Register (RGMIICTL) for
RGMII mode and the RGMII Delay Control Register (RGMIIDCTL) for 0 ns TX delay, 2.25 ns
RX delay. Set IO Drive Strength Register (IO_IMPEDANCE_CTRL) to maximum drive.
3.12 Video Output
The EVM supports three different options for supporting video output: HDMI (integrated PHY with audio),
generic LCD/Display Panel with touch, and FPD-link. Each can be supported independently or all can be
used simultaneously.
3.12.1
HDMI Display
The SoC includes a integrated HDMI display interface, which is supported on a type A HDMI connector.
The interface supports 1080p with 24b color. A communication channel (DDC/CEC) is supported to the
HDMI connector for communication with the HDMI panel. A monitor detect indication is also provided. The
DDC/CED interface and monitor detect signals (HPD) are translated through the transceiver, and can be
controlled using GPIO from the SoC.
•
DDC Transceiver used: Texas Instruments TPD12S016
•
Transceiver Control: GPIO7_30 (Lvl Shift Reg Enable, HPD), GPIO7_31 (DDC/CEC Enable)
3.12.2
LCD/Display With Touch Panel
The EVM supports a generic LCD/display panel interface for supporting video output to a display panel.
The SoC VOUT1 resource is used drive up to 24b RGB data to interface. The interface supports resource
connections for interfacing with a touch panel for advanced user interfaces. These include a control bus
(I2C1), USB host interface (USB2), and interrupt for touch indications.
•
Connector used: Sametc QSH-030-01
An LCD panel is not included with the CPU EVM, but can be ordered and included as part of an assembly
kit.
3.12.3
FPD-Link III Output/Panel
The EVM includes a 720p FPD-link III parallel to serial interface on VOUT3. It supports up to 24 bits of
data and can operate at pixel rates up to 85 MHz. An interrupt is supported to enable back-channel
communication, typically needed if supporting touch screen. Power control to the panel is also supported
via SoC GPIO. The transceiver is configured using I2C (port 3, 0x1B).
Note that the interface clock from the SoC to transceiver is first passed through a de-jitter device to ensure
the clock is optimal. This is typically needed if the frequency of the clock is above 70 MHz. The de-jitter IC
is configured via I2C (port 1, 0x65).
•
Serializer device used: Texas Instruments DS90UH921Q
•
Clock de-jitter device used: Texas Instruments CDCE813-Q1
•
Connector used: Automotive HSD Connector, right-angle plug for PCB, Rosenberger D4S20D-40ML5-
Z
3.13 Video Input
3.13.1
Parallel Imaging
Parallel video input is supported through connections from external sensors and transceivers. The SoC
port VIN2A is routed to the connector interface designed to mate with the camera sensors from Leopard
Imaging. This approach provides flexibility for customers to select from a variety of available modules,
while also supporting connections of custom solutions. The attached module can be configured using
either I2C (port 5) or SPI (port 1).
•
Connector used: FPC 36 position, 0.5 mm, Molex 052559-3679