DAC8742HEVM Hardware Overview
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8
SLAU700A – June 2017 – Revised November 2017
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Copyright © 2017, Texas Instruments Incorporated
DAC8742H Evaluation Module
4.4
DAC8742H Reference Connection
The DAC8742HEVM connects to an optional external reference through the J5 terminal block, or it can be
supplied by the internal reference of the DAC8742H device (see
Table 6
).
Table 6. DAC8742HEVM Reference Connection
Connector
Connection Type
Description
J5
REF Terminal Block
Connects external reference to REF net
JP7
Populate
Connects external reference to REF net
4.5
Digital Inputs
The digital communication lines of the DAC8742H device can be accessed through the USB2ANY header
connection (J2) or the J6 header block, which are listed in
Table 7
and
Table 8
, along with the digital input
signals of the DAC8742H device.
Table 7. Digital Signal Definition
Name
Connector
Description
JP13
IF_SEL
(1 – 2) IOVDD: SPI mode
(2 – 3) GND: UART mode
JP15, JP17
CLK_CFG0
(JP15 – closed, JP17 – open): CLK_CFG0 set to IOVDD
(JP15 – open, JP17 – closed): CLK_CFG0 set to GND
(JP15 – closed, JP17 – closed): CLK_CFG0 set to (0.5) IOVDD
JP14
CLK_CFG1
(1 – 2) CLK_CFG1 set to IOVDD
(2 – 3) CLK_CFG1 set to GND
JP20
/XEN
(1 – 2) GND: external crystal
(2 – 3) IOVDD: external oscillator or internal oscillator required
JP19
REF_EN
(1 – 2) GND: external reference
(2 – 3) IOVDD: internal reference
JP18
BPF_EN
(1 – 2) GND: external bandpass required
(2 – 3) IOVDD: internal bandpass filter
Table 8. J6 Digital Signal Definition
Name
Connector
J6-1
UART_OUT/SDO
J6-2
DUPLEX/SDI
J6-3
/UART_RTS/SCLK
J6-4
UART_IN/CS
J6-5
CD/IRQ
J6-6
/RST
J6-7
IOVDD
J6-8
GND
NOTE:
Control the REF_EN, BPF_EN, and IF_SEL lines through the GUI.
The DAC8742H data sheet lists acceptable clock configurations, and they are also listed in
Table 9
for
reference.
