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DAC8742HEVM Hardware Overview

7

SLAU700A – June 2017 – Revised November 2017

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Copyright © 2017, Texas Instruments Incorporated

DAC8742H Evaluation Module

4

DAC8742HEVM Hardware Overview

The subsequent sections provide detailed information on the EVM hardware, and jumper configuration
settings.

Table 4

displays the default configurations of all jumper connections on the DAC8742HEVM.

Connect the USB extender cable from the USB2ANY to the PC.

Table 4. Default Jumper Settings

Jumper

Position

Description

JP1

Shunt on 1 – 2

HART: Connects to 3.6864-MHz external crystal

JP2

Shunt on 1 – 2

HART: Connects to 3.6864-MHz external crystal

JP4

Shunt on 2 – 3

Connects TS5N412PW device

JP5

Populate

HART: Connects IOVDD to AVDD for single supply
operation

JP6

Shunt on 1 – 2

Connects IOVDD to USB2ANY 3.3-V supply

JP8

Populate

HART: Connects to 0.022-µF load capacitor

JP9

Shunt on 2 – 3

HART: Connects to MOD_IN

JP10

Shunt on 2 – 3

HART: Connects to 2200 pF

JP11

Shunt on 1 – 2

HART: Connects to 2200 pF

JP14

Shunt on 2 – 3

CLK_CFG1 set to GND

JP16

Shunt on 5 – 6

HART: Connects to 680 pF

JP17

Populate

CLK_CFG0 set to GND

JP20

Shunt on 1 – 2

/XEN set to GND

4.1

Electrostatic Discharge Warning

Many of the components on the DAC8742HEVM are susceptible to damage by electrostatic discharge
(ESD). Customers are advised to observe proper ESD handling precautions when unpacking and handling
the board, including the use of a grounded wrist strap at an approved ESD workstation.

4.2

Connecting the Hardware

To connect the USB2ANY to the EVM board, align and firmly connect the keyed ribbon connector to the
J2 connector. Verify the connection is snug, as loose connections may cause intermittent operation.

4.3

DAC8742HEVM Power Configurations

The DAC8742HEVM provides electrical connections to the device supply pins. The connectors and
optional configurations are shown in the

Table 5

.

Table 5. DAC8742HEVM Power Supply Configuration

Connector

Connection Type

Description

J3

AVDD terminal block

Connects external supply to AVDD net

J4

IOVDD terminal block

Connects external supply to IOVDD net

JP5

Shunt connection

Connects AVDD to IOVDD

JP6

Shunt (1 – 2)

Connects USB2ANY 3.3 V to IOVDD

Shunt (2 – 3)

Connects IOVDD net to J4 terminal block

USB2ANY can supply IOVDD and AVDD by populating the JP6 shunt to position (1 – 2) and connecting
shunt J5.

Summary of Contents for DAC8742H

Page 1: ...VM Software 6 3 2 DAC8742H Software Installation 6 4 DAC8742HEVM Hardware Overview 7 4 1 Electrostatic Discharge Warning 7 4 2 Connecting the Hardware 7 4 3 DAC8742HEVM Power Configurations 7 4 4 DAC8742H Reference Connection 8 4 5 Digital Inputs 8 4 6 Clock Configuration 9 4 7 HART PAFF Shunt Selection 10 5 DAC8742HEVM Software Overview 11 5 1 Starting the DAC8742HEVM Software 11 5 2 DAC8742HEVM ...

Page 2: ...42HEVM Power Supply Configuration 7 6 DAC8742HEVM Reference Connection 8 7 Digital Signal Definition 8 8 J6 Digital Signal Definition 8 9 Clock Configuration 9 10 XTAL1 and XTAL2 Configuration Settings 9 11 Internal Mode Shunt Selection 10 12 External Filter Mode With Internal REF Shunt Selection 10 13 DAC8742H Test Board Bill of Materials 19 Trademarks Microsoft Windows are registered trademarks ...

Page 3: ...oduct Information Center or visit the Texas Instruments E2E Community http E2E ti com if any component is missing TI highly recommends that the user verify the latest versions of the related software at the TI website www ti com Table 1 Contents of DAC8742H Kit Item Quantity DAC8742HEVM PCB evaluation board 1 USB2ANY 1 1 2 Related Documentation From Texas Instruments The following document provide...

Page 4: ...rovides the overall system setup for the EVM A PC runs software that communicates with the USB2ANY platform which generates the optional IOVDD or AVDD power and digital signals used to communicate with the EVM board Test point connections are included on the EVM board for external power supplies Figure 1 displays the DAC8742HEVM system setup Figure 1 DAC8742HEVM Hardware Setup 2 1 DAC8742H Hardwar...

Page 5: ...vide the AVDD and IOVDD supply through an external supply and access all digital communication lines through their respective digital test points This information is provided in Table 3 Table 3 J2 USB2ANY and Digital Signal Definition Pin On J2 Signal Description 2 COM_SELECT Select between SPI or UART 4 6 8 16 27 28 GND CS general purpose I O 12 CS_GPIO6 SPI CS or general purpose I O 13 RXD_MISO ...

Page 6: ...rating systems 3 2 DAC8742H Software Installation The software is available through the EVM product folder on the TI website Once the software is downloaded onto the PC navigate to the DAC8742HEVM folder and run the setup exe file as shown in Figure 3 When the software is launched an installation dialog will open and prompt the user to select an installation directory If left unchanged the softwar...

Page 7: ...5 6 HART Connects to 680 pF JP17 Populate CLK_CFG0 set to GND JP20 Shunt on 1 2 XEN set to GND 4 1 Electrostatic Discharge Warning Many of the components on the DAC8742HEVM are susceptible to damage by electrostatic discharge ESD Customers are advised to observe proper ESD handling precautions when unpacking and handling the board including the use of a grounded wrist strap at an approved ESD work...

Page 8: ...e 8 along with the digital input signals of the DAC8742H device Table 7 Digital Signal Definition Name Connector Description JP13 IF_SEL 1 2 IOVDD SPI mode 2 3 GND UART mode JP15 JP17 CLK_CFG0 JP15 closed JP17 open CLK_CFG0 set to IOVDD JP15 open JP17 closed CLK_CFG0 set to GND JP15 closed JP17 closed CLK_CFG0 set to 0 5 IOVDD JP14 CLK_CFG1 1 2 CLK_CFG1 set to IOVDD 2 3 CLK_CFG1 set to GND JP20 XE...

Page 9: ...nnected at XTAL1 1 1 0 No output Internal oscillator enabled 1 1 1 1 2288 MHz output Internal oscillator enabled CLKO enabled 0 0 0 No output Crystal oscillator enabled 0 0 1 3 6864 MHz output 3 6864 MHz crystal oscillator CLKO enabled 0 1 0 1 8432 MHz output 1 8432 MHz crystal oscillator CLKO enabled 0 1 1 1 2288 MHz output 1 2288 MHz crystal oscillator CLKO enabled 1 0 0 5 IOVDD No output 4 MHz ...

Page 10: ...tion Description JP8 CLOSED HART HART Connects to 0 022 µF load capacitor OPEN PAFF JP9 1 2 HART PAFF Connects MODINF to MOD_IN terminal block J7 JP10 1 2 PAFF HART Connects to 2200 pF 2 3 HART PAFF Connects to 2700 pF JP11 1 2 HART HART Connects to 2200 pF 2 3 PAFF PAFF Connects to 2700 pF JP12 1 2 HART PAFF Connects MODINF to MOD_IN terminal block J7 JP16 5 6 HART HART Connects to 680 pF 7 8 PAF...

Page 11: ...nstruments folder in the All Programs menu and select the DAC8742H EVM icon Figure 4 DAC8742HEVM GUI Location This section describes the features of the DAC8742H EVM software The software as shown in Figure 4 provides basic control of all the registers and functions to the DAC8742H device If the USB2ANY is correctly connected the STATUS displays HARDWARE CONNECTED If the USB2ANY is not properly co...

Page 12: ...aluation Module 5 2 DAC8742HEVM Software Features The DAC8742H EVM incorporates interactive functions that help configure the DAC8742H device These functions are built into several GUI pages as shown in Figure 6 The Page Selection menu allows the user to switch between the pages each page representing a feature of the software Figure 6 DAC8742H EVM Software Page Selection ...

Page 13: ...w Level Configuration Page The values of the register map can also be saved by pressing the Save Configuration button under the File menu option Additionally the configuration files are accessed through the Load Configuration button Other options selectable by the user are the Update Mode Write Selected red box Read Selected orange box Write Modified gray box and Read All yellow box buttons All bu...

Page 14: ...ible for different modes of communication UART SPI as well as HART or PAFF mode of operation The first section is responsible for choosing the form of digital communication The COMMUNICATION MODE panel is responsible for selecting between HART and PAFF The remaining three input controls are only operable in SPI but are used to modify the FIFO level set register 0x25 and TX_AMP parameter of the MOD...

Page 15: ...H Evaluation Module The panel to the aforementioned text is shown in Figure 10 Figure 10 MODE Section The second section displays the state to several digital inputs of the DAC8742HEVM device Such digital inputs include the RESET IF_SEL REF_EN and BPFEN pin These buttons are shown in Figure 11 highlighted with yellow boxes Figure 11 DAC8742HEVM Digital Input Selection ...

Page 16: ... are input press the Generate Write button Green box and this shifts the contents into the FIFO and transmit for the specified industrial protocol HART PAFF Press the Generate Read button Orange box if you are expecting an incoming transmission to the DAC8742H device Once pressed the HART PAFF Read field Yellow box will update with the captured data NOTE For Read operations in UART the user must s...

Page 17: ...AGND 1 2 3 JP19 IOVDD 1 00M R17 REF_EN AGND 1 2 3 JP20 IOVDD 1 00M R18 AGND 0 022µF C15 2 2µF C13 AGND JP8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 19 21 23 25 27 29 16 18 20 22 24 26 28 30 J2 RXD_MISO USB_3p3 REF_EN BPF_EN COM_SELECT CS_GPIO6 TXD_MOSI SCLK_GPIO2 IF_SEL RST USB2ANY Connection AGND AGND 1 2 3 JP3 IOVDD Selectable COM UARTRTS SCLK SCLK_GPIO2 TXD_MOSI RXD_MISO CS_GPIO6 DUPLEX SDI UARTO...

Page 18: ...700A June 2017 Revised November 2017 Submit Documentation Feedback Copyright 2017 Texas Instruments Incorporated DAC8742H Evaluation Module 6 2 DAC8742HEVM PCB Components Layout Figure 14 shows the layout of the components for the DAC8742HEVM board Figure 14 DAC8742HEVM PCB Components Layout ...

Page 19: ...15 1 0 022 µF Capacitor ceramic 0 022 µF 50 V 10 X7R 0603 0603 GRM188R71H223KA01D MuRata C16 C21 2 300 pF Capacitor ceramic 300 pF 50 V 5 C0G NP0 0603 0603 GRM1885C1H301JA01D MuRata C17 1 2700 pF Capacitor ceramic 2700 pF 50 V 5 C0G NP0 0603 0603 GRM1885C1H272JA01D MuRata C18 1 100 pF Capacitor ceramic 100 pF 50 V 5 C0G NP0 0603 0603 GRM1885C1H101JA01D MuRata C19 1 2200 pF Capacitor ceramic 2200 p...

Page 20: ...1 1 0 RES 0 5 0 1 W 0603 0603 CRCW06030000Z0EA Vishay Dale R2 R3 R11 3 1 00 k RES 1 00 k 1 0 1 W 0603 0603 CRCW06031K00FKEA Vishay Dale R4 R5 R6 R7 R8 R12 R14 R16 R17 R18 R19 11 1 00 Meg RES 1 00 M 1 0 1 W 0603 0603 RC0603FR 071ML Yageo America R9 1 536 k RES 536 k 1 0 1 W 0603 0603 RC0603FR 07536KL Yageo America R10 1 27 0 k RES 27 0 k 1 0 1 W 0603 0603 RC0603FR 0727KL Yageo America R13 1 620 k R...

Page 21: ...est point multipurpose black TH Black multipurpose test point 5011 Keystone U1 1 4 bit 1 of 2 FET multiplexer demultiplexer high bandwidth bus switch PW0016A TSSOP 16 PW0016A TS5N412PW Texas Instruments Texas Instruments U2 1 HART FOUNDATION Fieldbus PROFIBUS PA Modem PBS0032A PBS0032A DAC8742HPBS Texas Instruments Texas Instruments Y1 1 Crystal 3 6864 MHz 18 pF SMD Body12 7 4 7 mm ABLS 3 6864MHZ ...

Page 22: ...ed Default Jumper Settings table 7 Changed DAC8742HEVM Power Configurations section shunt information and DAC8742HEVM Power Supply Configuration table 7 Changed DAC8742H Reference Connection section and table 8 Changed Digital Inputs section and Digital Signal Definition table 8 Added J6 Digital Signal Definition table 8 Changed HART PAFF Shunt Selection section 10 Changed Internal Mode Shunt Sele...

Page 23: ...y set forth above or credit User s account for such EVM TI s liability under this warranty shall be limited to EVMs that are returned during the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty If TI elects to repair or replace such EVM TI shall have a reasonable time to repair such EVM or provide replacements Repaired EVMs shall be warr...

Page 24: ...the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated Antenna types not included in this list having a gain greater than the maximum gain indicated for that type are strictly prohibited for use with this device Concernant les EVMs avec antennes détachables Conformément à la réglementation d Industrie Canada le présent émetteur radio peut fo...

Page 25: ...ed loads Any loads applied outside of the specified output range may also result in unintended and or inaccurate operation and or possible permanent damage to the EVM and or interface electronics Please consult the EVM user guide prior to connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation even ...

Page 26: ...COST OF REMOVAL OR REINSTALLATION ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES RETESTING OUTSIDE COMPUTER TIME LABOR COSTS LOSS OF GOODWILL LOSS OF PROFITS LOSS OF SAVINGS LOSS OF USE LOSS OF DATA OR BUSINESS INTERRUPTION NO CLAIM SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN TWELVE 12 MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS OCCURRED 8 2 Specif...

Page 27: ... TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN including but not limited to any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI product...

Page 28: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments DAC8742HEVM ...

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