Texas Instruments CC2500, Manual

Page: 45 / 96

CC2500
SWRS040C Page 45 of 89
be set to the centre of the lowest channel
frequency that is to be used.
The desired channel number is programmed
with
the 8-bit channel number register,
CHANNR.CHAN
, which is multiplied by the
channel offset. The resultant carrier frequency
is given by:
 
   
2 _
16
2 _ 256
2
      
E CHANSPC
XOSC
carrier
M CHANSPC CHAN FREQ
f
f
With a 26 MHz crystal the maximum channel
spacing is 405 kHz. To get e.g. 1 MHz channel
spacing one solution is to use 333 kHz
channel spacing and select each third channel
in
CHANNR.CHAN
.
The preferred IF frequency is programmed
with the
FSCTRL1.FREQ_IF
register. The IF
frequency is given by:
IF FREQ
f
f
XOSC
IF
_
2
10
 
Note that the SmartRF
®
Studio software [5]
automatically calculates the optimum
FSCTRL1.FREQ_IF
register setting based on
channel spacing and channel filter bandwidth.
If any frequency programming register is
altered when the frequency synthesizer is
running,
the synthesizer may give an
undesired response. Hence, the frequency
programming should only be updated when
the radio is in the IDLE state.
22 VCO
The VCO is completely integrated on-chip.
22.1 VCO and PLL Self-Calibration
The VCO characteristics will vary with
temperature and supply voltage changes, as
well as the desired operating frequency. In
order to ensure reliable operation,
CC2500
includes frequency synthesizer self-calibration
circuitry. This calibration should be done
regularly, and must be performed after turning
on power and before using a new frequency
(or channel). The number of XOSC cycles for
completing the PLL calibration is given in
Table 28 on page 42.
The calibration can be initiated automatically
or
manually. The synthesizer can be
automatically calibrated each time the
synthesizer is turned on, or each time the
synthesizer is turned off automatically. This is
configured
with the
MCSM0.FS_AUTOCAL
register setting. In manual mode, the
calibration is initiated when the
SCAL
command strobe is activated in the IDLE
mode.
Note that the calibration values are maintained
in SLEEP mode, so the calibration is still valid
after waking up from SLEEP mode (unless
supply voltage or temperature has changed
significantly).
To check that the PLL is in lock the user can
program register
IOCFGx.GDOx_CFG
to 0x0A
and use the lock detector output available on
the
GDOx
pin as an interrupt for the MCU (x =
0,1 or 2). A positive transition on the
GDOx
pin
means that the PLL is in lock. As an alternative
the user can read register
FSCAL1
. The PLL is
in lock if the register content is different from
0x3F. Refer also to the
CC2500
Errata Notes
[1]. For more robust operation the source code
could include a check so that the PLL is re-
calibrated until PLL lock is achieved if the PLL
does not lock the first time.