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CC2500
SWRS040C
Page 61 of 89
32.1
Configuration Register Details – Registers with Preserved Values in SLEEP State
0x00: IOCFG2 –
GDO2
Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
7
Reserved
R0
6
GDO2_INV
0
R/W
Invert output, i.e. select active low (1) / high (0)
5:0
GDO2_CFG[5:0]
41 (0x29)
R/W
Default is CHIP_RDYn (see Table 33 on page 53).
0x01: IOCFG1 –
GDO1
Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
7
GDO_DS
0
R/W
Set high (1) or low (0) output drive strength on the
GDO pins.
6
GDO1_INV
0
R/W
Invert output, i.e. select active low (1) / high (0)
5:0
GDO1_CFG[5:0]
46 (0x2E)
R/W
Default is 3-state (see Table 33 on page 53)
0x02: IOCFG0 –
GDO0
Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
7
TEMP_SENSOR_ENABLE
0
R/W
Enable analog temperature sensor. Write 0 in all other
register bits when using temperature sensor.
6
GDO0_INV
0
R/W
Invert output, i.e. select active low (1) / high (0)
5:0
GDO0_CFG[5:0]
63 (0x3F)
R/W
Summary of Contents for CC2500
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