![Texas Instruments Boomer LM49360 User Manual Download Page 60](http://html1.mh-extra.com/html/texas-instruments/boomer-lm49360/boomer-lm49360_user-manual_1094195060.webp)
General Type LDOS
The general “PERFECT” LDOs are optimized for supplying both analog and digital loads having ULTRA LOW NOISE (10µV
RMS
for I
OUT
>5mA) and excellent PSRR (75dB at 10kHz) performance. They can be programmed through the serial interface for different
output voltage values.
For fast discharging of output capacitors in shut down, the LDOs can connect a 300
Ω
pull-down resistor to the output. This resistor
is only connected when the LDO is disabled. See
In sleep mode, quiescent current is reduced to 30µA for energy saving. In this mode these LDOs should not be loaded with more
than 3-5mA of output current.
HILO LDO
LDO7 (HILO) has lowered output voltage range from 0.8V to 1.55V (step 50mV) controlled by 4 bit control signal as shown in LDO7
(HILO) output voltage selection table below. Typical output current is 2mA but maximum current can reach 20mA. For proper
operation, an input voltage of more than 2V is necessary. Hence, voltage drop on the pass transistor (dropout voltage) always
exceeds 0.45V and is not dependent on output current (in specified current range).
For fast discharging of output capacitors in shut down, the LDO7 (HILO) can connect a 300
Ω
pull-down resistor to the output. This
resistor is only connected when the LDO is disabled. See
for the register description.
Since the LDO7 (HILO) is based on the micro power LDO, no extra output capacitor is needed. However, for better dynamic
performance it is recommended that a capacitor in the 100nF to 1
μ
F range be used.
µPWR LDO
This LDO is primarily used for internal supply purposes and fixed to 1.8V, but may deliver up to 30mA of current also externally.
This LDO is ON even in Standby mode (with total PMU current consumption about 2uA) and the user may use it to supply some
backup/always on system(s).
TABLE 17. LDO1 — 6
Bank 0: CONFIG = Z (0x14h:LDO1)
→
(0x19h:LDO6)
Bank 1: CONFIG = H (0x24h:LDO1)
→
(0x29h:LDO6)
Bank 2: CONFIG = L (0x34h:LDO1)
→
(0x39h:LDO6)
Bits
Field
Description
4:0
LDO(1-6)*_VSEL
This sets the output voltage of the corresponding LDO.
LDO*_VSEL
Vout (V)
LDO*_VSEL
Vout (V)
00000
1.2
10000
2.1
00001
1.25
10001
2.2
00010
1.3
10010
2.3
00011
1.35
10011
2.4
00100
1.4
10100
2.5
00101
1.45
10101
2.6
00110
1.5
10110
2.65
00111
1.55
10111
2.7
01000
1.6
11000
2.75
01001
1.65
11001
2.8
01010
1.7
11010
2.85
01011
1.75
11011
2.9
01100
1.8
11100
2.95
01101
1.85
11101
3
01110
1.9
11110
3.1
01111
2
11111
3.3
59
www.ti.com
LM49360
Summary of Contents for Boomer LM49360
Page 3: ...5 0 LM49360 Overview 301282h8 FIGURE 1 LM49360 Block Diagram www ti com 2 LM49360...
Page 4: ...6 0 Typical Application 30128211 FIGURE 2 Sub PMU System Diagram 3 www ti com LM49360...
Page 5: ...30128216 FIGURE 3 AP PMU System Diagram www ti com 4 LM49360...
Page 16: ...301282h9 FIGURE 4 PMU State Machine 15 www ti com LM49360...
Page 68: ...30128213 FIGURE 20 Internal Clock Network 67 www ti com LM49360...
Page 128: ...40 0 Schematic Diagram 30128220 FIGURE 36 Demo Board Schematic 127 www ti com LM49360...
Page 129: ...30128245 FIGURE 37 Demo Board Schematic www ti com 128 LM49360...
Page 131: ...30128238 FIGURE 40 Inner Layer 2 30128239 FIGURE 41 Inner Layer 3 www ti com 130 LM49360...
Page 132: ...30128240 FIGURE 42 Inner Layer 4 30128241 FIGURE 43 Inner Layer 5 131 www ti com LM49360...
Page 133: ...30128231 FIGURE 44 Bottom Layer 30128242 FIGURE 45 Bottom Silkscreen www ti com 132 LM49360...
Page 136: ...Notes 135 www ti com LM49360...