Texas Instruments Boomer LM49360, User Manual

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Bits Field Description
5:3 BK2_DELAY This sets the time slot when Buck2 enables and disables.
000 Power up in slot 0, Power down in slot 0
001 Power up in slot 1, Power down in slot 1
010 Power up in slot 2, Power down in slot 2
011 Power up in slot 3, Power down in slot 3
100 Power up in slot 4, Power down in slot 4
101 Power up in slot 5, Power down in slot 5
110 Power up in slot 6, Power down in slot 6
111 Power up in slot 7, Power down in slot 7
6 LDO7_ENABLE If set, LDO 7 is enabled and disabled at time slot LDO7_DLY.
7 BK2_OVR If set, BUCK2 will enable when the OVR pin is asserted.
TABLE 15. BK1V
Bank 0: CONFIG = Z (0x12h)
Bank 1: CONFIG = H (0x22h)
Bank 2: CONFIG = L (0x32h)
Bits Field Description
7:0 BK1_VSEL
Sets the Buck 1 output voltage.
Vout(V) = 0.6 + (BK1_VSEL*0.00588)
TABLE 16. BK2V
Bank 0: CONFIG = Z (0x13h)
Bank 1: CONFIG = H (0x23h)
Bank 2: CONFIG = L (0x33h)
Bits Field Description
7:0 BK2_VSEL
Sets the Buck 2 output voltage.
Vout(V) = 0.6 + (BK2_VSEL*0.00588)
LDO INFORMATION
There are 8 LDOs in LM49360 grouped as:
6 General type “PERFECT” LDOs
1 HILO LDO
1 µPWR LDO
All LDOs can be programmed through serial interface for different output voltage values, which are summarized in the LDO output
voltage selection register tables.
For stability all LDOs need to have an external capacitor Cout connected to the output with the recommended value of 1
μ
F. It is
important that the capacitance is within the specified value across voltage and temperature.
PMU Enabled
The PMU allows four major methods of enabling and disabling the PMU outputs.
The first method is to use the I 2 C registers ENB1 and ENB2. Then set the Timestep and Delay for the required power sequence.
The second method is via the OVR pin and the OVR register bits to enable any of the PMU outputs under hardware control. This
mode is available in AP_PMU, SUB-PMU and CAM modes.
The third method is via the SUBOVR pin and the SUBOVR register bits to enable any of the SUB-PMU outputs Buck 1, LDO1,
LDO4, LDO5 and LDO7 under hardware control. This mode is available in SUB-PMU and CAM modes. A subset of this mode is
that the SUBOVR pin can be used to enable Buck 2 without setting a SUBOVR register bit. This means that Buck 2 will always be
enabled when the SUBOVR pin is high.
The fourth method is software control via I 2 C access to the ENB2, SWOVR 1 and SWOVR 2 registers. This mode is available in
AP_PMU, SUB-PMU and CAM modes.
The PMU outputs are enabled on an “OR” condition of the 4 methods. If the enable bits in the I 2 C registers ENB1 and ENB2 are
cleared, one of the other three methods can be used to enable and disable the PMU outputs. If the Timestep and Delays are
programmed but the Enables (ENB1, ENB2) are cleared, then the initial enabling of the PMU output via hardware and software
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LM49360