20.0 Timing Characteristics: DV
DD
= I/OV
DD
= 1.8V
The following specifications
apply for R
L(SP)
= 8Ω
, R
L(HP)
= 32Ω
, f = 1kHz, unless otherwise specified. Limits apply for T
A
= 25°C.
Symbol
Parameter
Conditions
LM49360
Units
(Limit)
Typical
(
)
Limit
(
PLL
f
IN
PLL Input Frequency Range
Minimum MCLK Frequency
0.5
MHz (min)
Maximum MCLK Frequency
50
MHz (max)
I
2
S MASTER TIMING
I2S_CLK
PER
I2S_CLK Period
I
2
S Master
81.38
ns
tCLK_L
I2S_CLK Low Time
I
2
S Master
37
ns
tCLK_H
I2S_CLK High Time
I
2
S Master
37
ns
t
WS_DLY
WS Propagation Delay from I2S_CLK
falling edge
I
2
S Master
21
ns
t
SDO_DLY
SDO Propagation Delay from I2S_CLK
falling edge
I
2
S Master
21
ns
t
DST
SDI Setup Time to I2S_CLK Rising
Edge
I
2
S Master
20
ns
t
DHT
SDI Hold Time to I2S_CLK Rising
Edge
I
2
S Master
20
ns
I
2
S SLAVE TIMING
I2S_CLK
PER
I2S_CLK Period
I
2
S Slave
81.38
ns (min)
tCLK_L
I2S_CLK Low Time
I
2
S Slave
37
ns (min)
tCLK_H
I2S_CLK High Time
I
2
S Slave
37
ns (min)
t
SDO_DLY
SDO Propagation Delay from I2S_CLK
falling edge
I
2
S Slave
21
ns
t
DST
SDI Setup Time to I2S_CLK Rising
Edge
I
2
S Slave
20
ns (min)
t
DHT
SDI Hold Time to I2S_CLK Rising
Edge
I
2
S Slave
20
ns (min)
t
WS_ST
WS Setup Time to I2S_CLK Rising
Edge
I
2
S Slave
20
ns (min)
t
WS_HT
WS Hold Time to I2S_CLK Rising
Edge
I
2
S Slave
20
ns (min)
CONTROL INTERFACE TIMING
SCL Frequency
400
kHz (max)
1
Hold Time (repeated START
Condition)
0.6
μ
s (min)
2
Clock Low Time
1.3
μ
s (min)
3
Clock High Time
600
ns (min)
4
Setup Time for a Repeated START
Condition
600
ns (min)
5
Data Hold Time
Output
(LM49360 generated)
50
ns (min)
Input
(Master generated)
50
ns (min)
6
Data Setup Time
100
ns (min)
7
Rise Time of SDA and SCL
300
ns (max)
8
Fall Time SDA and SCL
300
ns (max)
9
Setup Time for STOP Condition
600
ns (min)
27
www.ti.com
LM49360
Summary of Contents for Boomer LM49360
Page 3: ...5 0 LM49360 Overview 301282h8 FIGURE 1 LM49360 Block Diagram www ti com 2 LM49360...
Page 4: ...6 0 Typical Application 30128211 FIGURE 2 Sub PMU System Diagram 3 www ti com LM49360...
Page 5: ...30128216 FIGURE 3 AP PMU System Diagram www ti com 4 LM49360...
Page 16: ...301282h9 FIGURE 4 PMU State Machine 15 www ti com LM49360...
Page 68: ...30128213 FIGURE 20 Internal Clock Network 67 www ti com LM49360...
Page 128: ...40 0 Schematic Diagram 30128220 FIGURE 36 Demo Board Schematic 127 www ti com LM49360...
Page 129: ...30128245 FIGURE 37 Demo Board Schematic www ti com 128 LM49360...
Page 131: ...30128238 FIGURE 40 Inner Layer 2 30128239 FIGURE 41 Inner Layer 3 www ti com 130 LM49360...
Page 132: ...30128240 FIGURE 42 Inner Layer 4 30128241 FIGURE 43 Inner Layer 5 131 www ti com LM49360...
Page 133: ...30128231 FIGURE 44 Bottom Layer 30128242 FIGURE 45 Bottom Silkscreen www ti com 132 LM49360...
Page 136: ...Notes 135 www ti com LM49360...
