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MPU Registers

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5.3.14 Fault Status Register (FLTSTAT)

The fault status register (FLTSTAT) holds the status and attributes of the first protection fault transfer. The
FLTSTAT is shown in

Figure 5-18

and described in

Table 5-21

Figure 5-18. Fault Status Register (FLTSTAT)

Reserved

MSTID

R-0

Reserved

PRIVID

Reserved

TYPE

R-0

LEGEND: R = Read only; -n = value after reset

Table 5-21. Fault Status Register (FLTSTAT) Field Descriptions

Bit

Field

Value

Description

31-24

Reserved

23-16

MSTID

0-FFh

Master ID of fault transfer.

15-13

Reserved

12-9

PRIVID

0-Fh

Privilege ID of fault transfer.

8-6

Reserved

5-0

TYPE

0-3Fh

Fault type. The TYPE bit field is cleared when a 1 is written to the CLEAR bit in the fault clear
register (FLTCLR).

No fault.

User execute fault.

User write fault.

Reserved

User read fault.

5h-7h

Reserved

Supervisor execute fault.

9h-Fh

Reserved

10h

Supervisor write fault.

11h

Reserved

12h

Relaxed cache write back fault.

13h-1Fh

Reserved

20h

Supervisor read fault.

21h-3Eh

Reserved

3Fh

Relaxed cache line fill fault.

Memory Protection Unit (MPU)

SPRUGX5A

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May 2011

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Summary of Contents for AM1802

Page 1: ...AM1802 ARM Microprocessor System Reference Guide Literature Number SPRUGX5A May 2011 ...

Page 3: ...ction 36 4 2 ARM Memories 36 4 3 On Chip RAM Memory 36 4 4 External Memories 36 4 5 Internal Peripherals 36 4 6 Peripherals 36 5 Memory Protection Unit MPU 37 5 1 Introduction 38 5 1 1 Purpose of the MPU 38 5 1 2 Features 38 5 1 3 Block Diagram 38 5 1 4 MPU Default Configuration 39 5 2 Architecture 39 5 2 1 Privilege Levels 39 5 2 2 Memory Protection Ranges 40 5 2 3 Permission Structures 40 5 2 4 ...

Page 4: ...on 72 7 2 PLL Controllers 72 7 2 1 Device Clock Generation 74 7 2 2 Steps for Programming the PLLs 75 7 3 PLLC Registers 77 7 3 1 PLLC0 Revision Identification Register REVID 78 7 3 2 PLLC1 Revision Identification Register REVID 79 7 3 3 Reset Type Status Register RSTYPE 79 7 3 4 PLLC0 Reset Control Register RSCTRL 80 7 3 5 PLLC0 Control Register PLLCTL 81 7 3 6 PLLC1 Control Register PLLCTL 82 7 ...

Page 5: ...upt Handling 113 8 6 PSC Registers 114 8 6 1 Revision Identification Register REVID 115 8 6 2 Interrupt Evaluation Register INTEVAL 115 8 6 3 PSC0 Module Error Pending Register 0 modules 0 15 MERRPR0 116 8 6 4 PSC1 Module Error Pending Register 0 modules 0 31 MERRPR0 116 8 6 5 PSC0 Module Error Clear Register 0 modules 0 15 MERRCR0 117 8 6 6 PSC1 Module Error Clear Register 0 modules 0 31 MERRCR0 ...

Page 6: ... 3 Master Priority Control 147 10 4 SYSCFG Registers 148 10 4 1 Revision Identification Register REVID 150 10 4 2 Device Identification Register 0 DEVIDR0 150 10 4 3 Boot Configuration Register BOOTCFG 151 10 4 4 Kick Registers KICK0R KICK1R 152 10 4 5 Host 0 Configuration Register HOST0CFG 153 10 4 6 Interrupt Registers 154 10 4 7 Fault Registers 157 10 4 8 Master Priority Registers MSTPRI0 MSTPR...

Page 7: ... Status Raw Set Register 2 SRSR2 235 11 4 18 System Interrupt Status Raw Set Register 3 SRSR3 235 11 4 19 System Interrupt Status Raw Set Register 4 SRSR4 236 11 4 20 System Interrupt Status Enabled Clear Register 1 SECR1 236 11 4 21 System Interrupt Status Enabled Clear Register 2 SECR2 237 11 4 22 System Interrupt Status Enabled Clear Register 3 SECR3 237 11 4 23 System Interrupt Status Enabled ...

Page 9: ...ault Status Register FLTSTAT 56 5 19 Fault Clear Register FLTCLR 57 6 1 Overall Clocking Diagram 61 6 2 USB Clocking Diagram 63 6 3 DDR2 mDDR Memory Controller Clocking Diagram 65 6 4 EMIFA Clocking Diagram 66 6 5 EMAC Clocking Diagram 67 6 6 McASP Clocking Diagram 68 7 1 PLLC Structure 73 7 2 PLLC0 Revision Identification Register REVID 78 7 3 PLLC1 Revision Identification Register REVID 79 7 4 R...

Page 10: ...er 0 MERRCR0 117 8 6 PSC1 Module Error Clear Register 0 MERRCR0 117 8 7 Power Error Pending Register PERRPR 118 8 8 Power Error Clear Register PERRCR 118 8 9 Power Domain Transition Command Register PTCMD 119 8 10 Power Domain Transition Status Register PTSTAT 120 8 11 Power Domain 0 Status Register PDSTAT0 121 8 12 Power Domain 1 Status Register PDSTAT1 122 8 13 Power Domain 0 Control Register PD...

Page 11: ...xing Control 17 Register PINMUX17 195 10 35 Pin Multiplexing Control 18 Register PINMUX18 197 10 36 Pin Multiplexing Control 19 Register PINMUX19 199 10 37 Suspend Source Register SUSPSRC 201 10 38 Chip Signal Register CHIPSIG 203 10 39 Chip Signal Clear Register CHIPSIG_CLR 204 10 40 Chip Configuration 0 Register CFGCHIP0 205 10 41 Chip Configuration 1 Register CFGCHIP1 206 10 42 Chip Configurati...

Page 12: ...gister 4 SECR4 238 11 26 System Interrupt Enable Set Register 1 ESR1 238 11 27 System Interrupt Enable Set Register 2 ESR2 239 11 28 System Interrupt Enable Set Register 3 ESR3 239 11 29 System Interrupt Enable Set Register 4 ESR4 240 11 30 System Interrupt Enable Clear Register 1 ECR1 240 11 31 System Interrupt Enable Clear Register 2 ECR2 241 11 32 System Interrupt Enable Clear Register 3 ECR3 2...

Page 13: ...s 53 5 19 Programmable Range Memory Protection Page Attributes Register PROGn_MPPA Field Descriptions 54 5 20 Fault Address Register FLTADDRR Field Descriptions 55 5 21 Fault Status Register FLTSTAT Field Descriptions 56 5 22 Fault Clear Register FLTCLR Field Descriptions 57 6 1 Device Clock Inputs 60 6 2 System Clock Domains 60 6 3 Example PLL Frequencies 63 6 4 USB Clock Multiplexing Options 63 ...

Page 14: ...ons 101 7 38 PLLC1 SYSCLK Status Register SYSTAT Field Descriptions 102 7 39 Emulation Performance Counter 0 Register EMUCNT0 Field Descriptions 103 7 40 Emulation Performance Counter 1 Register EMUCNT1 Field Descriptions 103 8 1 PSC0 Default Module Configuration 106 8 2 PSC1 Default Module Configuration 107 8 3 Module States 109 8 4 IcePick Emulation Commands 111 8 5 PSC Interrupt Events 111 8 6 ...

Page 15: ...escriptions 168 10 25 Pin Multiplexing Control 4 Register PINMUX4 Field Descriptions 170 10 26 Pin Multiplexing Control 5 Register PINMUX5 Field Descriptions 172 10 27 Pin Multiplexing Control 6 Register PINMUX6 Field Descriptions 174 10 28 Pin Multiplexing Control 7 Register PINMUX7 Field Descriptions 176 10 29 Pin Multiplexing Control 8 Register PINMUX8 Field Descriptions 178 10 30 Pin Multiplex...

Page 16: ...eld Descriptions 234 11 19 System Interrupt Status Raw Set Register 2 SRSR2 Field Descriptions 235 11 20 System Interrupt Status Raw Set Register 3 SRSR3 Field Descriptions 235 11 21 System Interrupt Status Raw Set Register 4 SRSR4 Field Descriptions 236 11 22 System Interrupt Status Enabled Clear Register 1 SECR1 Field Descriptions 236 11 23 System Interrupt Status Enabled Clear Register 2 SECR2 ...

Page 19: ...elds of the register Each field is labeled with its bit name its beginning and ending bit numbers above and its read write properties below A legend explains the notation used for the properties Reserved bits in a register figure designate a bit that is used for future device expansion Related Documentation From Texas Instruments The following documents describe the AM18x ARM Microprocessors Copie...

Page 21: ... 1 SPRUGX5A May 2011 Overview Topic Page 1 1 Introduction 22 1 2 Block Diagram 22 1 3 ARM Subsystem 22 21 SPRUGX5A May 2011 Overview Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 22: ...control The AM1802 ARM microprocessor consists of the following primary components ARM926 RISC CPU core and associated memories A set of I O peripherals A powerful DMA subsystem and SDRAM EMIF interface 1 2 Block Diagram A block diagram for the AM1802 ARM microprocessor is shown in Figure 1 1 1 3 ARM Subsystem The ARM926EJ 32 bit RISC CPU in the ARM subsystem ARMSS acts as the overall system contr...

Page 23: ...ates Modes 25 2 3 Processor Status Registers 25 2 4 Exceptions and Exception Vectors 26 2 5 The 16 BIS 32 BIS Concept 27 2 6 16 BIS 32 BIS Advantages 27 2 7 Co Processor 15 CP15 28 23 SPRUGX5A May 2011 ARM Subsystem Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 24: ... for efficient execution of Java byte codes and providing Java performance similar to Just in Time JIT Java interpreter without associated code overhead The ARM926EJ S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debugging The ARM926EJ S processor has a Harvard architecture and provides a complete high performance subsystem including the ...

Page 25: ...ter SP automatically changes to the SP of the mode that was entered 2 3 Processor Status Registers The processor status register PSR controls the enabling and disabling of interrupts and setting the mode of operation of the processor The 8 least significant bits PSR 7 0 are the control bits of the processor PSR 27 8 are reserved bits and PSR 31 28 are status registers The details of the control bi...

Page 26: ... instruction have the same priority The ARM is configured with the VINTH signal set high VINTH 1 such that the vector table is located at address FFFF 0000h This address maps to the beginning of the ARM local RAM 8 KB NOTE The VINTH signal is configurable by way of the register setting in CP15 However it is not recommended to set VINTH 0 as the device has no physical memory in the 0000 0000h addre...

Page 27: ...instructions to perform the same task as a single 32 bit instruction However not all of the code in a program processes 32 bit data for example code that performs character string handling and some instructions like branches do not process any data at all If a 16 bit architecture only has 16 bit instructions and a 32 bit architecture only has 32 bit instructions then the 16 bit architecture has be...

Page 28: ...n the cache then the MMU translates the MVA to produce the PA NOTE See the Programmers Model of the ARM926EJ S Technical Reference Manual TRM downloadable from http infocenter arm com help index jsp for more detailed information 2 7 2 Memory Management Unit The ARM926EJ S MMU provides virtual memory features required by operating systems such as SymbianOS WindowsCE and Linux A single set of two le...

Page 29: ... possibility of TLB misses related to the write back address Cache maintenance operations to provide efficient invalidation of the following The entire Dcache or Icache Regions of the Dcache or Icache The entire Dcache Regions of virtual memory They also provide operations for efficient cleaning and invalidation of the following The entire Dcache Regions of the Dcache Regions of virtual memory The...

Page 31: ...A May 2011 System Interconnect Topic Page 3 1 Introduction 32 3 2 System Interconnect Block Diagram 33 31 SPRUGX5A May 2011 System Interconnect Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 32: ...and write transfers in the system and do not rely on the EDMA3 or on a CPU to perform transfers to and from them The system master peripherals include the ARM the EDMA3 transfer controllers EMAC and USB2 0 Not all master peripherals may connect to all slave peripherals The supported connections are designated by an X in Table 3 1 Table 3 1 AM1802 ARM Microprocessor System Interconnect Matrix Maste...

Page 33: ...ync 1 Clock Domain EMIFA ARM ROM ARM RAM SCR4 MMC SD0 SPI0 UART0 EDMA3_0_TC0 EDMA3_0_TC1 SCR F5 EDMA3_0_CC1 EDMA3_1_CC0 USB0 Cfg EDMA3_0_CC1 BR F3 SCR F6 SYSCFG1 EMAC EMAC MDIO GPIO PSC1 PLLC1 Clock Domain SYSCLK4 CPU 4 Synchronous BR F4 BR F5 SCR F7 UART1 UART2 McASP0 SCR F8 Timer64P2 Timer64P3 SPI1 Async 3 PLL1 Clock Domain Clock Domain SYSCLK4 CPU 4 Synchronous Clock Domain SYSCLK4 CPU 4 Synchr...

Page 35: ...ge 4 1 Introduction 36 4 2 ARM Memories 36 4 3 On Chip RAM Memory 36 4 4 External Memories 36 4 5 Internal Peripherals 36 4 6 Peripherals 36 35 SPRUGX5A May 2011 System Memory Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 36: ...ter peripherals 4 4 External Memories This device has two external memory interfaces that provide multiple external memory options accessible by the CPU and master peripherals EMIFA 8 16 bit wide asynchronous EMIF module that supports asynchronous devices such as ASRAM NAND Flash and NOR Flash up to 4 devices 8 16 bit wide NAND Flash with 4 bit ECC up to 4 devices 16 bit SDRAM with 128 MB address ...

Page 37: ...011 Memory Protection Unit MPU Topic Page 5 1 Introduction 38 5 2 Architecture 39 5 3 MPU Registers 44 37 SPRUGX5A May 2011 Memory Protection Unit MPU Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 38: ...th ranges Generates an interrupt when there is a protection violation and saves violating transfer parameters Supports protection of its own registers 5 1 3 Block Diagram Figure 5 1shows a block diagram of the MPU An access to a protected memory must pass through the MPU During an access the MPU checks the memory address on the input data bus against fixed and programmable ranges If allowed the tr...

Page 39: ...inator of the memory access might have Two privilege levels are supported supervisor and user Supervisor level is generally granted access to peripheral registers and the memory protection configuration User level is generally confined to the memory spaces that the OS specifically designates for its use ARM CPU instruction and data accesses have a privilege level associated with them See the ARM92...

Page 40: ...re to program the start and end addresses Each address range has the following set of registers Range start and end address registers MPSAR and MPEAR Specifies the starting and ending address of the address range Memory protection page attribute register MPPA Use to program the permission settings of the address range It is allowed to configure ranges such that they overlap each other In this case...

Page 41: ...ing requestor 5 2 3 2 Request Type Based Permissions The memory protection model defines three fundamental functional access types read write and execute Read and write refer to data accesses accesses originating via the load store units on the CPU or via a master peripheral Execute refers to accesses associated with an instruction fetch The memory protection model allows controlling read write an...

Page 42: ...ss to the range start and end address registers MPSAR and MPEAR and memory protection page attribute registers MPPA is also protected All non debug writes must be by a supervisor entity A protection fault can occur from a register write with invalid permissions and this triggers an interrupt just like a memory access Faults are not recorded nor interrupts generated for debug accesses 5 2 6 Invalid...

Page 43: ...both MPUs are combined with the boot configuration module into a single interrupt called MPU_BOOTCFG_ERR The combined interrupt is routed to the ARM interrupt controller Table 5 5 shows the interrupt sources that are combined to make MPU_BOOTCFG_ERR Table 5 5 MPU_BOOTCFG_ERR Interrupt Sources Interrupt Source MPU1_ADDR_ERR_INT MPU1 address error interrupt MPU1_PROT_ERR_INT MPU1 protection interrup...

Page 44: ...0 1 01E1 4234h PROG4_MPEAR Programmable range 4 end address register Section 5 3 11 1 01E1 4238h PROG4_MPPA Programmable range 4 memory protection page attributes register Section 5 3 12 01E1 4240h PROG5_MPSAR Programmable range 5 start address register Section 5 3 10 1 01E1 4244h PROG5_MPEAR Programmable range 5 end address register Section 5 3 11 1 01E1 4248h PROG5_MPPA Programmable range 5 memo...

Page 45: ...able range 7 start address register Section 5 3 10 2 01E1 5274h PROG7_MPEAR Programmable range 7 end address register Section 5 3 11 2 01E1 5268h PROG7_MPPA Programmable range 7 memory protection page attributes register Section 5 3 12 01E1 5270h PROG8_MPSAR Programmable range 8 start address register Section 5 3 10 2 01E1 5274h PROG8_MPEAR Programmable range 8 end address register Section 5 3 11 ...

Page 46: ...e for a list of AIDs supported on your device Figure 5 4 Configuration Register CONFIG 31 24 23 20 19 16 ADDR_WIDTH NUM_FIXED NUM_PROG R 0 1 or 6h 2 R 0 1 or 1 2 R 6h 1 or Ch 2 15 12 11 1 0 NUM_AIDS Reserved ASSUME_ALLOWED R Ch R 0 R 1 LEGEND R Read only n value after reset 1 For MPU1 2 For MPU2 Table 5 9 Configuration Register CONFIG Field Descriptions Bit Field Value Description 31 24 ADDR_WIDTH...

Page 47: ... 2 1 0 ADDRERR PROTERR R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 5 10 Interrupt Raw Status Set Register IRAWSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 ADDRERR Address violation error Reading this bit reflects the status of the interrupt Writing 1 sets the status writing 0 has no effect 0 Interrupt is not set 1 Interrupt is set 0...

Page 48: ...e R Read only n value after reset Table 5 11 Interrupt Enable Status Clear Register IENSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 ADDRERR Address violation error If the interrupt is enabled reading this bit reflects the status of the interrupt If the interrupt is disabled reading this bit returns 0 Writing 1 sets the status writing 0 has no effect 0 Interrupt is...

Page 49: ...fect 1 Interrupt is enabled 5 3 6 Interrupt Enable Clear Register IENCLR Reading the interrupt enable clear register IENCLR returns the interrupts that are enabled Software can write to IENCLR to clear disable an interrupt Writes of 0 have no effect The IENCLR is shown in Figure 5 8 and described in Table 5 13 Figure 5 8 Interrupt Enable Clear Register IENCLR 31 16 Reserved R 0 15 2 1 0 Reserved A...

Page 50: ...0 Reserved R 0 LEGEND R Read only n value after reset 5 3 8 Fixed Range End Address Register FXD_MPEAR The fixed range end address register FXD_MPEAR holds the end address for the fixed range The fixed address range manages access to the DDR2 mDDR SDRAM control registers B000 0000h B000 7FFFh However these addresses are not indicated in FXD_MPEAR and the fixed range start address register FXD_MPSA...

Page 51: ...le 5 14 Fixed Range Memory Protection Page Attributes Register FXD_MPPA Field Descriptions Bit Field Value Description 31 26 Reserved 0 Reserved 25 22 Reserved Fh Reserved 21 10 AIDn Controls access from ID n 0 Access is denied 1 Access is granted 9 AIDX Controls access from ID 11 0 Access is denied 1 Access is granted 8 Reserved 0 Reserved 7 Reserved 1 Reserved This bit must be written as 1 6 Res...

Page 52: ...e starting at byte address 8001 0000h write 8001 0000h to PROGn_MPSAR and 8001 FFFFh to PROGn_MPEAR 5 3 10 1 MPU1 Programmable Range n Start Address Register PROG1_MPSAR PROG6_MPSAR The PROGn_MPSAR for MPU1 is shown in Figure 5 12 and described in Table 5 15 Figure 5 12 MPU1 Programmable Range n Start Address Register PROGn_MPSAR 31 10 9 0 START_ADDR Reserved R W 20 0000h R 0 LEGEND R W Read Write...

Page 53: ... 17 Figure 5 14 MPU1 Programmable Range n End Address Register PROGn_MPEAR 31 10 9 0 END_ADDR Reserved R W 20 007Fh R 3FFh LEGEND R W Read Write R Read only n value after reset Table 5 17 MPU1 Programmable Range n End Address Register PROGn_MPEAR Field Descriptions Bit Field Value Description 31 10 END_ADDR 20 0000h End address for range N 20 007Fh 9 0 Reserved 3FFh Reserved 5 3 11 2 MPU2 Programm...

Page 54: ... reset Table 5 19 Programmable Range Memory Protection Page Attributes Register PROGn_MPPA Field Descriptions Bit Field Value Description 31 26 Reserved 0 Reserved 25 22 Reserved Fh Reserved 21 10 AIDn Controls access from ID n 0 Access is denied 1 Access is granted 9 AIDX Controls access from ID 11 0 Access is denied 1 Access is granted 8 Reserved 0 Reserved 7 Reserved 1 Reserved This bit must be...

Page 55: ...7 and described in Table 5 20 Figure 5 17 Fault Address Register FLTADDRR 31 0 FLTADDR R 0 LEGEND R Read only n value after reset Table 5 20 Fault Address Register FLTADDRR Field Descriptions Bit Field Value Description 31 0 FLTADDR 0 FFFF FFFFh Memory address of fault 55 SPRUGX5A May 2011 Memory Protection Unit MPU Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 56: ...0 Reserved 23 16 MSTID 0 FFh Master ID of fault transfer 15 13 Reserved 0 Reserved 12 9 PRIVID 0 Fh Privilege ID of fault transfer 8 6 Reserved 0 Reserved 5 0 TYPE 0 3Fh Fault type The TYPE bit field is cleared when a 1 is written to the CLEAR bit in the fault clear register FLTCLR 0 No fault 1h User execute fault 2h User write fault 3h Reserved 4h User read fault 5h 7h Reserved 8h Supervisor exec...

Page 57: ...is shown in Figure 5 19 and described in Table 5 22 Figure 5 19 Fault Clear Register FLTCLR 31 16 Reserved R 0 15 1 0 Reserved CLEAR R 0 W 0 LEGEND R Read only W Write only n value after reset Table 5 22 Fault Clear Register FLTCLR Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 CLEAR Command to clear the current fault Writing 0 has no effect 0 No effect 1 Clear the curre...

Page 59: ...May 2011 Device Clocking Topic Page 6 1 Overview 60 6 2 Frequency Flexibility 62 6 3 Peripheral Clocking 63 59 SPRUGX5A May 2011 Device Clocking Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 60: ...hows the clocking architecture Table 6 1 Device Clock Inputs Peripheral Input Clock Signal Name Oscillator PLL OSCIN RTC RTC_XI JTAG TCK RTCK EMAC RMII RMII_MHZ_50_CLK EMAC MII MII_TXCLK MII_RXCLK USB2 0 USB_REFCLKIN I2C0 I2C0_SCL Timers TM64Pn_IN12 SPIs SPIn_CLK McASP0 ACLKR AHCLKR ACLKX AHCLKX Table 6 2 System Clock Domains Fixed Ratio to Default Ratio to CPU Device Peripherals System Clock Doma...

Page 61: ... AUXCLK SYSCLK2 2 CLKSRC DDR2 mDDR PLL1 Controller A B C D E 1 0 CFGCHIP3 EMA_CLKSRC 1 0 CFGCHIP3 ASYNC3_CLKSRC PLL Ref CLK www ti com Overview Figure 6 1 Overall Clocking Diagram A See Section 6 3 1 for USB clocking B See Section 6 3 2 for DDR2 mDDR clocking C See Section 6 3 3 for EMIFA clocking D See Section 6 3 4 for EMAC clocking E See Section 6 3 5 for McASP clocking 61 SPRUGX5A May 2011 Dev...

Page 62: ...utput of the PLL Multiplier must be within the range specified in the device specific data manual The output of each PLLDIV block must be less than or equal to the maximum device frequency specified in the device specific data manual NOTE The above limitations are provided here as an example and are used to illustrate the recommended configuration of the PLL controller These limitations may vary b...

Page 63: ...guration 2 register CFGCHIP2 of the System Configuration Module The USB_REFCLKIN source should be selected when it is not possible such as when specific audio rates are required to operate the device at one of the allowed input frequencies to the USB2 0 subsystem The USB2 0 subsystem peripheral bus clock is sourced from PLL0_SYSCLK2 Table 6 4 determines the source origination as well as the source...

Page 64: ...typical CPU frequency of 300 MHz the output of the PLL multiplier should be set to be 300 MHz and the DDR_CLK source should be set to PLL1_SYSCLK1 The frequency of the PLL1 direct output clock is fixed at the output frequency of the PLL1 multiplier block The PLLDIV1 block that sets the divider ratio for SYSCLK1 can be changed to achieve various clock frequencies For certain PLL1 multiplier and PLL...

Page 65: ...ier PLL1 PLL1 Post POSTDIV PLLDIV1 OSCIN Register Multiplier Divider Mode Output Register Frequency Setting Frequency 1 Frequency Setting PLL1_SYSCLK1 MCLK 24 18h 600 MHz Div2 300 MHz 8000h 300 MHz 150 MHz 24 15h 528 MHz Div2 264 MHz 8000h 264 MHz 132 MHz 24 14h 504 MHz Div2 252 MHz 8000h 252 MHz 126 MHz 1 See Section 6 2 for explanation of POSTDIV divider modes 65 SPRUGX5A May 2011 Device Clockin...

Page 66: ... PLLDIV3 register set to 3 The frequency of the DIV4P5 clock is fixed at the output frequency of the PLL multiplier block divided by 4 5 The PLLDIV3 block that sets the divider ratio for PLL0_SYSCLK3 can be changed to achieve various clock frequencies Figure 6 4 EMIFA Clocking Diagram Table 6 6 EMIFA Frequencies PLL Multiplier POSTDIV PLLDIV3 OSCIN Register Multiplier Post Divider Output Register ...

Page 67: ... pin or from PLL0_SYSCLK7 as shown in Figure 6 5 The PINMUX15_3_0 bits in the pin multiplexing control 15 register PINMUX15 of the System Configuration Module control this clock selection PINMUX15_3_0 0 enables sourcing of the 50 MHz reference clock from an external source on the RMII_MHZ_50_CLK pin PINMUX15_3_0 8h enables sourcing of the 50 MHz reference clock from PLL0_SYSCLK7 Also PLL0_SYSCLK7 ...

Page 68: ...e McASP peripheral requires multiple clock sources Internally the module clock is selected to be either PLL0_SYSCLK2 or PLL1_SYSCLK2 by configuring the ASYNC3_CLKSRC bit in the chip configuration 3 register CFGCHIP3 of the System Configuration Module The transmit and receive clocks are sourced internally or externally by configuring the McASP clock control registers ACLKRCTL AHCLKRCTL ACLKXCTL and...

Page 69: ...ey are fed the AUXCLK directly from the oscillator input Synchronous Peripherals Synchronous peripherals have their MMC SD0 PLL0_SYSCLK2 frequencies derived from the ARM UART0 PLL0_SYSCLK2 clock frequency The peripheral GPIO PLL0_SYSCLK4 system clock frequency changes accordingly if the PLL0 frequency changes Most synchronous peripherals have internal dividers so they can generate their required c...

Page 71: ... Locked Loop Controller PLLC Topic Page 7 1 Introduction 72 7 2 PLL Controllers 72 7 3 PLLC Registers 77 71 SPRUGX5A May 2011 Phase Locked Loop Controller PLLC Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 72: ... the PLL controller 1 PLLC1 registers Figure 7 1 shows the PLLC0 and PLLC1 architecture The PLL0 and PLL1 multipliers are controlled by their respective PLL multiplier control register PLLM The PLLM defaults to a multiplier value of 13h at power up which results in a PLL multiplier of 20 The PLL0 and PLL1 output clocks may be divided down for slower device operation using the PLL post divider cont...

Page 73: ...OSTDIV PLLM PLL 0 1 PLLCTL PLLEN PLLCTL CLKMODE POSTDIV PLLC0 OBSCLK CLKOUT Pin DIV4 5 OSCDIV PLL Controller 0 PLL Controller 1 SYSCLK2 SYSCLK3 SYSCLK1 OSCIN 14h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh SYSCLK1 SYSCLK2 SYSCLK3 SYSCLK4 SYSCLK5 SYSCLK6 SYSCLK7 PLLC1 OBSCLK OCSEL OCSRC 14h 17h 18h 19h SYSCLK1 SYSCLK2 SYSCLK3 OCSEL OCSRC OSCDIV PLLC1 OBSCLK DEEPSLEEP Enable www ti com PLL Controllers Figure 7 ...

Page 74: ...0_AUXCLK I2C0 Timer64P0 P1 RTC USB2 0 PHY PLL bypass clock No McASP0 serial clock PLL0_OBSCLK Observation clock OBSCLK source Pin configurable No PLLC1 PLL1_SYSCLK1 DDR2 mDDR PHY 1 or disabled No PLL1_SYSCLK2 3 UART1 2 Timer64P2 3 McASP0 SPI1 all 2 or disabled No these modules use PLL0_SYSCLK2 by default PLL1_SYSCLK3 4 PLL0 input reference clock 3 or disabled No not configured by default 1 The div...

Page 75: ...p if this PLL clock is unintentionally disabled The PLL lock bits are located within the system configuration SYSCFG module When set the PLL_MASTER_LOCK bit in the chip configuration 0 register CFGCHIP0 locks PLLC0 When set the PLL1_MASTER_LOCK bit in the chip configuration 3 register CFGCHIP3 locks PLLC1 Because the SYSCFG module has its own lock mechanism the SYSCFG module must be unlocked first...

Page 76: ...evice specific data manual for PLL lock time 9 Set the PLLEN bit in PLLCTL to 1 removes PLL from bypass mode 7 2 2 3 Changing PLL Multiplier If the PLL is not powered down PLLPWRDN bit in PLLCTL is cleared to 0 perform the following procedure to change the PLL multiplier 1 Switch the PLL to bypass mode a Clear the PLLENSRC bit in PLLCTL to 0 allows PLLEN bit to take effect b For PLL0 only select t...

Page 77: ... Section 7 3 10 01C1 1118h PLLDIV1 PLLC0 Divider 1 Register Section 7 3 11 01C1 111Ch PLLDIV2 PLLC0 Divider 2 Register Section 7 3 13 01C1 1120h PLLDIV3 PLLC0 Divider 3 Register Section 7 3 15 01C1 1124h OSCDIV PLLC0 Oscillator Divider 1 Register Section 7 3 21 01C1 1128h POSTDIV PLLC0 PLL Post Divider Control Register Section 7 3 23 01C1 1138h PLLCMD PLLC0 PLL Controller Command Register Section ...

Page 78: ...h ALNCTL PLLC1 Clock Align Control Register Section 7 3 27 01E1 A144h DCHANGE PLLC1 PLLDIV Ratio Change Status Register Section 7 3 29 01E1 A148h CKEN PLLC1 Clock Enable Control Register Section 7 3 31 01E1 A14Ch CKSTAT PLLC1 Clock Status Register Section 7 3 33 01E1 A150h SYSTAT PLLC1 SYSCLK Status Register Section 7 3 35 01E1 A1F0h EMUCNT0 PLLC1 Emulation Performance Counter 0 Register Section 7...

Page 79: ...d deasserted simultaneously RSTYPE latches the highest priority reset source RSTYPE is shown in Figure 7 4 and described in Table 7 6 Figure 7 4 Reset Type Status Register RSTYPE 31 16 Reserved R 0 15 3 2 1 0 Reserved PLLSWRST XWRST POR R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 7 6 Reset Type Status Register RSTYPE Field Descriptions Bit Field Value Description 31 3 Reserved 0 R...

Page 80: ...ure 7 5 Reset Control Register RSCTRL 31 17 16 Reserved SWRST R 0 R W 1 15 0 KEY R W 3h LEGEND R W Read Write R Read only n value after reset Table 7 7 Reset Control Register RSCTRL Field Descriptions Bit Field Value Description 31 17 Reserved 0 Reserved 16 SWRST PLL software reset Register must be unlocked before writing to this bit Writes are possible only when qualified with a valid key 0 In so...

Page 81: ...ternal clock source selection 0 Use OSCIN for the PLL bypass clock 1 Use PLL1_SYSCLK3 for the PLL bypass clock 8 CLKMODE Reference clock selection 0 Internal oscillator crystal 1 Square wave 7 6 Reserved 1 Reserved 5 PLLENSRC 0 This bit must be cleared before the PLLEN bit will have any effect 4 Reserved 1 Reserved Write the default value when modifying this register 3 PLLRST PLL0 reset 0 PLL0 res...

Page 82: ...ield Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 6 Reserved 1 Reserved 5 PLLENSRC 0 This bit must be cleared before the PLLEN bit will have any effect 4 Reserved 1 Reserved Write the default value when modifying this register 3 PLLRST PLL1 reset 0 PLL1 reset is asserted 1 PLL1 reset is not asserted 2 Reserved 0 Reserved 1 PLLPWRDN PLL1 power down 0 PLL1 is operating 1 PLL1 ...

Page 83: ...erved R 0 15 5 4 0 Reserved OCSRC R 0 R W 14h LEGEND R W Read Write R Read only n value after reset Table 7 10 PLLC0 OBSCLK Select Register OCSEL Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 0 OCSRC 0 1Fh PLLC0 OBSCLK source Output on CLKOUT pin 0 13h Reserved 14h OSCIN 15h 16h Reserved 17h PLL0_SYSCLK1 18h PLL0_SYSCLK2 19h PLL0_SYSCLK3 1Ah PLL0_SYSCLK4 1Bh PLL0_SYSCLK...

Page 84: ...re 7 9 PLLC1 OBSCLK Select Register OCSEL 31 16 Reserved R 0 15 5 4 0 Reserved OCSRC R 0 R W 14h LEGEND R W Read Write R Read only n value after reset Table 7 11 PLLC1 OBSCLK Select Register OCSEL Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 0 OCSRC 0 1Fh PLLC1 OBSCLK source 0 13h Reserved 14h OSCIN 15h 16h Reserved 17h PLL1_SYSCLK1 18h PLL1_SYSCLK2 19h PLL1_SYSCLK3 1A...

Page 85: ...L VCO frequency specification limits 7 3 10 PLLC0 Pre Divider Control Register PREDIV The PLLC0 pre divider control register PREDIV is shown in Figure 7 11 and described in Table 7 13 Figure 7 11 PLLC0 Pre Divider Control Register PREDIV 31 16 Reserved R 0 15 14 5 4 0 PREDEN Reserved RATIO R W 1 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 7 13 PLLC0 Pre Divider Control Re...

Page 86: ...alue RATIO 1 RATIO defaults to 0 PLL divide by 1 7 3 12 PLLC1 Divider 1 Register PLLDIV1 The PLLC1 divider 1 register PLLDIV1 controls the divider for PLL1_SYSCLK1 PLLDIV1 is shown in Figure 7 13 and described in Table 7 15 Figure 7 13 PLLC1 Divider 1 Register PLLDIV1 31 16 Reserved R 0 15 14 5 4 0 D1EN Reserved RATIO R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 7 15...

Page 87: ...alue RATIO 1 RATIO defaults to 1 PLL divide by 2 7 3 14 PLLC1 Divider 2 Register PLLDIV2 The PLLC1 divider 2 register PLLDIV2 controls the divider for PLL1_SYSCLK2 PLLDIV2 is shown in Figure 7 15 and described in Table 7 17 Figure 7 15 PLLC1 Divider 2 Register PLLDIV2 31 16 Reserved R 0 15 14 5 4 0 D2EN Reserved RATIO R W 0 R 0 R W 1 LEGEND R W Read Write R Read only n value after reset Table 7 17...

Page 88: ...lue RATIO 1 RATIO defaults to 2h PLL divide by 3 7 3 16 PLLC1 Divider 3 Register PLLDIV3 The PLLC1 divider 3 register PLLDIV3 controls the divider for PLL1_SYSCLK3 PLLDIV3 is shown in Figure 7 17 and described in Table 7 19 Figure 7 17 PLLC1 Divider 3 Register PLLDIV3 31 16 Reserved R 0 15 14 5 4 0 D3EN Reserved RATIO R W 0 R 0 R W 2h LEGEND R W Read Write R Read only n value after reset Table 7 1...

Page 89: ... Value RATIO 1 RATIO defaults 3 PLL divide by 4 7 3 18 PLLC0 Divider 5 Register PLLDIV5 The PLLC0 divider 5 register PLLDIV5 controls the divider for PLL0_SYSCLK5 PLLDIV5 is shown in Figure 7 19 and described in Table 7 21 Figure 7 19 PLLC0 Divider 5 Register PLLDIV5 31 16 Reserved R 0 15 14 5 4 0 D5EN Reserved RATIO R W 1 R 0 R W 2h LEGEND R W Read Write R Read only n value after reset Table 7 21...

Page 90: ...lue RATIO 1 RATIO defaults to 0 PLL divide by 1 7 3 20 PLLC0 Divider 7 Register PLLDIV7 The PLLC0 divider 7 register PLLDIV7 controls the divider for PLL0_SYSCLK7 PLLDIV7 is shown in Figure 7 21 and described in Table 7 23 Figure 7 21 PLLC0 Divider 7 Register PLLDIV7 31 16 Reserved R 0 15 14 5 4 0 D7EN Reserved RATIO R W 1 R 0 R W 5h LEGEND R W Read Write R Read only n value after reset Table 7 23...

Page 91: ...or example RATIO 0 means divide by 1 7 3 22 PLLC1 Oscillator Divider 1 Register OSCDIV The PLLC1 oscillator divider 1 register OSCDIV controls the divider for PLLC1 OBSCLK dividing down the clock selected as the PLLC1 OBSCLK source The PLLC1 OBSCLK signal may be selected as the output on the CLKOUT pin The OSCDIV is shown in Figure 7 23 and described in Table 7 25 Figure 7 23 PLLC1 Oscillator Divi...

Page 92: ...ATIO 1 RATIO defaults to 1 PLL post divide by 2 7 3 24 PLL Controller Command Register PLLCMD The PLL controller command register PLLCMD contains the command bit for phase alignment A write of 1 initiates the command a write of 0 clears the bit but has no effect PLLCMD is shown in Figure 7 25 and described in Table 7 27 Figure 7 25 PLL Controller Command Register PLLCMD 31 16 Reserved R 0 15 1 0 R...

Page 93: ...7 28 PLL Controller Status Register PLLSTAT Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 STABLE OSC counter done oscillator assumed to be stable By the time the device comes out of reset this bit should become 1 0 No 1 Yes 1 Reserved 0 Reserved 0 GOSTAT Status of GO operation If 1 indicates GO operation is in progress 0 GO operation is not in progress 1 GO operation is...

Page 94: ...ue Description 31 7 Reserved 3h Reserved 6 ALN7 PLL0_SYSCLK7 needs to be aligned to others selected in this register 0 No 1 Yes 5 ALN6 PLL0_SYSCLK6 needs to be aligned to others selected in this register 0 No 1 Yes 4 ALN5 PLL0_SYSCLK5 needs to be aligned to others selected in this register 0 No 1 Yes 3 ALN4 PLL0_SYSCLK4 needs to be aligned to others selected in this register 0 No 1 Yes 2 ALN3 PLL0...

Page 95: ... 1 R W 1 LEGEND R W Read Write R Read only n value after reset Table 7 30 PLLC1 Clock Align Control Register ALNCTL Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 ALN3 PLL1_SYSCLK3 needs to be aligned to others selected in this register 0 No 1 Yes 1 ALN2 PLL1_SYSCLK2 needs to be aligned to others selected in this register 0 No 1 Yes 0 ALN1 PLL1_SYSCLK1 needs to be aligne...

Page 96: ...n 31 7 Reserved 0 Reserved 6 SYS7 PLL0_SYSCLK7 divide ratio is modified 0 Ratio is not modified 1 Ratio is modified 5 SYS6 PLL0_SYSCLK6 divide ratio is modified 0 Ratio is not modified 1 Ratio is modified 4 SYS5 PLL0_SYSCLK5 divide ratio is modified 0 Ratio is not modified 1 Ratio is modified 3 SYS4 PLL0_SYSCLK4 divide ratio is modified 0 Ratio is not modified 1 Ratio is modified 2 SYS3 PLL0_SYSCL...

Page 97: ... 0 R 0 R 0 LEGEND R Read only n value after reset Table 7 32 PLLC1 PLLDIV Ratio Change Status Register DCHANGE Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 SYS3 PLL1_SYSCLK3 divide ratio is modified 0 Ratio is not modified 1 Ratio is modified 1 SYS2 PLL1_SYSCLK2 divide ratio is modified 0 Ratio is not modified 1 Ratio is modified 0 SYS1 PLL1_SYSCLK1 divide ratio is mod...

Page 98: ... AUXCLK status is shown in the PLLC0 clock status register CKSTAT 0 PLLC0 AUXCLK is disabled 1 PLLC0 AUXCLK is enabled 7 3 31 PLLC1 Clock Enable Control Register CKEN The PLLC1 clock enable control register CKEN controls the PLLC1 OBSCLK clock CKEN is shown in Figure 7 32 and described in Table 7 34 Figure 7 32 PLLC1 Clock Enable Control Register CKEN 31 16 Reserved R 0 15 2 1 0 Reserved OBSEN Res...

Page 99: ...after reset Table 7 35 PLLC0 Clock Status Register CKSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 OBSEN OBSCLK on status PLLC0 OBSCLK is controlled in the PLLC0 oscillator divider 1 register OSCDIV by the OBSEN bit in the PLLC0 clock enable control register CKEN 0 PLLC0 OBSCLK is off 1 PLLC0 OBSCLK is on 0 AUXEN AUXCLK on status PLLC0 AUXCLK is controlled by the A...

Page 100: ... Reserved OBSEN Reserved R 2h R 0 R 0 LEGEND R Read only n value after reset Table 7 36 PLLC1 Clock Status Register CKSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 OBSEN OBSCLK on status PLLC1 OBSCLK is controlled in the PLLC1 oscillator divider 1 register OSCDIV by the OBSEN bit in the PLLC1 clock enable control register CKEN 0 PLLC1 OBSCLK is off 1 PLLC1 OBSCLK i...

Page 101: ...YS2ON SYS1ON R 1 R 1 R 1 R 1 R 1 R 1 R 1 R 1 LEGEND R W Read Write R Read only n value after reset Table 7 37 PLLC0 SYSCLK Status Register SYSTAT Field Descriptions Bit Field Value Description 31 7 Reserved 3h Reserved 6 SYS7ON PLL0_SYSCLK7 on status 0 Off 1 On 5 SYS6ON PLL0_SYSCLK6 on status 0 Off 1 On 4 SYS5ON PLL0_SYSCLK5 on status 0 Off 1 On 3 SYS4ON PLL0_SYSCLK4 on status 0 Off 1 On 2 SYS3ON ...

Page 102: ...C1 SYSCLK Status Register SYSTAT 31 8 Reserved R 0 7 3 2 1 0 Reserved SYS3ON SYS2ON SYS1ON R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 7 38 PLLC1 SYSCLK Status Register SYSTAT Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 SYS3ON PLL1_SYSCLK3 on status 0 Off 1 On 1 SYS2ON PLL1_SYSCLK2 on status 0 Off 1 On 0 SYS1ON PLL1_SYSCLK1 on status 0 ...

Page 103: ...lue Description 31 0 COUNT 0 FFFF FFFFh Counter value for lower 64 bits 7 3 37 Emulation Performance Counter 1 Register EMUCNT1 The emulation performance counter 1 register EMUCNT1 is shown in Figure 7 38 and described in Table 7 40 EMUCNT1 is for emulation performance profiling To start the counter a write must be made to EMUCNT0 This register is not writable but only used to start the register A...

Page 105: ... 2 Power Domain and Module Topology 106 8 3 Executing State Transitions 110 8 4 IcePick Emulation Support in the PSC 111 8 5 PSC Interrupts 111 8 6 PSC Registers 114 105 SPRUGX5A May 2011 Power and Sleep Controller PSC Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 106: ...ls modules that are controlled by the PSC the power domain they are associated with the LPSC assignment and the default power on reset module states See the device specific data manual for the peripherals available on a given device The module states and terminology are defined in Section 8 2 2 Even though there are 2 PSC modules with 2 power domains each on the device both PSC modules and all the...

Page 107: ...annel Controller 0 AlwaysON PD0 SwRstDisable 1 USB0 USB2 0 AlwaysON PD0 SwRstDisable 2 Not Used 3 GPIO AlwaysON PD0 SwRstDisable 4 Not Used 5 EMAC AlwaysON PD0 SwRstDisable 6 DDR2 mDDR AlwaysON PD0 SwRstDisable 7 McASP0 McASP0 FIFO AlwaysON PD0 SwRstDisable 8 9 Not Used 10 SPI1 AlwaysON PD0 SwRstDisable 11 Not Used 12 UART1 AlwaysON PD0 SwRstDisable 13 UART2 AlwaysON PD0 SwRstDisable 14 20 Not Use...

Page 108: ...rence between the Auto Sleep and Auto Wake states is that once the module is configured in Auto Sleep mode it will transition back to the clock disabled state automatically sleep after servicing the internal read write access request where as in Auto Wake mode on receiving the first internal read write access request the module will permanently transition from the clock disabled to clock enabled s...

Page 109: ...it has its clock on Generally software is not expected to initiate this state SwRstDisable Asserted Off A module in the SwResetDisable state has its module reset asserted and it has its clock disabled After initial power on several modules come up in the SwRstDisable state Generally software is not expected to initiate this state Auto Sleep De asserted Off A module in the Auto Sleep state also has...

Page 110: ...ple the external memory controller requires that you first place the SDRAM memory in self refresh mode before you invoke the PSC module state transitions if you want to maintain the memory contents The following procedure is directly applicable for all modules that are controlled via the PSC shown in Table 8 1 and Table 8 2 except for the core s To transition module state there are additional syst...

Page 111: ...ent values in the NEXT bit in PDCTL0 and the NEXT bit in MDCTLn as set by software 8 5 PSC Interrupts The PSC has an interrupt that is tied to the core interrupt controller This interrupt is named PSCINT in the interrupt map The PSC interrupt is generated when certain IcePick emulation events occur 8 5 1 Interrupt Events The PSC interrupt is generated when any of the following events occur Power D...

Page 112: ...nterrupt Registers The PSC interrupt enable bits are the EMUIHBIE bit in PDCTL1 PSC0 the EMUIHBIE and the EMURSTIE bits in MDCTLn where n is the modules that have IcePick emulation support as specified in Section 8 4 NOTE To interrupt the CPU the power sleep controller interrupt PSC0_ALLINT and PSC1_ALLINT must also be enabled appropriately in the ARM interrupt controller For details on the ARM in...

Page 113: ...terrupt service routine ISR when it receives the interrupt 1 Read the P n bit in PERRPR and or the M n bit in MERRPR0 the M n bit in MERRPR1 to determine the source of the interrupt s 2 For each active event that you want to service a Read the event status bits in PDSTATn and MDSTATn depending on the status bits read in the previous step to determine the event that caused the interrupt b Service t...

Page 114: ... 6 17 01C1 083Ch MDSTAT15 01C1 0A00h MDCTL0 Module Control n Register modules 0 15 Section 8 6 18 01C1 0A3Ch MDCTL15 Table 8 7 Power and Sleep Controller 1 PSC1 Registers Address Acronym Register Description Section 01E2 7000h REVID Revision Identification Register Section 8 6 1 01E2 7018h INTEVAL Interrupt Evaluation Register Section 8 6 2 01E2 7040h MERRPR0 Module Error Pending Register 0 module...

Page 115: ...tion Register INTEVAL The interrupt evaluation register INTEVAL is shown in Figure 8 2 and described in Table 8 9 Figure 8 2 Interrupt Evaluation Register INTEVAL 31 16 Reserved R 0 15 1 0 Reserved ALLEV R 0 W 0 LEGEND R Read only W Write only n value after reset Table 8 9 Interrupt Evaluation Register INTEVAL Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 ALLEV Evaluate...

Page 116: ...scription 31 15 Reserved 0 Reserved 14 M 14 Module interrupt status bit for module 14 ARM 0 Module 14 does not have an error condition 1 Module 14 has an error condition See the module status 14 register MDSTAT14 for the error condition 13 0 Reserved 0 Reserved 8 6 4 PSC1 Module Error Pending Register 0 modules 0 31 MERRPR0 The PSC1 module error pending register 0 MERRPR0 is shown in Figure 8 4 Fi...

Page 117: ...lue when modifying this register 14 M 14 Clears the interrupt status bit M 14 set in the PSC0 module error pending register 0 MERRPR0 and the interrupt status bits set in the module status 14 register MDSTAT14 0 A write of 0 has no effect 1 A write of 1 clears the M 14 bit in MERRPR0 and the EMUIHB and EMURST bits in MDSTAT14 13 0 Reserved 0 Reserved 8 6 6 PSC1 Module Error Clear Register 0 module...

Page 118: ...0 Reserved 0 Reserved 8 6 8 Power Error Clear Register PERRCR The power error clear register PERRCR is shown in Figure 8 8 and described in Table 8 13 Figure 8 8 Power Error Clear Register PERRCR 31 16 Reserved R 0 15 2 1 0 Reserved P 1 Rsvd R 0 W 0 R 0 LEGEND R Read only W Write only n value after reset Table 8 13 Power Error Clear Register PERRCR Field Descriptions Bit Field Value Description 31...

Page 119: ...nt to this power domain including PDCTL NEXT for this domain and MDCTL NEXT for all the modules residing on this domain If any of the NEXT fields are not matching the corresponding current state PDSTAT STATE MDSTAT STATE the PSC will transition those respective domain modules to the new NEXT state 0 GO 0 Always ON PD0 power domain GO transition command 0 A write of 0 has no effect 1 A write of 1 c...

Page 120: ... Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 GOSTAT 1 RAM Pseudo PD1 power domain transition status 0 No transition in progress 1 RAM Pseudo power domain is transitioning that is either the power domain is transitioning or modules in this power domain are transitioning 0 GOSTAT 0 Always ON PD0 power domain transition status 0 No transition in progress 1 Modules in Alw...

Page 121: ...lation altering user desired power domain states 1 Interrupt is active Emulation alters user desired power domain state 10 Reserved 0 Reserved 9 PORDONE Power_On_Reset POR Done status 0 Power domain POR is not done 1 Power domain POR is done 8 POR Power Domain Power_On_Reset POR status This bit reflects the POR status for this power domain including all modules in the domain 0 Power domain POR is ...

Page 122: ...lation altering user desired power domain states 1 Interrupt is active Emulation alters user desired power domain state 10 Reserved 0 Reserved 9 PORDONE Power_On_Reset POR Done status 0 Power domain POR is not done 1 Power domain POR is done 8 POR Power Domain Power_On_Reset POR status This bit reflects the POR status for this power domain including all modules in the domain 0 Power domain POR is ...

Page 123: ... FFh RAM wake count delay value Not recommended to change the default value 1Fh Bits 23 30 GOOD2ACCESS wake delay Bits 19 16 ON2GOOD wake delay 15 12 PDMODE 0 Fh Power down mode 0 Eh Reserved Fh Core on RAM array on RAM periphery on 11 10 Reserved 0 Reserved 9 EMUIHBIE Emulation alters power domain state interrupt enable 0 Disable interrupt 1 Enable interrupt 8 Reserved 1 Reserved 7 1 Reserved 0 R...

Page 124: ... down mode 0 Core off RAM array off RAM periphery off 1h Core off RAM array retention RAM periphery off deep sleep 2h 3h Reserved 4h Core retention RAM array off RAM periphery off 5h Core retention RAM array retention RAM periphery off deep sleep 6h 7h Reserved 8h Core on RAM array off RAM periphery off 9h Core on RAM array retention RAM periphery off deep sleep Ah Core on RAM array retention RAM ...

Page 125: ...ation Register PDCFG0 Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 PD_LOCK PDCTL NEXT lock For Always ON power domain this bit is a don t care 0 PDCTL NEXT bit is locked and cannot be changed in software 1 PDCTL NEXT bit is not locked 2 ICEPICK IcePick support 0 Not present 1 Present 1 RAM_PSM RAM power domain 0 Not a RAM power domain 1 RAM power domain 0 ALWAYSON Alwa...

Page 126: ...ation Register PDCFG1 Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 PD_LOCK PDCTL NEXT lock For Always ON power domain this bit is a don t care 0 PDCTL NEXT bit is locked and cannot be changed in software 1 PDCTL NEXT bit is not locked 2 ICEPICK IcePick support 0 Not present 1 Present 1 RAM_PSM RAM power domain 0 Not a RAM power domain 1 RAM power domain 0 ALWAYSON Alwa...

Page 127: ... all other modules 0 No emulation altering user desired module reset state 1 Emulation altered user desired module reset state If you desire to generate a PSCINT upon this event you must set the EMURSTIE bit in the module control 14 register MDCTL14 15 13 Reserved 0 Reserved 12 MCKOUT Module clock output status Shows status of module clock 0 Module clock is off 1 Module clock is on 11 Reserved 1 R...

Page 128: ...dshakes managed by the PSC to change the state of the clocks to the module Note It is not recommended to use the FORCE bit to disable the module clock unless specified 0 Force is disabled 1 Force is enabled 30 11 Reserved 0 Reserved 10 EMUIHBIE Interrupt enable for emulation alters module state This bit applies to ARM module module 14 0 Disable interrupt 1 Enable interrupt 9 EMURSTIE Interrupt ena...

Page 129: ...n 31 FORCE Force enable This bit forces the module state programmed in the NEXT bit in the module control 14 register MDCTL14 ignoring and bypassing all the clock stop request handshakes managed by the PSC to change the state of the clocks to the module Note It is not recommended to use the FORCE bit to disable the module clock unless specified 0 Force is disabled 1 Force is enabled 30 3 Reserved ...

Page 131: ... Features 133 9 5 Clock Management 134 9 6 ARM Sleep Mode Management 135 9 7 RTC Only Mode 137 9 8 Dynamic Voltage and Frequency Scaling DVFS 137 9 9 Deep Sleep Mode 139 9 10 Additional Peripheral Power Management Considerations 142 131 SPRUGX5A May 2011 Power Management Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 132: ... reduced by scaling the operating voltage when the performance requirements are not that high and the device can be operated at a corresponding lower frequency The capacitance is the capacitance of the switching nodes or the load capacitances on the switching I O pins The static power as the name suggests is independent of the switching frequency of the logic It can be shown as Pstatic f leakage c...

Page 133: ...n be put in sleep mode Reduces the dynamic power consumption sleep modes Additionally the ARM subsystem clock can be completely gated when not in use Voltage Management RTC only mode Allows removing power from all core and I O Reduces the dynamic and static power for standby supply and just have the real time clock RTC modes that require only the RTC to be functional running Dynamic Voltage and Fr...

Page 134: ...ll dynamic power consumption when modules are not active 9 5 2 Module Clock Frequency Scaling Module clock frequency is scalable by programming the PLL multiply and divide parameters Additionally some modules might also have internal clock dividers Reducing the clock frequency reduces the dynamic switching power consumption which scales linearly with frequency Chapter 6 details the clocking struct...

Page 135: ... Enable any interrupt for example an external interrupt that you plan to use as the wake up interrupt to exit from the WFI mode Enable the WFI mode using the following CP15 instruction MCR p15 0 r3 c7 c0 4 The following sequence describes the procedure to wake up from the WFI mode To wake up from the WFI mode trigger any enabled interrupt for example an external interrupt The ARM s PC jumps to the...

Page 136: ... the interrupt to be used as the wake up interrupt for example one of the CHIPSIG interrupts controlled by the chip signal register CHIPSIG in the system configuration SYSCFG module CHIPSIG 0 CHIPSIG 1 etc that will be used to wake up the ARM during the ARM clock on sequence 3 Execute the wait for interrupt WFI ARM instruction 9 6 3 ARM Subsystem Clock ON The ARM module defaults to the SwRstDisabl...

Page 137: ...owever software must be in place to restore the context of the device for example reinitialize internal registers setup cache memory configurations interrupt vectors etc 9 8 Dynamic Voltage and Frequency Scaling DVFS Dynamic voltage and frequency scaling DVFS consists of minimizing the idle time of the system The DVFS technique uses dynamic selection of the optimal frequency and voltage to allow a...

Page 138: ... MHZ You can use the OSCIN bypass mode to reduce the core and module clock frequencies to very low maintenance levels without using the PLL during periods of very low system activity It may be desirable for the bypass clock to not revert to OSCIN in some situations to preserved bandwidth during frequency scaling transitions For this reason the PLLC0 bypass clock can be set to PLL1_SYSCLK3 This sel...

Page 139: ...PCOUNT bit field in the deep sleep register DEEPSLEEP in the System Configuration Module This count determines the delay before the Deep Sleep logic releases the clocks to the device during wake up allowing the oscillator to stabilize 8 Set the SLEEPENABLE bit in DEEPSLEEP to 1 This automatically clears the SLEEPCOMPLETE bit 9 Begin polling the SLEEPCOMPLETE bit until it is set to 1 This bit is se...

Page 140: ...This automatically clears the SLEEPCOMPLETE bit Also the device now enters the Deep Sleep mode since the DEEPSLEEP pin is low For more details on the clock stop procedure of the DDR2 mDDR memory controller see the AM17x AM18x ARM Microprocessor DDR2 mDDR Memory Controller User s Guide SPRUFU3 9 9 2 2 Exiting Deep Sleep Mode Use the following procedure to exit the Deep Sleep state if the RTC is use...

Page 141: ...he on chip oscillator is disabled If the device is being clocked by an external source this clock may stay enabled the power savings from turning off this clock is minimal 5 The DEEPSLEEP pin is driven high and the on chip oscillator is enabled 6 The Deep Sleep counter beings counting valid clock cycles 7 The count has reached the number specified in the SLEEPCOUNT bit field and the SLEEPCOMPLETE ...

Page 142: ...ng edge of the GPIO signal 4 An external device drives the GP0 8 pin low 5 Software prepares the device for Deep Sleep mode 6 Set the SLEEPENABLE bit in DEEPSLEEP to 1 The Deep Sleep mode is immediately started and all device clocks are stopped Also the SLEEPCOMPLETE bit is automatically cleared 9 9 4 2 Exiting Deep Sleep Mode To exit the Deep Sleep mode follow this sequence 1 An external device d...

Page 143: ...DR2 mDDR memory controller 5 Connect the DDR2 mDDR memory controller CKE output pin to the memory 6 Disable the self refresh mode of the DDR2 mDDR memory controller After this sequence the DDR2 mDDR memory controller is ready for use Note that hardware logic is needed to disconnect the CKE output pin from the memory and to drive the memory s CKE input pin low For more details on the power manageme...

Page 145: ...CFG Module Topic Page 10 1 Introduction 146 10 2 Protection 146 10 3 Master Priority Control 147 10 4 SYSCFG Registers 148 145 SPRUGX5A May 2011 System Configuration SYSCFG Module Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 146: ... memory map The protection mechanisms that are present in the module are A special key sequence that needs to be written into a set of registers in the system configuration module to allow write ability to the rest of registers in the system configuration module Several registers in the module are only accessible when the CPU requesting read write access is in privileged mode 10 2 Protection The S...

Page 147: ...and peripherals that do not rely on the CPU or EDMA3 for initiating the data transfer to from them In order to determine allowed connection between masters and slave each master request source must have a unique master ID mstid associated with it The master ID is shown in Table 10 1 See the device specific data manual to determine the masters present on your device Each switched central resource S...

Page 148: ...ation Register 2 01C1 4014h DIEIDR3 1 Die Identification Register 3 01C1 4018h DEVIDR0 Device Identification Register 0 Privileged mode Section 10 4 2 01C1 4020h BOOTCFG Boot Configuration Register Privileged mode Section 10 4 3 01C1 4038h KICK0R Kick 0 Register Privileged mode Section 10 4 4 1 01C1 403Ch KICK1R Kick 1 Register Privileged mode Section 10 4 4 2 01C1 4040h HOST0CFG Host 0 Configurat...

Page 149: ...rol 16 Register Privileged mode Section 10 4 9 17 01C1 4164h PINMUX17 Pin Multiplexing Control 17 Register Privileged mode Section 10 4 9 18 01C1 4168h PINMUX18 Pin Multiplexing Control 18 Register Privileged mode Section 10 4 9 19 01C1 416Ch PINMUX19 Pin Multiplexing Control 19 Register Privileged mode Section 10 4 9 20 01C1 4170h SUSPSRC Suspend Source Register Privileged mode Section 10 4 10 01...

Page 150: ...er 0 DEVIDR0 The device identification register 0 DEVIDR0 contains a software readable version of the JTAG ID device Software can use this register to determine the version of the device on which it is executing The DEVIDR0 is shown in Figure 10 2 and described in Table 10 6 Figure 10 2 Device Identification Register 0 DEVIDR0 31 0 DEVID0 R nB7D 102Fh LEGEND R Read only n value after reset Table 1...

Page 151: ...G is shown in Figure 10 3 and described in Table 10 7 Figure 10 3 Boot Configuration Register BOOTCFG 31 16 Reserved R 0 15 0 BOOTMODE R 0 LEGEND R Read only n value after reset Table 10 7 Boot Configuration Register BOOTCFG Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 0 BOOTMODE 0 FFFFh Boot Mode This reflects the state of the boot mode pins 151 SPRUGX5A May 2011 Sy...

Page 152: ...4 4 1 Kick 0 Register KICK0R The KICK0R is shown in Figure 10 4 and described in Table 10 8 Figure 10 4 Kick 0 Register KICK0R 31 0 KICK1 R W 0 LEGEND R W Read Write n value after reset Table 10 8 Kick 0 Register KICK0R Field Descriptions Bit Field Value Description 31 0 KICK0 0 FFFF FFFFh KICK0R allows writing to unlock the kick0 data The written data must be 83E7 0B13h to unlock this register It...

Page 153: ...gure 10 6 Host 0 Configuration Register HOST0CFG 31 16 Reserved R 0 15 1 0 Reserved BOOTRDY R 0 R W 1 LEGEND R W Read Write R Read only n value after reset Table 10 10 Host 0 Configuration Register HOST0CFG Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 BOOTRDY ARM boot ready bit allowing ARM to boot 0 ARM held in reset mode 1 ARM released from wait in reset mode 153 SPR...

Page 154: ...Status Set Register IRAWSTAT 31 16 Reserved R 0 15 2 1 0 Reserved ADDRERR PROTERR R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 11 Interrupt Raw Status Set Register IRAWSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved Always read 0 1 ADDRERR Addressing violation error Reading this bit field reflects the raw status of the interrupt before...

Page 155: ...le Status Clear Register IENSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved Always read 0 1 ADDRERR Addressing violation error Reading this bit field reflects the interrupt enabled status 0 Indicates the interrupt is not set Writing 0 has no effect 1 Indicates the interrupt is set Writing 1 clears the status 0 PROTERR Protection violation error Reading this bit field r...

Page 156: ...ting a 1 enables this interrupt 10 4 6 4 Interrupt Enable Clear Register IENCLR The interrupt enable clear register IENCLR allows clearing disable the interrupt for address and or protection violation condition It also shows the value of the interrupt enable register IENSET The IENCLR is shown in Figure 10 10 and described in Table 10 14 Figure 10 10 Interrupt Enable Clear Register IENCLR 31 16 Re...

Page 157: ...escription 31 8 Reserved 0 Reserved Always read 0 7 0 EOIVECT 0 FFh EOI vector value Write the interrupt distribution value of the chip 10 4 7 Fault Registers The fault registers are a group of registers responsible for capturing the details on the faulty address protection violation errors accesses such as address and type of error 10 4 7 1 Fault Address Register FLTADDRR The fault address regist...

Page 158: ...Read only n value after reset Table 10 17 Fault Status Register FLTSTAT Field Descriptions Bit Field Value Description 31 24 ID 0 FFh Transfer ID of the first fault transfer 23 16 MSTID 0 FFh Master ID of the first fault transfer 15 13 Reserved 0 Reserved Always read 0 12 9 PRIVID 0 Fh Privilege ID of the first fault transfer 8 6 Reserved 0 Reserved Always read 0 5 0 TYPE Fault type of first fault...

Page 159: ...lue when modifying this register 26 24 Reserved 4h Reserved Write the default value when modifying this register 23 Reserved 0 Reserved Write the default value when modifying this register 22 20 Reserved 4h Reserved Write the default value when modifying this register 19 Reserved 0 Reserved Write the default value when modifying this register 18 16 Reserved 4h Reserved Write the default value when...

Page 160: ...eserved Write the default value when modifying this register 23 Reserved 0 Reserved Write the default value when modifying this register 22 20 Reserved 4h Reserved Write the default value when modifying this register 19 Reserved 0 Reserved Write the default value when modifying this register 18 16 EDMA31TC0 0 7h EDMA3_1_TC0 port priority Bit 0 priority 0 highest bit 7h priority 7 lowest 15 Reserve...

Page 161: ... Reserved 0 Reserved Write the default value when modifying this register 22 20 Reserved 6h Reserved Write the default value when modifying this register 19 Reserved 0 Reserved Write the default value when modifying this register 18 16 Reserved 0 Reserved Write the default value to all bits when modifying this register 15 Reserved 0 Reserved Write the default value when modifying this register 14 ...

Page 162: ...exing utility is available in AM18xx Pin Multiplexing Utility Application Report SPRABA2 10 4 9 1 Pin Multiplexing Control 0 Register PINMUX0 Figure 10 17 Pin Multiplexing Control 0 Register PINMUX0 31 28 27 24 23 20 19 16 PINMUX0_31_28 PINMUX0_27_24 PINMUX0_23_20 PINMUX0_19_16 R W 0 R W 0 R W 0 R W 0 15 12 11 8 7 4 3 0 PINMUX0_15_12 PINMUX0_11_8 PINMUX0_7_4 PINMUX0_3_0 R W 0 R W 0 R W 0 R W 0 LEG...

Page 163: ...lects Function GP0 11 I O 9h Fh Reserved X 15 12 PINMUX0_15_12 AFSX GP0 12 Control 0 Pin is 3 stated Z 1h Selects Function AFSX I O 2h 7h Reserved X 8h Selects Function GP0 12 I O 9h Fh Reserved X 11 8 PINMUX0_11_8 AFSR GP0 13 Control 0 Pin is 3 stated Z 1h Selects Function AFSR I O 2h 7h Reserved X 8h Selects Function GP0 13 I O 9h Fh Reserved X 7 4 PINMUX0_7_4 ACLKX GP0 14 Control 0 Pin is 3 sta...

Page 164: ... Reserved X 27 24 PINMUX1_27_24 AXR9 GP0 1 Control 0 Pin is 3 stated Z 1h Selects Function AXR9 I O 2h 7h Reserved X 8h Selects Function GP0 1 I O 9h Fh Reserved X 23 20 PINMUX1_23_20 AXR10 GP0 2 Control 0 Pin is 3 stated Z 1h Selects Function AXR10 I O 2h 7h Reserved X 8h Selects Function GP0 2 I O 9h Fh Reserved X 19 16 PINMUX1_19_16 AXR11 GP0 3 Control 0 Pin is 3 stated Z 1h Selects Function AX...

Page 165: ...unction GP0 5 I O 9h Fh Reserved X 7 4 PINMUX1_7_4 AXR14 GP0 6 Control 0 Pin is 3 stated Z 1h Selects Function AXR14 I O 2h 7h Reserved X 8h Selects Function GP0 6 I O 9h Fh Reserved X 3 0 PINMUX1_3_0 AXR15 GP0 7 Control 0 Pin is 3 stated Z 1h Selects Function AXR15 I O 2h 7h Reserved X 8h Selects Function GP0 7 I O 9h Fh Reserved X 165 SPRUGX5A May 2011 System Configuration SYSCFG Module Submit D...

Page 166: ... MII_TXD 0 O 9h Fh Reserved X 27 24 PINMUX2_27_24 AXR1 GP1 9 MII_TXD 1 Control 0 Pin is 3 stated Z 1h Selects Function AXR1 I O 2h 3h Reserved X 4h Selects Function GP1 9 I O 5h 7h Reserved X 8h Selects Function MII_TXD 1 O 9h Fh Reserved X 23 20 PINMUX2_23_20 AXR2 GP1 10 MII_TXD 2 Control 0 Pin is 3 stated Z 1h Selects Function AXR2 I O 2h 3h Reserved X 4h Selects Function GP1 10 I O 5h 7h Reserv...

Page 167: ...Selects Function AXR5 I O 2h 3h Reserved X 4h Selects Function GP1 13 I O 5h 7h Reserved X 8h Selects Function MII_TXCLK I 9h Fh Reserved X 7 4 PINMUX2_7_4 AXR6 GP1 14 MII_TXEN Control 0 Pin is 3 stated Z 1h Selects Function AXR6 I O 2h 3h Reserved X 4h Selects Function GP1 14 I O 5h 7h Reserved X 8h Selects Function MII_TXEN O 9h Fh Reserved X 3 0 PINMUX2_3_0 AXR7 GP1 15 Control 0 Pin is 3 stated...

Page 168: ...O 3h Reserved X 4h Selects Function GP8 1 I O 5h 7h Reserved X 8h Selects Function MII_RXD 0 I 9h Fh Reserved X 27 24 PINMUX3_27_24 SPI0_SCS 3 UART0_CTS GP8 2 MII_RXD 1 Control 0 Pin is 3 stated Z 1h Selects Function SPI0_SCS 3 I O 2h Selects Function UART0_CTS I 3h Reserved X 4h Selects Function GP8 2 I O 5h 7h Reserved X 8h Selects Function MII_RXD 1 I 9h Fh Reserved X 23 20 PINMUX3_23_20 SPI0_S...

Page 169: ...ed X 8h Selects Function MII_CRS I 9h Fh Reserved X 11 8 PINMUX3_11_8 SPI0_SOMI GP8 6 MII_RXER Control 0 Pin is 3 stated Z 1h Selects Function SPI0_SOMI I O 2h 3h Reserved X 4h Selects Function GP8 6 I O 5h 7h Reserved X 8h Selects Function MII_RXER I 9h Fh Reserved X 7 4 PINMUX3_7_4 SPI0_ENA MII_RXDV Control 0 Pin is 3 stated Z 1h Selects Function SPI0_ENA I O 2h 7h Reserved X 8h Selects Function...

Page 170: ...Function GP1 0 I O 9h Fh Reserved X 27 24 PINMUX4_27_24 SPI1_SCS 3 UART1_RXD GP1 1 Control 0 Pin is 3 stated Z 1h Selects Function SPI1_SCS 3 I O 2h Selects Function UART1_RXD I 3h 7h Reserved X 8h Selects Function GP1 1 I O 9h Fh Reserved X 23 20 PINMUX4_23_20 SPI1_SCS 4 UART2_TXD GP1 2 Control 0 Pin is 3 stated Z 1h Selects Function SPI1_SCS 4 I O 2h Selects Function UART2_TXD O 3h 7h Reserved X...

Page 171: ...s Function TM64P2_OUT12 O 5h 7h Reserved X 8h Selects Function GP1 5 I O 9h Fh Reserved X 7 4 PINMUX4_7_4 SPI0_SCS 0 TM64P1_OUT12 GP1 6 MDIO_D TM64P1_IN12 Control 0 Selects Function TM64P1_IN12 I 1h Selects Function SPI0_SCS 0 I O 2h Selects Function TM64P1_OUT12 O 3h Reserved X 4h Selects Function GP1 6 I O 5h 7h Reserved X 8h Selects Function MDIO_D I O 9h Fh Reserved X 3 0 PINMUX4_3_0 SPI0_SCS ...

Page 172: ... 24 PINMUX5_27_24 EMA_BA 1 GP2 9 Control 0 Pin is 3 stated Z 1h Selects Function EMA_BA 1 O 2h 7h Reserved X 8h Selects Function GP2 9 I O 9h Fh Reserved X 23 20 PINMUX5_23_20 SPI1_SIMO GP2 10 Control 0 Pin is 3 stated Z 1h Selects Function SPI1_SIMO I O 2h 7h Reserved X 8h Selects Function GP2 10 I O 9h Fh Reserved X 19 16 PINMUX5_19_16 SPI1_SOMI GP2 11 Control 0 Pin is 3 stated Z 1h Selects Func...

Page 173: ...X 7 4 PINMUX5_7_4 SPI1_SCS 0 GP2 14 TM64P3_IN12 Control 0 Selects Function TM64P3_IN12 I 1h Selects Function SPI1_SCS 0 I O 2h 7h Reserved X 8h Selects Function GP2 14 I O 9h Fh Reserved X 3 0 PINMUX5_3_0 SPI1_SCS 1 GP2 15 TM64P2_IN12 Control 0 Selects Function TM64P2_IN12 I 1h Selects Function SPI1_SCS 1 I O 2h 7h Reserved X 8h Selects Function GP2 15 I O 9h Fh Reserved X 173 SPRUGX5A May 2011 Sy...

Page 174: ...24 PINMUX6_27_24 EMA_WAIT 1 GP2 1 Control 0 Pin is 3 stated Z 1h Selects Function EMA_WAIT 1 I 2h 7h Reserved X 8h Selects Function GP2 1 I O 9h Fh Reserved X 23 20 PINMUX6_23_20 EMA_WE_DQM 1 GP2 2 Control 0 Pin is 3 stated Z 1h Selects Function EMA_WE_DQM 1 O 2h 7h Reserved X 8h Selects Function GP2 2 I O 9h Fh Reserved X 19 16 PINMUX6_19_16 EMA_WE_DQM 0 GP2 3 Control 0 Pin is 3 stated Z 1h Selec...

Page 175: ...tion GP2 5 I O 9h Fh Reserved X 7 4 PINMUX6_7_4 EMA_SDCKE GP2 6 Control 0 Pin is 3 stated Z 1h Selects Function EMA_SDCKE O 2h 7h Reserved X 8h Selects Function GP2 6 I O 9h Fh Reserved X 3 0 PINMUX6_3_0 EMA_CLK GP2 7 Control 0 Pin is 3 stated Z 1h Selects Function EMA_CLK O 2h 7h Reserved X 8h Selects Function GP2 7 I O 9h Fh Reserved X 175 SPRUGX5A May 2011 System Configuration SYSCFG Module Sub...

Page 176: ...eserved X 27 24 PINMUX7_27_24 EM_A_RW GP3 9 Control 0 Pin is 3 stated Z 1h Selects Function EM_A_RW O 2h 7h Reserved X 8h Selects Function GP3 9 I O 9h Fh Reserved X 23 20 PINMUX7_23_20 EMA_OE GP3 10 Control 0 Pin is 3 stated Z 1h Selects Function EMA_OE O 2h 7h Reserved X 8h Selects Function GP3 10 I O 9h Fh Reserved X 19 16 PINMUX7_19_16 EMA_WE GP3 11 Control 0 Pin is 3 stated Z 1h Selects Funct...

Page 177: ...ion GP3 13 I O 9h Fh Reserved X 7 4 PINMUX7_7_4 EMA_CS 3 GP3 14 Control 0 Pin is 3 stated Z 1h Selects Function EMA_CS 3 O 2h 7h Reserved X 8h Selects Function GP3 14 I O 9h Fh Reserved X 3 0 PINMUX7_3_0 EMA_CS 2 GP3 15 Control 0 Pin is 3 stated Z 1h Selects Function EMA_CS 2 O 2h 7h Reserved X 8h Selects Function GP3 15 I O 9h Fh Reserved X 177 SPRUGX5A May 2011 System Configuration SYSCFG Module...

Page 178: ... X 27 24 PINMUX8_27_24 EMA_D 9 GP3 1 Control 0 Pin is 3 stated Z 1h Selects Function EMA_D 9 I O 2h 7h Reserved X 8h Selects Function GP3 1 I O 9h Fh Reserved X 23 20 PINMUX8_23_20 EMA_D 10 GP3 2 Control 0 Pin is 3 stated Z 1h Selects Function EMA_D 10 I O 2h 7h Reserved X 8h Selects Function GP3 2 I O 9h Fh Reserved X 19 16 PINMUX8_19_16 EMA_D 11 GP3 3 Control 0 Pin is 3 stated Z 1h Selects Funct...

Page 179: ...tion GP3 5 I O 9h Fh Reserved X 7 4 PINMUX8_7_4 EMA_D 14 GP3 6 Control 0 Pin is 3 stated Z 1h Selects Function EMA_D 14 I O 2h 7h Reserved X 8h Selects Function GP3 6 I O 9h Fh Reserved X 3 0 PINMUX8_3_0 EMA_D 15 GP3 7 Control 0 Pin is 3 stated Z 1h Selects Function EMA_D 15 I O 2h 7h Reserved X 8h Selects Function GP3 7 I O 9h Fh Reserved X 179 SPRUGX5A May 2011 System Configuration SYSCFG Module...

Page 180: ... X 27 24 PINMUX9_27_24 EMA_D 1 GP4 9 Control 0 Pin is 3 stated Z 1h Selects Function EMA_D 1 I O 2h 7h Reserved X 8h Selects Function GP4 9 I O 9h Fh Reserved X 23 20 PINMUX9_23_20 EMA_D 2 GP4 10 Control 0 Pin is 3 stated Z 1h Selects Function EMA_D 2 I O 2h 7h Reserved X 8h Selects Function GP4 10 I O 9h Fh Reserved X 19 16 PINMUX9_19_16 EMA_D 3 GP4 11 Control 0 Pin is 3 stated Z 1h Selects Funct...

Page 181: ...ion GP4 13 I O 9h Fh Reserved X 7 4 PINMUX9_7_4 EMA_D 6 GP4 14 Control 0 Pin is 3 stated Z 1h Selects Function EMA_D 6 I O 2h 7h Reserved X 8h Selects Function GP4 14 I O 9h Fh Reserved X 3 0 PINMUX9_3_0 EMA_D 7 GP4 15 Control 0 Pin is 3 stated Z 1h Selects Function EMA_D 7 I O 2h 7h Reserved X 8h Selects Function GP4 15 I O 9h Fh Reserved X 181 SPRUGX5A May 2011 System Configuration SYSCFG Module...

Page 182: ...is 3 stated Z 1h Selects Function EMA_A 17 O 2h Selects Function MMCSD0_DAT 4 I O 3h 7h Reserved X 8h Selects Function GP4 1 I O 9h Fh Reserved X 23 20 PINMUX10_23_20 EMA_A 18 MMCSD0_DAT 3 GP4 2 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A 18 O 2h Selects Function MMCSD0_DAT 3 I O 3h 7h Reserved X 8h Selects Function GP4 2 I O 9h Fh Reserved X 19 16 PINMUX10_19_16 EMA_A 19 MMCSD0_DAT 2 GP...

Page 183: ...P4 5 I O 9h Fh Reserved X 7 4 PINMUX10_7_4 EMA_A 22 MMCSD0_CMD GP4 6 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A 22 O 2h Selects Function MMCSD0_CMD I O 3h 7h Reserved X 8h Selects Function GP4 6 I O 9h Fh Reserved X 3 0 PINMUX10_3_0 MMCSD0_CLK GP4 7 Control 0 Pin is 3 stated Z 1h Reserved X 2h Selects Function MMCSD0_CLK O 3h 7h Reserved X 8h Selects Function GP4 7 I O 9h Fh Reserved X ...

Page 184: ...served X 27 24 PINMUX11_27_24 EMA_A 9 GP5 9 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A 9 O 2h 7h Reserved X 8h Selects Function GP5 9 I O 9h Fh Reserved X 23 20 PINMUX11_23_20 EMA_A 10 GP5 10 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A 10 O 2h 7h Reserved X 8h Selects Function GP5 10 I O 9h Fh Reserved X 19 16 PINMUX11_19_16 EMA_A 11 GP5 11 Control 0 Pin is 3 stated Z 1h Selec...

Page 185: ...MA_A 14 MMCSD0_DAT 7 GP5 14 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A 14 O 2h Selects Function MMCSD0_DAT 7 I O 3h 7h Reserved X 8h Selects Function GP5 14 I O 9h Fh Reserved X 3 0 PINMUX11_3_0 EMA_A 15 MMCSD0_DAT 6 GP5 15 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A 15 O 2h Selects Function MMCSD0_DAT 6 I O 3h 7h Reserved X 8h Selects Function GP5 15 I O 9h Fh Reserved X 185 ...

Page 186: ... Fh Reserved X 27 24 PINMUX12_27_24 EMA_A 1 GP5 1 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A 1 O 2h 7h Reserved X 8h Selects Function GP5 1 I O 9h Fh Reserved X 23 20 PINMUX12_23_20 EMA_A 2 GP5 2 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A 2 O 2h 7h Reserved X 8h Selects Function GP5 2 I O 9h Fh Reserved X 19 16 PINMUX12_19_16 EMA_A 3 GP5 3 Control 0 Pin is 3 stated Z 1h Selec...

Page 187: ...nction GP5 5 I O 9h Fh Reserved X 7 4 PINMUX12_7_4 EMA_A 6 GP5 6 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A 6 O 2h 7h Reserved X 8h Selects Function GP5 6 I O 9h Fh Reserved X 3 0 PINMUX12_3_0 EMA_A 7 GP5 7 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A 7 O 2h 7h Reserved X 8h Selects Function GP5 7 I O 9h Fh Reserved X 187 SPRUGX5A May 2011 System Configuration SYSCFG Module Sub...

Page 188: ...served X 27 24 PINMUX13_27_24 GP6 9 Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects Function GP6 9 I O 9h Fh Reserved X 23 20 PINMUX13_23_20 GP6 10 Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects Function GP6 10 I O 9h Fh Reserved X 19 16 PINMUX13_19_16 GP6 11 Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects Function GP6 11 I O 9h Fh Reserved X 15 12 PINMUX13_15_12 GP6 12 Co...

Page 189: ...stated Z 1h Selects Function CLKOUT O 2h 7h Reserved X 8h Selects Function GP6 14 I O 9h Fh Reserved X 3 0 PINMUX13_3_0 RESETOUT GP6 15 Control 0 Selects Function RESETOUT O 1h Selects Function RESETOUT O 2h 7h Reserved X 8h Selects Function GP6 15 I O 9h Fh Reserved X 189 SPRUGX5A May 2011 System Configuration SYSCFG Module Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporat...

Page 190: ...1h 7h Reserved X 8h Selects Function RMII_RXD 0 I 9h Fh Reserved X 23 20 PINMUX14_23_20 RMII_RXD 1 Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects Function RMII_RXD 1 I 9h Fh Reserved X 19 16 PINMUX14_19_16 RMII_TXEN Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects Function RMII_TXEN O 9h Fh Reserved X 15 12 PINMUX14_15_12 RMII_TXD 0 Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h S...

Page 191: ...ptions continued Bit Field Value Description Type 1 3 0 PINMUX14_3_0 GP6 7 Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects Function GP6 7 I O 9h Fh Reserved X 191 SPRUGX5A May 2011 System Configuration SYSCFG Module Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 192: ...1h Fh Reserved X 15 12 PINMUX15_15_12 PINMUX15_15_12 Control 0 Pin is 3 stated Z 1h Fh Reserved X 11 8 PINMUX15_11_8 PINMUX15_11_8 Control 0 Pin is 3 stated Z 1h Fh Reserved X 7 4 PINMUX15_7_4 RMII_CRS_DV Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects Function RMII_CRS_DV I 9h Fh Reserved X 3 0 PINMUX15_3_0 RMII_MHZ_50_CLK Control 0 Enables sourcing of the 50 MHz reference clock from an e...

Page 193: ...tated Z 1h 7h Reserved X 8h Selects Function GP7 11 I O 9h Fh Reserved X 23 20 PINMUX16_23_20 GP7 12 Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects Function GP7 12 I O 9h Fh Reserved X 19 16 PINMUX16_19_16 GP7 13 Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects Function GP7 13 I O 9h Fh Reserved X 15 12 PINMUX16_15_12 GP7 14 Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects F...

Page 194: ...INMUX16 Field Descriptions continued Bit Field Value Description Type 1 3 0 PINMUX16_3_0 PINMUX16_3_0 Control 0 Pin is 3 stated Z 1h Fh Reserved X 194 System Configuration SYSCFG Module SPRUGX5A May 2011 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 195: ...h Reserved X 8h Selects Function GP7 3 I O 9h Fh Reserved X 23 20 PINMUX17_23_20 GP7 4 BOOT 4 Control 0 Selects Function BOOT 4 I 1h 7h Reserved X 8h Selects Function GP7 4 I O 9h Fh Reserved X 19 16 PINMUX17_19_16 GP7 5 BOOT 5 Control 0 Selects Function BOOT 5 I 1h 7h Reserved X 8h Selects Function GP7 5 I O 9h Fh Reserved X 15 12 PINMUX17_15_12 GP7 6 BOOT 6 Control 0 Selects Function BOOT 6 I 1h...

Page 196: ...ptions continued Bit Field Value Description Type 1 3 0 PINMUX17_3_0 GP7 9 Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects Function GP7 9 I O 9h Fh Reserved X 196 System Configuration SYSCFG Module SPRUGX5A May 2011 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 197: ...1h 7h Reserved X 8h Selects Function GP8 11 I O 9h Fh Reserved X 23 20 PINMUX18_23_20 GP8 12 Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects Function GP8 12 I O 9h Fh Reserved X 19 16 PINMUX18_19_16 GP8 13 Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects Function GP8 13 I O 9h Fh Reserved X 15 12 PINMUX18_15_12 GP8 14 Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects Function ...

Page 198: ...continued Bit Field Value Description Type 1 3 0 PINMUX18_3_0 GP7 1 BOOT 1 Control 0 Selects Function BOOT 1 I 1h 7h Reserved X 8h Selects Function GP7 1 I O 9h Fh Reserved X 198 System Configuration SYSCFG Module SPRUGX5A May 2011 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 199: ...tion GP8 0 I O 9h Fh Reserved X 27 24 PINMUX19_27_24 GP6 0 Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects Function GP6 0 I O 9h Fh Reserved X 23 20 PINMUX19_23_20 GP6 1 Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects Function GP6 1 I O 9h Fh Reserved X 19 16 PINMUX19_19_16 GP6 2 Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects Function GP6 2 I O 9h Fh Reserved X 15 12 PINMU...

Page 200: ...INMUX19_7_4 GP8 8 Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects Function GP8 8 I O 9h Fh Reserved X 3 0 PINMUX19_3_0 GP8 9 Control 0 Pin is 3 stated Z 1h 7h Reserved X 8h Selects Function GP8 9 I O 9h Fh Reserved X 200 System Configuration SYSCFG Module SPRUGX5A May 2011 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 201: ... R W Read Write n value after reset Table 10 41 Suspend Source Register SUSPSRC Field Descriptions Bit Field Value Description 31 30 Reserved 1 Reserved Write the default value to all bits when modifying this register 29 TIMER64P_2SRC Timer2 64 Emulation Suspend Source 0 ARM is the source of the emulation suspend 1 No emulation suspend 28 TIMER64P_1SRC Timer1 64 Emulation Suspend Source 0 ARM is t...

Page 202: ...0SRC USB0 USB 2 0 Emulation Suspend Source 0 ARM is the source of the emulation suspend 1 No emulation suspend 8 6 Reserved 1 Reserved Write the default value to all bits when modifying this register 5 EMACSRC EMAC Emulation Suspend Source 0 ARM is the source of the emulation suspend 1 No emulation suspend 4 Reserved 1 Reserved Write the default value to all bits when modifying this register 3 TIM...

Page 203: ...G0 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 42 Chip Signal Register CHIPSIG Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 Reserved 0 Reserved Write the default value when modifying this register 3 CHIPSIG3 Asserts SYSCFG_CHIPINT3 interrupt 0 No effect 1 Asserts interrupt 2 CHIPSIG2 Asserts SYSCFG_CHIPINT2 interrupt...

Page 204: ...ure 10 39 Chip Signal Clear Register CHIPSIG_CLR 31 16 Reserved R 0 15 5 4 3 2 1 0 Reserved Rsvd CHIPSIG3 CHIPSIG2 CHIPSIG1 CHIPSIG0 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 43 Chip Signal Clear Register CHIPSIG_CLR Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 Reserved 0 Reserved Write the default value when modif...

Page 205: ... priority configured by the MSTPRI register is evaluated at burst size boundaries The DBS value can significantly impact the standalone throughput performance depending on the source and destination bus width frequency burst support etc and the TC FIFO size etc Therefore the DBS size configuration should be carefully analyzed to meet the system s throughput performance requirements The CFGCHIP0 is...

Page 206: ... be carefully analyzed to meet the system s throughput performance requirements McASP0 AMUTEIN signal source control Allows selecting GPIO interrupt from different banks as source for the McASP0 AMUTEIN signal The CFGCHIP1 is shown in Figure 10 41 and described in Table 10 45 Figure 10 41 Chip Configuration 1 Register CFGCHIP1 31 16 Reserved R W 0 15 14 13 12 4 3 0 Rsvd EDMA31TC0DBS Reserved AMUTE...

Page 207: ...s not sensing voltage presence on the VBUS pin 1 PHY is sensing voltage presence on the VBUS pin 15 RESET USB2 0 PHY reset 0 Not in reset 1 USB2 0 PHY in reset 14 13 USB0OTGMODE USB2 0 OTG subsystem mode 0 No override PHY drive signals to controller based on its comparators for VBUS and ID pins 1h Override phy values to force USB host operation 2h Override phy values to force USB device operation ...

Page 208: ...e 48 MHz clock during USB SUSPEND 0 USB2 0 PHY is allowed to stop the 48 MHz clock during USB SUSPEND 1 USB2 0 PHY is prevented from stopping the 48 MHz clock during USB SUSPEND 5 USB0SESNDEN USB2 0 Session End comparator enable 0 Session End comparator is disabled 1 Session End comparator is enabled 4 USB0VBDTCTEN USB2 0 VBUS line comparators enable 0 All VBUS line comparators are disabled 1 All ...

Page 209: ...45PENA EMA_CLKSRC Reserved R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 47 Chip Configuration 3 Register CFGCHIP3 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 9 Reserved 7Fh Reserved Write the default value to all bits when modifying this register 8 RMII_SEL EMAC MII RMII mode select 0 MII mode 1 RMII ...

Page 210: ...s when modifying this register 0 AMUTECLR0 Clears the latched GPIO interrupt for AMUTEIN of McASP0 when set to 1 0 No effect 1 Clears interrupt 10 4 18 VTP I O Control Register VTPIO_CTL The VTP I O control register VTPIO_CTL is used to control the calibration of the DDR2 mDDR memory controller I Os with respect to voltage temperature and process VTP The voltage temperature and process information...

Page 211: ...1 FORCEDNN 0 Force decrease NFET drive 10 FORCEUPP 0 Force increase PFET drive 9 FORCEUPN 0 Force increase PFET drive 8 PWRSAVE VTP power save mode Turn off power to the external resistor when it is not needed The PWRSAVE bit setting is only valid when the POWERDN bit is cleared to 0 0 Disable power save mode 1 Enable power save mode 7 LOCK VTP impedance lock Lock impedance value so that the VTP c...

Page 212: ...on this device 0 No termination 1h 3h Reserved 9 8 ODT_TERMOFF Controls Thevenin termination mode while I O is not in read or write mode Termination is not supported on this device 0 No termination 1h 3h Reserved 7 6 Reserved 0 Reserved 5 DDR_PDENA Enables pull downs for mDDR mode should be disabled for DDR2 0 Pull downs are disabled Disable pull downs when using DDR2 1 Pull downs are enabled Enab...

Page 213: ... bit to 0 when the device is awakened from deep sleep 0 Device is in normal operating mode DEEPSLEEP pin has no effect 1 Deep sleep mode is enabled setting DEEPSLEEP pin low initiates oscillator shut down 30 SLEEPCOMPLETE Deep sleep complete Once the deep sleep process starts the software must poll the SLEEPCOMPLETE bit when the SLEEPCOMPLETE bit is read as 1 the software should clear the SLEEPENA...

Page 214: ... pullup pulldown select register PUPD_SEL selects between the pull up or pull down functionality for the pin group n defined in your device specific data manual The PUPD_SEL is shown in Figure 10 49 and described in Table 10 53 and Table 10 54 NOTE The PUPD_SEL settings are not active until the device is out of reset During reset all of the CP n pins are weakly pulled down If the application requi...

Page 215: ...n Group CP 17 is configured for pull up by default 16 PUPDSEL 16 1 Pin Group CP 16 is configured for pull up by default 15 PUPDSEL 15 1 Pin Group CP 15 is configured for pull up by default 14 PUPDSEL 14 1 Pin Group CP 14 is configured for pull up by default 13 PUPDSEL 13 1 Pin Group CP 13 is configured for pull up by default 12 PUPDSEL 12 1 Pin Group CP 12 is configured for pull up by default 11 P...

Page 216: ...h LEGEND R W Read Write n value after reset Table 10 55 RXACTIVE Control Register RXACTIVE Field Descriptions Bit Field Value Description 31 0 RXACTIVE n Enables the LVCMOS receivers on pin group n See your device specific data manual for pin group information Receivers should only be disabled if the associated pin group is not being used 0 LVCMOS receivers for pin group n are disabled 1 LVCMOS re...

Page 217: ...ller AINTC Topic Page 11 1 Introduction 218 11 2 Interrupt Mapping 218 11 3 AINTC Methodology 221 11 4 AINTC Registers 225 217 SPRUGX5A May 2011 ARM Interrupt Controller AINTC Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 218: ... active low debug interrupts See the ARM926EJ Technical Reference Manual for information about the ARM s FIQ and IRQ interrupts 11 2 Interrupt Mapping The AINTC supports up to 101 system interrupts from different peripherals to be mapped to 32 channels inside the AINTC see Figure 11 1 Interrupts from these 32 channels are further mapped to either an ARM FIQ interrupt or an ARM IRQ interrupt Any of...

Page 219: ... Register 30 SYSCFG_CHIPINT2 SYSCFG CHIPSIG Register 31 SYSCFG_CHIPINT3 SYSCFG CHIPSIG Register 32 EDMA3_0_TC1_ERRINT EDMA3_0 Transfer Controller 1 Error Interrupt 33 EMAC_C0RXTHRESH EMAC Core 0 Receive Threshold Interrupt 34 EMAC_C0RX EMAC Core 0 Receive Interrupt 35 EMAC_C0TX EMAC Core 0 Transmit Interrupt 36 EMAC_C0MISC EMAC Core 0 Miscellaneous Interrupt 37 EMAC_C1RXTHRESH EMAC Core 1 Receive ...

Page 220: ...INT7 Timer64P2 Compare Interrupt 7 82 T64P3_CMPINT0 Timer64P3 Compare Interrupt 0 83 T64P3_CMPINT1 Timer64P3 Compare Interrupt 1 84 T64P3_CMPINT2 Timer64P3 Compare Interrupt 2 85 T64P3_CMPINT3 Timer64P3 Compare Interrupt 3 86 T64P3_CMPINT4 Timer64P3 Compare Interrupt 4 87 T64P3_CMPINT5 Timer64P3 Compare Interrupt 5 88 T64P3_CMPINT6 Timer64P3 Compare Interrupt 6 89 T64P3_CMPINT7 Timer64P3 Compare I...

Page 221: ...type of interrupts The AINTC encompasses many functions to process the system interrupts and prepare them for the host interface These functions are processing enabling status channel mapping host interrupt mapping prioritization vectorization debug and host interfacing Figure 11 2 illustrates the flow of system interrupts through the functions to the host The following subsections describe each p...

Page 222: ...ure the enabled status of interrupts The pending status reflects whether the system interrupt occurred since the last time the status register bit was cleared Each bit in the status register is individually clearable 11 3 4 Interrupt Channel Mapping The AINTC has 32 internal channels to which enabled system interrupts can be mapped Higher priority interrupts should be mapped to channels 0 and 1 Ot...

Page 223: ...upt enable index clear register HIEICR 11 3 7 Interrupt Nesting If interrupt service routines ISRs consume a large number of CPU cycles and may delay the servicing of other interrupts the AINTC can perform a nesting function in its prioritization Nesting is a method of disabling certain interrupts usually lower priority interrupts when an interrupt is taken so that only those desired interrupts ca...

Page 224: ...ware interrupt 8 Execute the ISR at the address stored from step 5 During this step interrupts enabled by the new nest priority level will be able to preempt the ISR 9 Disable the ARM hardware interrupt 10 Discard the most recent priority level in the nest priority stack and restore the previous priority level to HINLRn by setting the OVERRIDE bit 11 Enable the ARM hardware interrupt 11 3 8 Interr...

Page 225: ...Section 11 4 7 FFFE E02Ch EICR System Interrupt Enable Indexed Clear Register Section 11 4 8 FFFE E034h HIEISR Host Interrupt Enable Indexed Set Register Section 11 4 9 FFFE E038h HIEICR Host Interrupt Enable Indexed Clear Register Section 11 4 10 FFFE E050h VBR Vector Base Register Section 11 4 11 FFFE E054h VSR Vector Size Register Section 11 4 12 FFFE E058h VNR Vector Null Register Section 11 4...

Page 226: ...ter 2 Section 11 4 36 FFFE F500h HIER Host Interrupt Enable Register Section 11 4 37 FFFE F600h HIPVR1 Host Interrupt Prioritized Vector Register 1 Section 11 4 38 FFFE F604h HIPVR2 Host Interrupt Prioritized Vector Register 2 Section 11 4 39 11 4 1 Revision Identification Register REVID The revision identification register REVID is shown in Figure 11 3 and described in Table 11 3 Figure 11 3 Revi...

Page 227: ...lue Description 31 5 Reserved 0 Reserved 4 PRHOLDMODE Enables priority holding mode 0 No priority holding Prioritized MMRs will continually update 1 Priority holding enabled Prioritized Index and Vector Address MMRs will hold their value after the first is read See Section 11 3 6 for details 3 2 NESTMODE 0 3h Nesting mode 0 No nesting 1h Automatic individual nesting per host interrupt 2h Automatic...

Page 228: ...g level across all host interrupts when automatic global nesting mode is set The nesting level is the channel and all of lower priority that are nested out because of a current interrupt The GNLR is shown in Figure 11 6 and described in Table 11 6 Figure 11 6 Global Nesting Level Register GNLR 31 30 16 OVERRIDE Reserved R W 0 R 0 15 9 8 0 Reserved NESTLVL R 0 R W 100h LEGEND R W Read Write R Read ...

Page 229: ...pt given in the INDEX value Reads return 0 11 4 6 System Interrupt Status Indexed Clear Register SICR The system interrupt status indexed clear register SICR allows clearing the status of an interrupt The interrupt to clear is the INDEX value written This clears the Raw Status Register bit of the given INDEX The SICR is shown in Figure 11 8 and described in Table 11 8 Figure 11 8 System Interrupt ...

Page 230: ... given in the INDEX value Reads return 0 11 4 8 System Interrupt Enable Indexed Clear Register EICR The system interrupt enable indexed clear register EICR allows disabling an interrupt The interrupt to disable is the INDEX value written This clears the Enable Register bit of the given INDEX The EICR is shown in Figure 11 10 and described in Table 11 10 Figure 11 10 System Interrupt Enable Indexed...

Page 231: ...ue Reads return 0 0 Writing a 0 sets FIQ 1 Writing a 1 sets IRQ 11 4 10 Host Interrupt Enable Indexed Clear Register HIEICR The host interrupt enable indexed clear register HIEICR allows disabling a host interrupt output The host interrupt to disable is the INDEX value written This disables the host interrupt output The HIEICR is shown in Figure 11 12 and described in Table 11 12 Figure 11 12 Host...

Page 232: ...sizes to space the calculated vector addresses for the initial ISR targets the ISR targets could branch off to the full ISR routines The VSR is shown in Figure 11 14 and described in Table 11 14 NOTE The VSR must be configured even if the desired value is equal to the default value Figure 11 14 Vector Size Register VSR 31 16 Reserved R 0 15 8 7 0 Reserved SIZE R 0 R W 0 LEGEND R W Read Write R Rea...

Page 233: ...hows the interrupt number of the highest priority interrupt pending across all the host interrupts The GPIR is shown in Figure 11 16 and described in Table 11 16 Figure 11 16 Global Prioritized Index Register GPIR 31 30 16 NONE Reserved R 1 R 0 15 10 9 0 Reserved PRI_INDX R 0 R 0 LEGEND R Read only n value after reset Table 11 16 Global Prioritized Index Register GPIR Field Descriptions Bit Field ...

Page 234: ...m interrupt status raw set register 1 SRSR1 shows the pending enabled status of the system interrupts 0 to 31 Software can write to SRSR1 to set a system interrupt without a hardware trigger There is one bit per system interrupt The SRSR1 is shown in Figure 11 18 and described in Table 11 18 Figure 11 18 System Interrupt Status Raw Set Register 1 SRSR1 31 0 RAW_STATUS n W 0 LEGEND W Write only n v...

Page 235: ... n to set the status of the system interrupt n 32 11 4 18 System Interrupt Status Raw Set Register 3 SRSR3 The system interrupt status raw set register 3 SRSR3 shows the pending enabled status of the system interrupts 64 to 95 Software can write to SRSR3 to set a system interrupt without a hardware trigger There is one bit per system interrupt The SRSR3 is shown in Figure 11 20 and described in Ta...

Page 236: ...abled Clear Register 1 SECR1 The system interrupt status enabled clear register 1 SECR1 shows the pending enabled status of the system interrupts 0 to 31 Software can write to SECR1 to clear a system interrupt after it has been serviced If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly There is one bi...

Page 237: ... to clear the status of the system interrupt n 32 11 4 22 System Interrupt Status Enabled Clear Register 3 SECR3 The system interrupt status enabled clear register 3 SECR3 shows the pending enabled status of the system interrupts 64 to 95 Software can write to SECR3 to clear a system interrupt after it has been serviced If a system interrupt status is not cleared then another host interrupt may no...

Page 238: ...atus and clearing of the system interrupts 96 to 100 Reads return the enabled status before enabling with the Enable Registers 0 Writing a 0 has no effect 1 Write a 1 in bit position n to clear the status of the system interrupt n 96 11 4 24 System Interrupt Enable Set Register 1 ESR1 The system interrupt enable set register 1 ESR1 enables system interrupts 0 to 31 to trigger outputs System interr...

Page 239: ...ion n to set the enable for system interrupt n 32 11 4 26 System Interrupt Enable Set Register 3 ESR3 The system interrupt enable set register 3 ESR3 enables system interrupts 64 to 95 to trigger outputs System interrupts that are not enabled do not interrupt the host There is one bit per system interrupt The ESR3 is shown in Figure 11 28 and described in Table 11 28 Figure 11 28 System Interrupt ...

Page 240: ... Write a 1 in bit position n to set the enable for system interrupt n 96 11 4 28 System Interrupt Enable Clear Register 1 ECR1 The system interrupt enable clear register 1 ECR1 disables system interrupts 0 to 31 to map to channels System interrupts that are not enabled do not interrupt the host There is one bit per system interrupt The ECR1 is shown in Figure 11 30 and described in Table 11 30 Fig...

Page 241: ...n n to clear the enable for system interrupt n 32 11 4 30 System Interrupt Enable Clear Register 3 ECR3 The system interrupt enable clear register 3 ECR3 disables system interrupts 64 to 95 to map to channels System interrupts that are not enabled do not interrupt the host There is one bit per system interrupt The ECR3 is shown in Figure 11 32 and described in Table 11 32 Figure 11 32 System Inter...

Page 242: ...ite a 1 in bit position n to clear the enable for system interrupt n 96 11 4 32 Channel Map Registers CMR0 CMR25 The channel map registers CMR0 CMR25 define the channel for each system interrupt There is one register per 4 system interrupts The CMRn is shown in Figure 11 34 and described in Table 11 34 Figure 11 34 Channel Map Registers CMRn 31 24 23 16 CHNL_NPLUS3 CHNL_NPLUS2 R W 0 R W 0 15 8 7 0...

Page 243: ...priority pending interrupt for FIQ host interrupt 11 4 34 Host Interrupt Prioritized Index Register 2 HIPIR2 The host interrupt prioritized index register 2 HIPIR2 shows the highest priority current pending interrupt for the IRQ interrupt The HIPIR2 is shown in Figure 11 36 and described in Table 11 36 Figure 11 36 Host Interrupt Prioritized Index Register 2 HIPIR2 31 30 16 NONE Reserved R 1 R 0 1...

Page 244: ...e OVERRIDE is set and then the write data is used 11 4 36 Host Interrupt Nesting Level Register 2 HINLR2 The host interrupt nesting level register 2 HINLR2 displays and controls the nesting level for IRQ host interrupt The nesting level controls which channel and lower priority channels are nested The HINLR2 is shown in Figure 11 38 and described in Table 11 38 Figure 11 38 Host Interrupt Nesting ...

Page 245: ...ter HIDISR The HIER is shown in Figure 11 39 and described in Table 11 39 Figure 11 39 Host Interrupt Enable Register HIER 31 16 Reserved R 0 15 2 1 0 Reserved IRQ FIQ R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 11 39 Host Interrupt Enable Register HIER Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 IRQ Enable of IRQ 0 IRQ is disabled 1 IR...

Page 246: ... vector address across for the FIQ host interrupt 11 4 39 Host Interrupt Prioritized Vector Register 2 HIPVR2 The host interrupt prioritized vector register 2 HIPVR2 shows the interrupt vector address of the highest priority interrupt pending for IRQ host interrupt The HIPVR2 is shown in Figure 11 41 and described in Table 11 41 Figure 11 41 Host Interrupt Prioritized Vector Register 2 HIPVR2 31 0...

Page 247: ...Chapter 12 SPRUGX5A May 2011 Boot Considerations Topic Page 12 1 Introduction 248 247 SPRUGX5A May 2011 Boot Considerations Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated ...

Page 248: ... the BOOT pins The following boot modes are supported NAND Flash boot 8 bit NAND 16 bit NAND NOR Flash boot NOR Direct boot 8 bit or 16 bit NOR Legacy boot 8 bit or 16 bit NOR AIS boot 8 bit or 16 bit I2C0 Boot EEPROM Master Mode External Host Slave Mode SPI0 SPI1 Boot Serial Flash Master Mode Serial EEPROM Master Mode External Host Slave Mode UART0 1 2 Boot External Host See Using the AM18xx Boot...

Page 249: ...section Section 7 3 33 Added subsection Subsequent subsections figures and tables renumbered Section 8 2 Added NOTE Section 10 2 2 Changed NOTE Section 10 4 9 Added Type column to all tables Table 10 36 Changed Description of PINMUX15_3_0 bit value 0 Changed Description of PINMUX15_3_0 bit value 8h Table 11 1 Changed Interrupt Name and Source of Events 74 89 Section 11 3 2 Changed step 3 b Section...

Page 250: ...horized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge ...

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