Timing Controller Register Map
966
SBAU337 – May 2020
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.15.20 Register 99h (offset = 99h) [reset = 0h]
Figure 2-2227. Register 99h
7
6
5
4
3
2
1
0
TXNCOSEL_MODE_AB
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2242. Register 99 Field Descriptions
Bit
Field
Type
Reset
Description
1-0
TXNCOSEL_MOD
E_AB
R/W
0h
The 4 bits of NCOSel get routed to both A and B channels
according to mode as follow. (NCOsel for (band1), (band0))
00 -> (b0,b0),(b0,b0.b0,b0)
01 -> (b1,b0),(b1,b0,b1,b0)
02 -> (0,0),(b3,b2,b1,b0)
03 -> (0,0),(0,0,0,0)
2.15.21 Register 9Ah (offset = 9Ah) [reset = 0h]
Figure 2-2228. Register 9Ah
7
6
5
4
3
2
1
0
TXNCOSEL_MODE_CD
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2243. Register 9A Field Descriptions
Bit
Field
Type
Reset
Description
1-0
TXNCOSEL_MOD
E_CD
R/W
0h
The 4 bits of NCOSel get routed to both C and D channels
according to mode as follow. (NCOsel for (band1), (band0))
If broadcast_txncosel==1
00 -> (b0,b0),(b0,b0.b0,b0)
01 -> (b1,b0),(b1,b0,b1,b0)
02 -> (0,0),(b3,b2,b1,b0)
03 -> (0,0),(0,0,0,0)
if broadcast_txncosel==0
00 -> (b2,b2),(b2,b2.b2,b2)
01 -> (b3,b2),(b3,b2,b3,b2)
02 -> (0,0),(b3,b2,b1,b0)
03 -> (0,0),(0,0,0,0)
2.15.22 Register 9Ch (offset = 9Ch) [reset = 0h]
Figure 2-2229. Register 9Ch
7
6
5
4
3
2
1
0
ENABLE_TXNCOSEL_A
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2244. Register 9C Field Descriptions
Bit
Field
Type
Reset
Description
5-0
ENABLE_TXNCOS
EL_A
R/W
0h
If enable == 0 then the corresponding bit in txncosel for that
channel is made 0, else ncosel is sent as it is