Texas Instruments AFE79 Series Programming & User Manual Download Page 1157 | Manualshive

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IO Wrap Register Map

1157

SBAU337 – May 2020

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Copyright © 2020, Texas Instruments Incorporated

Serial Interface Register Maps

2.16.479 Register 8ACh (offset = 8ACh) [reset = 0h]

Figure 2-2742. Register 8ACh

7

6

5

4

3

2

1

0

SEL_INTPI_ADC_SYNC_N_CD_

0

POL_INTPI_AD

C_SYNC_N_C

D_0

R/W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 2-2758. Register 8AC Field Descriptions

Bit

Field

Type

Reset

Description

2-1

SEL_INTPI_ADC_
SYNC_N_CD_0

R/W

0h

select control for intpi_adc_sync_n_cd_0. 0 indicates take
from parallel GPIO 1 indicates take from Serial LVDS GPIO 2
indicates take from Serdes GPIO

0-0

POL_INTPI_ADC_
SYNC_N_CD_0

R/W

0h

polarity control for intpi_adc_sync_n_cd_0. 0 indicates pass
through from GPIO when selected 1 indicates inverted signal

2.16.480 Register 8ADh (offset = 8ADh) [reset = 2h]

Figure 2-2743. Register 8ADh

7

6

5

4

3

2

1

0

OVR_SEL_INT

PI_ADC_SYNC

_N_CD_0

OVR_INTPI_A

DC_SYNC_N_

CD_0

R/W-1h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 2-2759. Register 8AD Field Descriptions

Bit

Field

Type

Reset

Description

1-1

OVR_SEL_INTPI_
ADC_SYNC_N_CD
_0

R/W

1h

control to select whether the input function
intpi_adc_sync_n_cd_0 needs to be overriden ot not. 1
indicates override.

0-0

OVR_INTPI_ADC_
SYNC_N_CD_0

R/W

0h

override value for ovr_sel_intpi_adc_sync_n_cd_0 is made
high

2.16.481 Register 8B0h (offset = 8B0h) [reset = 0h]

Figure 2-2744. Register 8B0h

7

6

5

4

3

2

1

0

SEL_INTPI_ADC_SYNC_N_CD_

1

POL_INTPI_AD

C_SYNC_N_C

D_1

R/W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 2-2760. Register 8B0 Field Descriptions

Bit

Field

Type

Reset

Description

2-1

SEL_INTPI_ADC_
SYNC_N_CD_1

R/W

0h

select control for intpi_adc_sync_n_cd_1. 0 indicates take
from parallel GPIO 1 indicates take from Serial LVDS GPIO 2
indicates take from Serdes GPIO

0-0

POL_INTPI_ADC_
SYNC_N_CD_1

R/W

0h

polarity control for intpi_adc_sync_n_cd_1. 0 indicates pass
through from GPIO when selected 1 indicates inverted signal

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Summary of Contents for AFE79 Series

Page 1: ...AFE79xx Programming User Guide Technical Reference Manual Literature Number SBAU337 May 2020 ...

Page 2: ...terface Rate Configuration Opcode 0x29 137 1 4 6 FB Interface Rate Configuration Opcode 0x2A 137 1 4 7 TX Interface Rate Configuration Opcode 0x2B 137 1 4 8 RX ADC Rate Configuration Opcode 0x2C 137 1 4 9 FB ADC Rate Configuration Opcode 0x2D 137 1 4 10 TX DAC Rate Configuration Opcode 0x2E 138 1 4 11 Channel Frequency Resolution Opcode 0x2F 138 1 4 12 RX Channel Frequency Configuration Opcode 0x3...

Page 3: ... 7 Register 63h offset 63h reset 0h 153 2 2 8 Register 66h offset 66h reset 0h 153 2 2 9 Register 68h offset 68h reset 0h 154 2 2 10 Register 6Ah offset 6Ah reset 0h 154 2 2 11 Register 6Ch offset 6Ch reset 0h 154 2 2 12 Register 6Dh offset 6Dh reset 0h 154 2 2 13 Register 6Eh offset 6Eh reset 0h 155 2 2 14 Register 6Fh offset 6Fh reset 0h 155 2 2 15 Register 70h offset 70h reset 0h 155 2 2 16 Reg...

Page 4: ...h 184 2 3 41 Register 4Fh offset 4Fh reset 76h 184 2 3 42 Register 50h offset 50h reset 20h 185 2 3 43 Register 52h offset 52h reset 0h 185 2 3 44 Register 53h offset 53h reset 0h 186 2 3 45 Register 54h offset 54h reset 0h 187 2 3 46 Register 55h offset 55h reset 32h 187 2 3 47 Register 56h offset 56h reset 53h 188 2 3 48 Register 57h offset 57h reset 0h 188 2 3 49 Register 58h offset 58h reset 0...

Page 5: ...er A8h offset A8h reset 10h 211 2 3 95 Register A9h offset A9h reset ABh 211 2 3 96 Register AAh offset AAh reset CDh 211 2 3 97 Register ABh offset ABh reset EFh 211 2 3 98 Register ACh offset ACh reset 10h 212 2 3 99 Register ADh offset ADh reset ABh 212 2 3 100 Register AEh offset AEh reset CDh 212 2 3 101 Register AFh offset AFh reset EFh 213 2 3 102 Register B0h offset B0h reset 0h 213 2 3 10...

Page 6: ...Register 168h offset 168h reset 0h 241 2 3 148 Register 169h offset 169h reset 0h 241 2 3 149 Register 16Ah offset 16Ah reset 0h 242 2 3 150 Register 16Ch offset 16Ch reset 0h 242 2 3 151 Register 16Dh offset 16Dh reset 0h 242 2 3 152 Register 16Eh offset 16Eh reset 0h 243 2 3 153 Register 170h offset 170h reset 0h 243 2 3 154 Register 171h offset 171h reset 0h 243 2 3 155 Register 172h offset 172...

Page 7: ...set 88h 268 2 4 11 Register 2Ah offset 2Ah reset Ah 268 2 4 12 Register 2Bh offset 2Bh reset 0h 269 2 4 13 Register 2Ch offset 2Ch reset 1h 269 2 4 14 Register 2Dh offset 2Dh reset 0h 270 2 4 15 Register 2Eh offset 2Eh reset 1h 270 2 4 16 Register 2Fh offset 2Fh reset 0h 270 2 4 17 Register 30h offset 30h reset 1h 271 2 4 18 Register 31h offset 31h reset 0h 271 2 4 19 Register 32h offset 32h reset...

Page 8: ... 285 2 4 64 Register 5Fh offset 5Fh reset 0h 286 2 4 65 Register 60h offset 60h reset 0h 286 2 4 66 Register 61h offset 61h reset 1h 286 2 4 67 Register 62h offset 62h reset 2h 287 2 4 68 Register 63h offset 63h reset 3h 287 2 4 69 Register 64h offset 64h reset Fh 287 2 4 70 Register 65h offset 65h reset 4h 287 2 4 71 Register 66h offset 66h reset 4h 288 2 4 72 Register 67h offset 67h reset 4h 288...

Page 9: ...2 4 117 Register 94h offset 94h reset 0h 304 2 4 118 Register 95h offset 95h reset 0h 304 2 4 119 Register 96h offset 96h reset 0h 305 2 4 120 Register 97h offset 97h reset 0h 305 2 4 121 Register 98h offset 98h reset 0h 305 2 4 122 Register 99h offset 99h reset 0h 307 2 4 123 Register 9Ah offset 9Ah reset 0h 308 2 4 124 Register 9Ch offset 9Ch reset 0h 308 2 4 125 Register 9Dh offset 9Dh reset 0h...

Page 10: ... 2 4 170 Register D2h offset D2h reset 0h 324 2 4 171 Register D3h offset D3h reset 0h 324 2 4 172 Register D4h offset D4h reset 0h 324 2 4 173 Register D5h offset D5h reset 0h 325 2 4 174 Register D6h offset D6h reset 0h 325 2 4 175 Register D7h offset D7h reset 0h 325 2 4 176 Register E8h offset E8h reset 0h 325 2 4 177 Register E9h offset E9h reset 0h 326 2 4 178 Register EAh offset EAh reset 0...

Page 11: ... Register 118h offset 118h reset 0h 350 2 4 224 Register 119h offset 119h reset 0h 350 2 4 225 Register 11Ah offset 11Ah reset 0h 351 2 4 226 Register 11Bh offset 11Bh reset 0h 351 2 4 227 Register 11Ch offset 11Ch reset 0h 352 2 4 228 Register 11Dh offset 11Dh reset 0h 352 2 4 229 Register 11Eh offset 11Eh reset 0h 353 2 4 230 Register 11Fh offset 11Fh reset 0h 354 2 4 231 Register 120h offset 12...

Page 12: ...set 27h reset Fh 377 2 5 8 Register 2Ch offset 2Ch reset 0h 377 2 5 9 Register 2Eh offset 2Eh reset 0h 378 2 5 10 Register 2Fh offset 2Fh reset 0h 378 2 5 11 Register 30h offset 30h reset 0h 379 2 5 12 Register 31h offset 31h reset 0h 379 2 5 13 Register 32h offset 32h reset 0h 380 2 5 14 Register 33h offset 33h reset 7h 380 2 5 15 Register 34h offset 34h reset 0h 381 2 5 16 Register 35h offset 35...

Page 13: ...0h 406 2 5 61 Register 69h offset 69h reset 88h 406 2 5 62 Register 6Ah offset 6Ah reset 88h 407 2 5 63 Register 6Ch offset 6Ch reset Fh 407 2 5 64 Register 6Dh offset 6Dh reset 7h 407 2 5 65 Register 6Eh offset 6Eh reset Fh 408 2 5 66 Register 6Fh offset 6Fh reset 2h 408 2 5 67 Register 74h offset 74h reset 0h 409 2 5 68 Register 75h offset 75h reset 0h 409 2 5 69 Register 76h offset 76h reset 0h...

Page 14: ... 114 Register A9h offset A9h reset 0h 424 2 5 115 Register AAh offset AAh reset 0h 425 2 5 116 Register ABh offset ABh reset Fh 425 2 5 117 Register ACh offset ACh reset 2Fh 425 2 5 118 Register ADh offset ADh reset 20h 426 2 5 119 Register AEh offset AEh reset 0h 426 2 5 120 Register AFh offset AFh reset 0h 426 2 5 121 Register B0h offset B0h reset 0h 426 2 5 122 Register B2h offset B2h reset 0h ...

Page 15: ... offset F9h reset 0h 442 2 5 168 Register FAh offset FAh reset 0h 443 2 5 169 Register FBh offset FBh reset 0h 443 2 5 170 Register FCh offset FCh reset 0h 443 2 5 171 Register FDh offset FDh reset 0h 444 2 5 172 Register FEh offset FEh reset 0h 444 2 5 173 Register FFh offset FFh reset 0h 444 2 5 174 Register 100h offset 100h reset 0h 445 2 5 175 Register 101h offset 101h reset 0h 445 2 5 176 Reg...

Page 16: ...h reset 0h 467 2 6 2 Register 4001h offset 4001h reset 10h 468 2 6 3 Register 4002h offset 4002h reset 8h 468 2 6 4 Register 4003h offset 4003h reset 0h 468 2 6 5 Register 4004h offset 4004h reset 20h 468 2 6 6 Register 4005h offset 4005h reset 60h 469 2 6 7 Register 4006h offset 4006h reset 66h 469 2 6 8 Register 4007h offset 4007h reset 7Bh 469 2 6 9 Register 4008h offset 4008h reset 0h 470 2 6 ...

Page 17: ...ister 4089h offset 4089h reset 0h 483 2 6 55 Register 408Eh offset 408Eh reset 24h 483 2 6 56 Register 408Fh offset 408Fh reset 1h 484 2 6 57 Register 4090h offset 4090h reset 92h 484 2 6 58 Register 4091h offset 4091h reset 9Bh 484 2 6 59 Register 4092h offset 4092h reset FFh 485 2 6 60 Register 4093h offset 4093h reset D6h 485 2 6 61 Register 4094h offset 4094h reset 60h 485 2 6 62 Register 4095...

Page 18: ... offset 487Ah reset 1h 500 2 6 108 Register 487Bh offset 487Bh reset 80h 500 2 6 109 Register 487Ch offset 487Ch reset 6h 500 2 6 110 Register 487Dh offset 487Dh reset 80h 500 2 6 111 Register 49CAh offset 49CAh reset 80h 501 2 6 112 Register 49CBh offset 49CBh reset 80h 501 2 6 113 Register 49CCh offset 49CCh reset 80h 501 2 6 114 Register 49CDh offset 49CDh reset 80h 501 2 6 115 Register 49D0h o...

Page 19: ...0 Register 7021h offset 7021h reset 0h 517 2 6 161 Register 7022h offset 7022h reset 0h 517 2 6 162 Register 7028h offset 7028h reset 0h 518 2 6 163 Register 7029h offset 7029h reset 0h 518 2 6 164 Register 702Ah offset 702Ah reset 0h 519 2 6 165 Register 702Bh offset 702Bh reset 0h 519 2 6 166 Register 702Ch offset 702Ch reset 0h 519 2 6 167 Register 702Dh offset 702Dh reset 0h 520 2 6 168 Regist...

Page 20: ...t 0h 535 2 7 4 Register 10Fh offset 10Fh reset 12h 535 2 7 5 Register 110h offset 110h reset 0h 535 2 7 6 Register 111h offset 111h reset 0h 535 2 7 7 Register 112h offset 112h reset 1h 536 2 7 8 Register 113h offset 113h reset 2h 536 2 7 9 Register 114h offset 114h reset 1h 536 2 7 10 Register 115h offset 115h reset 2h 537 2 8 Macro Register Map 538 2 8 1 Register A0h offset A0h reset 0h 541 2 8 ...

Page 21: ... 553 2 8 47 Register CEh offset CEh reset 0h 554 2 8 48 Register CFh offset CFh reset 0h 554 2 8 49 Register D0h offset D0h reset 0h 554 2 8 50 Register D1h offset D1h reset 0h 555 2 8 51 Register D2h offset D2h reset 0h 555 2 8 52 Register D3h offset D3h reset 0h 555 2 8 53 Register D4h offset D4h reset 0h 555 2 8 54 Register D5h offset D5h reset 0h 556 2 8 55 Register D6h offset D6h reset 0h 556...

Page 22: ...et 0h 569 2 8 101 Register 104h offset 104h reset 0h 570 2 8 102 Register 105h offset 105h reset 0h 570 2 8 103 Register 106h offset 106h reset 0h 570 2 8 104 Register 107h offset 107h reset 0h 570 2 8 105 Register 108h offset 108h reset 0h 571 2 8 106 Register 109h offset 109h reset 0h 571 2 8 107 Register 10Ah offset 10Ah reset 0h 571 2 8 108 Register 10Bh offset 10Bh reset 0h 572 2 8 109 Regist...

Page 23: ... Register 137h offset 137h reset 0h 584 2 8 153 Register 138h offset 138h reset 0h 584 2 8 154 Register 139h offset 139h reset 0h 585 2 8 155 Register 13Ah offset 13Ah reset 0h 585 2 8 156 Register 13Bh offset 13Bh reset 0h 585 2 8 157 Register 13Ch offset 13Ch reset 0h 586 2 8 158 Register 13Dh offset 13Dh reset 0h 586 2 8 159 Register 13Eh offset 13Eh reset 0h 586 2 8 160 Register 13Fh offset 13...

Page 24: ...ffset 130h reset 0h 602 2 10 30 Register 131h offset 131h reset 0h 603 2 10 31 Register 132h offset 132h reset 0h 603 2 10 32 Register 133h offset 133h reset 0h 603 2 10 33 Register 134h offset 134h reset 0h 603 2 10 34 Register 135h offset 135h reset 0h 604 2 10 35 Register 136h offset 136h reset 0h 604 2 10 36 Register 170h offset 170h reset 1h 604 2 10 37 Register 174h offset 174h reset 0h 605 ...

Page 25: ...et 0h 619 2 11 12 Register 112h offset 112h reset 0h 619 2 11 13 Register 113h offset 113h reset 0h 619 2 11 14 Register 114h offset 114h reset 0h 619 2 11 15 Register 115h offset 115h reset 0h 620 2 11 16 Register 116h offset 116h reset 0h 620 2 11 17 Register 117h offset 117h reset 0h 620 2 11 18 Register 118h offset 118h reset 0h 621 2 11 19 Register 119h offset 119h reset 0h 621 2 11 20 Regist...

Page 26: ... Register 131h offset 131h reset 0h 642 2 12 37 Register 142h offset 142h reset 0h 642 2 12 38 Register 200h offset 200h reset 0h 643 2 12 39 Register 201h offset 201h reset 0h 643 2 12 40 Register 202h offset 202h reset 0h 643 2 12 41 Register 203h offset 203h reset 0h 644 2 12 42 Register 204h offset 204h reset 0h 644 2 12 43 Register 205h offset 205h reset 0h 644 2 12 44 Register 206h offset 20...

Page 27: ...r 403h offset 403h reset 8h 659 2 12 90 Register 404h offset 404h reset 0h 659 2 12 91 Register 405h offset 405h reset 0h 660 2 12 92 Register 406h offset 406h reset 0h 660 2 12 93 Register 407h offset 407h reset 8h 660 2 12 94 Register 446h offset 446h reset 1h 661 2 12 95 Register 447h offset 447h reset 0h 661 2 12 96 Register 460h offset 460h reset 0h 661 2 12 97 Register 461h offset 461h reset...

Page 28: ... Register 54Ch offset 54Ch reset 0h 677 2 12 143 Register 54Dh offset 54Dh reset 0h 677 2 12 144 Register 54Eh offset 54Eh reset 1Bh 677 2 12 145 Register 54Fh offset 54Fh reset 6h 678 2 12 146 Register 550h offset 550h reset 0h 678 2 12 147 Register 554h offset 554h reset 0h 679 2 12 148 Register 555h offset 555h reset 0h 679 2 12 149 Register 556h offset 556h reset 0h 679 2 12 150 Register 557h ...

Page 29: ...ffset 597h reset 2Ch 695 2 12 195 Register 5A0h offset 5A0h reset 0h 696 2 12 196 Register 5A1h offset 5A1h reset 0h 696 2 12 197 Register 5A2h offset 5A2h reset 0h 696 2 12 198 Register 5A4h offset 5A4h reset 0h 697 2 12 199 Register 5A5h offset 5A5h reset 0h 697 2 12 200 Register 5A8h offset 5A8h reset 0h 697 2 12 201 Register 5A9h offset 5A9h reset 0h 697 2 12 202 Register 5AAh offset 5AAh rese...

Page 30: ... 147h offset 147h reset 2Dh 722 2 13 39 Register 188h offset 188h reset 5h 722 2 13 40 Register 1A0h offset 1A0h reset 0h 723 2 13 41 Register 1A1h offset 1A1h reset 0h 723 2 13 42 Register 1A2h offset 1A2h reset 0h 723 2 13 43 Register 1A3h offset 1A3h reset 0h 723 2 13 44 Register 1A4h offset 1A4h reset 0h 724 2 13 45 Register 1A5h offset 1A5h reset 0h 724 2 13 46 Register 1A6h offset 1A6h reset...

Page 31: ...424h offset 424h reset 9h 739 2 13 92 Register 425h offset 425h reset Fh 739 2 13 93 Register 428h offset 428h reset 0h 739 2 13 94 Register 429h offset 429h reset 0h 740 2 13 95 Register 42Ah offset 42Ah reset 40h 740 2 13 96 Register 42Ch offset 42Ch reset FAh 740 2 13 97 Register 42Dh offset 42Dh reset 3h 740 2 13 98 Register 430h offset 430h reset CBh 741 2 13 99 Register 431h offset 431h rese...

Page 32: ...ter 49Fh offset 49Fh reset 0h 755 2 13 145 Register 4A0h offset 4A0h reset 32h 755 2 13 146 Register 4A1h offset 4A1h reset 0h 755 2 13 147 Register 4A2h offset 4A2h reset 3Eh 755 2 13 148 Register 4A3h offset 4A3h reset 0h 756 2 13 149 Register 4A4h offset 4A4h reset 0h 756 2 13 150 Register 4A6h offset 4A6h reset 1h 756 2 13 151 Register 4A8h offset 4A8h reset 2h 757 2 13 152 Register 4A9h offse...

Page 33: ...Register 4D9h offset 4D9h reset 0h 771 2 13 198 Register 4DAh offset 4DAh reset 0h 771 2 13 199 Register 4DBh offset 4DBh reset 0h 771 2 13 200 Register 4DCh offset 4DCh reset 0h 772 2 13 201 Register 4DDh offset 4DDh reset 0h 772 2 13 202 Register 4DEh offset 4DEh reset 0h 772 2 13 203 Register 4DFh offset 4DFh reset 0h 772 2 13 204 Register 4E0h offset 4E0h reset 0h 773 2 13 205 Register 4E1h of...

Page 34: ...Register 50Eh offset 50Eh reset 0h 786 2 13 251 Register 50Fh offset 50Fh reset 0h 786 2 13 252 Register 510h offset 510h reset 0h 786 2 13 253 Register 511h offset 511h reset 0h 787 2 13 254 Register 512h offset 512h reset 0h 787 2 13 255 Register 513h offset 513h reset 0h 787 2 13 256 Register 514h offset 514h reset 0h 788 2 13 257 Register 515h offset 515h reset 0h 788 2 13 258 Register 516h of...

Page 35: ...Register 543h offset 543h reset 0h 801 2 13 304 Register 544h offset 544h reset 0h 801 2 13 305 Register 545h offset 545h reset 0h 802 2 13 306 Register 546h offset 546h reset 0h 802 2 13 307 Register 547h offset 547h reset 0h 802 2 13 308 Register 548h offset 548h reset 0h 802 2 13 309 Register 549h offset 549h reset 0h 803 2 13 310 Register 54Ah offset 54Ah reset 0h 803 2 13 311 Register 54Bh of...

Page 36: ...Register 578h offset 578h reset 0h 816 2 13 357 Register 579h offset 579h reset 0h 816 2 13 358 Register 57Ah offset 57Ah reset 0h 817 2 13 359 Register 57Bh offset 57Bh reset 0h 817 2 13 360 Register 57Ch offset 57Ch reset 0h 817 2 13 361 Register 57Dh offset 57Dh reset 0h 818 2 13 362 Register 57Eh offset 57Eh reset 0h 818 2 13 363 Register 57Fh offset 57Fh reset 0h 818 2 13 364 Register 580h of...

Page 37: ...Register 5ADh offset 5ADh reset 0h 831 2 13 410 Register 5AEh offset 5AEh reset 0h 832 2 13 411 Register 5AFh offset 5AFh reset 0h 832 2 13 412 Register 5B0h offset 5B0h reset 0h 832 2 13 413 Register 5B1h offset 5B1h reset 0h 832 2 13 414 Register 5B2h offset 5B2h reset 0h 833 2 13 415 Register 5B3h offset 5B3h reset 0h 833 2 13 416 Register 5B4h offset 5B4h reset 0h 833 2 13 417 Register 5B5h of...

Page 38: ...er 6A5h offset 6A5h reset 0h 848 2 13 462 Register 6D4h offset 6D4h reset 0h 849 2 13 463 Register 6D5h offset 6D5h reset 0h 849 2 13 464 Register 6D6h offset 6D6h reset 0h 849 2 13 465 Register 710h offset 710h reset 0h 850 2 13 466 Register 711h offset 711h reset 0h 850 2 13 467 Register 740h offset 740h reset 1h 850 2 13 468 Register 770h offset 770h reset 0h 851 2 13 469 Register 771h offset 7...

Page 39: ... offset 10Ch reset 0h 872 2 14 44 Register 10Dh offset 10Dh reset 0h 873 2 14 45 Register 10Eh offset 10Eh reset 0h 873 2 14 46 Register 140h offset 140h reset 0h 873 2 14 47 Register 141h offset 141h reset 0h 874 2 14 48 Register 142h offset 142h reset 0h 874 2 14 49 Register 143h offset 143h reset 2Dh 874 2 14 50 Register 144h offset 144h reset 0h 875 2 14 51 Register 145h offset 145h reset 0h 8...

Page 40: ...434h offset 434h reset 33h 889 2 14 97 Register 435h offset 435h reset 1h 890 2 14 98 Register 438h offset 438h reset 65h 890 2 14 99 Register 439h offset 439h reset Fh 890 2 14 100 Register 43Ch offset 43Ch reset 10h 890 2 14 101 Register 43Dh offset 43Dh reset 27h 891 2 14 102 Register 43Eh offset 43Eh reset 4h 891 2 14 103 Register 43Fh offset 43Fh reset Fh 891 2 14 104 Register 450h offset 450...

Page 41: ...4 149 Register 4BCh offset 4BCh reset 0h 906 2 14 150 Register 4BDh offset 4BDh reset 0h 906 2 14 151 Register 4BEh offset 4BEh reset 0h 906 2 14 152 Register 4BFh offset 4BFh reset 0h 907 2 14 153 Register 4C0h offset 4C0h reset 0h 907 2 14 154 Register 4C1h offset 4C1h reset 0h 907 2 14 155 Register 4C2h offset 4C2h reset 0h 907 2 14 156 Register 4C3h offset 4C3h reset 0h 908 2 14 157 Register 4...

Page 42: ...Register 4F1h offset 4F1h reset 0h 921 2 14 203 Register 4F2h offset 4F2h reset 0h 921 2 14 204 Register 4F3h offset 4F3h reset 0h 921 2 14 205 Register 4F4h offset 4F4h reset 0h 922 2 14 206 Register 4F5h offset 4F5h reset 0h 922 2 14 207 Register 4F6h offset 4F6h reset 0h 922 2 14 208 Register 4F7h offset 4F7h reset 0h 923 2 14 209 Register 4F8h offset 4F8h reset 0h 923 2 14 210 Register 4F9h of...

Page 43: ...Register 566h offset 566h reset 0h 936 2 14 256 Register 567h offset 567h reset 0h 936 2 14 257 Register 568h offset 568h reset 0h 937 2 14 258 Register 569h offset 569h reset 0h 937 2 14 259 Register 56Ah offset 56Ah reset 0h 937 2 14 260 Register 56Bh offset 56Bh reset 0h 937 2 14 261 Register 56Ch offset 56Ch reset 0h 938 2 14 262 Register 56Dh offset 56Dh reset 0h 938 2 14 263 Register 56Eh of...

Page 44: ... 640h reset 0h 953 2 14 308 Register 641h offset 641h reset 0h 953 2 14 309 Register 642h offset 642h reset 8h 953 2 14 310 Register 644h offset 644h reset 0h 954 2 14 311 Register 645h offset 645h reset 0h 954 2 14 312 Register 648h offset 648h reset 0h 954 2 14 313 Register 649h offset 649h reset 1h 955 2 14 314 Register 64Ah offset 64Ah reset 0h 955 2 14 315 Register 64Ch offset 64Ch reset 0h 9...

Page 45: ...970 2 15 36 Register ADh offset ADh reset 0h 970 2 15 37 Register AEh offset AEh reset 0h 971 2 15 38 Register B0h offset B0h reset 0h 971 2 15 39 Register B1h offset B1h reset 0h 971 2 15 40 Register B2h offset B2h reset 0h 972 2 15 41 Register B3h offset B3h reset 0h 972 2 15 42 Register B5h offset B5h reset 0h 972 2 15 43 Register B6h offset B6h reset 0h 972 2 15 44 Register B8h offset B8h rese...

Page 46: ...egister 229h offset 229h reset 2h 1007 2 16 33 Register 22Ah offset 22Ah reset 0h 1007 2 16 34 Register 22Ch offset 22Ch reset 1h 1008 2 16 35 Register 22Dh offset 22Dh reset 2h 1008 2 16 36 Register 22Eh offset 22Eh reset 0h 1008 2 16 37 Register 230h offset 230h reset 1h 1008 2 16 38 Register 231h offset 231h reset 2h 1009 2 16 39 Register 232h offset 232h reset 0h 1009 2 16 40 Register 234h off...

Page 47: ... 270h offset 270h reset 1h 1022 2 16 86 Register 271h offset 271h reset 2h 1022 2 16 87 Register 272h offset 272h reset 0h 1023 2 16 88 Register 274h offset 274h reset 1h 1023 2 16 89 Register 275h offset 275h reset 2h 1023 2 16 90 Register 276h offset 276h reset 0h 1024 2 16 91 Register 278h offset 278h reset 1h 1024 2 16 92 Register 279h offset 279h reset 2h 1024 2 16 93 Register 27Ah offset 27A...

Page 48: ...ister 2B6h offset 2B6h reset 0h 1037 2 16 139 Register 2B8h offset 2B8h reset 1h 1038 2 16 140 Register 2B9h offset 2B9h reset 2h 1038 2 16 141 Register 2BAh offset 2BAh reset 0h 1038 2 16 142 Register 2BCh offset 2BCh reset 1h 1038 2 16 143 Register 2BDh offset 2BDh reset 2h 1039 2 16 144 Register 2BEh offset 2BEh reset 0h 1039 2 16 145 Register 2C0h offset 2C0h reset 1h 1039 2 16 146 Register 2C...

Page 49: ...ister 2FDh offset 2FDh reset 2h 1052 2 16 192 Register 2FEh offset 2FEh reset 0h 1053 2 16 193 Register 300h offset 300h reset 1h 1053 2 16 194 Register 301h offset 301h reset 2h 1053 2 16 195 Register 302h offset 302h reset 0h 1054 2 16 196 Register 304h offset 304h reset 1h 1054 2 16 197 Register 305h offset 305h reset 2h 1054 2 16 198 Register 306h offset 306h reset 0h 1054 2 16 199 Register 30...

Page 50: ...ister 407h offset 407h reset 0h 1068 2 16 245 Register 408h offset 408h reset 1h 1068 2 16 246 Register 40Bh offset 40Bh reset 0h 1069 2 16 247 Register 40Ch offset 40Ch reset 1h 1069 2 16 248 Register 40Fh offset 40Fh reset 0h 1069 2 16 249 Register 410h offset 410h reset 1h 1070 2 16 250 Register 413h offset 413h reset 0h 1070 2 16 251 Register 414h offset 414h reset 1h 1071 2 16 252 Register 41...

Page 51: ...ister 470h offset 470h reset 1h 1089 2 16 298 Register 473h offset 473h reset 0h 1089 2 16 299 Register 474h offset 474h reset 1h 1090 2 16 300 Register 477h offset 477h reset 0h 1090 2 16 301 Register 478h offset 478h reset 1h 1091 2 16 302 Register 47Bh offset 47Bh reset 0h 1091 2 16 303 Register 47Ch offset 47Ch reset 1h 1091 2 16 304 Register 47Fh offset 47Fh reset 0h 1092 2 16 305 Register 48...

Page 52: ...ister 4DBh offset 4DBh reset 0h 1110 2 16 351 Register 4DCh offset 4DCh reset 1h 1111 2 16 352 Register 4DFh offset 4DFh reset 0h 1111 2 16 353 Register 4E0h offset 4E0h reset 1h 1111 2 16 354 Register 4E3h offset 4E3h reset 0h 1112 2 16 355 Register 4E4h offset 4E4h reset 1h 1112 2 16 356 Register 4E7h offset 4E7h reset 0h 1113 2 16 357 Register 4E8h offset 4E8h reset 1h 1113 2 16 358 Register 4E...

Page 53: ...ister 704h offset 704h reset 0h 1131 2 16 404 Register 705h offset 705h reset 2h 1132 2 16 405 Register 708h offset 708h reset 0h 1132 2 16 406 Register 709h offset 709h reset 2h 1132 2 16 407 Register 70Ch offset 70Ch reset 0h 1133 2 16 408 Register 70Dh offset 70Dh reset 2h 1133 2 16 409 Register 800h offset 800h reset 0h 1133 2 16 410 Register 801h offset 801h reset 2h 1134 2 16 411 Register 80...

Page 54: ...ister 86Dh offset 86Dh reset 2h 1149 2 16 457 Register 870h offset 870h reset 0h 1149 2 16 458 Register 871h offset 871h reset 2h 1150 2 16 459 Register 874h offset 874h reset 0h 1150 2 16 460 Register 875h offset 875h reset 2h 1150 2 16 461 Register 878h offset 878h reset 0h 1151 2 16 462 Register 879h offset 879h reset 2h 1151 2 16 463 Register 87Ch offset 87Ch reset 0h 1151 2 16 464 Register 87...

Page 55: ...ister 958h offset 958h reset 0h 1167 2 16 510 Register 959h offset 959h reset 2h 1167 2 16 511 Register 95Ch offset 95Ch reset 0h 1167 2 16 512 Register 95Dh offset 95Dh reset 2h 1168 2 16 513 Register 960h offset 960h reset 0h 1168 2 16 514 Register 961h offset 961h reset 2h 1168 2 16 515 Register 9CCh offset 9CCh reset 0h 1169 2 16 516 Register 9CDh offset 9CDh reset 2h 1169 2 16 517 Register 9D...

Page 56: ...eset 2h 1185 2 16 563 Register A44h offset A44h reset 0h 1185 2 16 564 Register A45h offset A45h reset 2h 1185 2 16 565 Register A48h offset A48h reset 0h 1186 2 16 566 Register A49h offset A49h reset 2h 1186 2 16 567 Register F00h offset F00h reset 0h 1186 2 16 568 Register 1004h offset 1004h reset 0h 1187 2 16 569 Register 1005h offset 1005h reset 2h 1187 2 16 570 Register 1008h offset 1008h res...

Page 57: ...0F5h offset 10F5h reset 2h 1202 2 16 616 Register 11A4h offset 11A4h reset 0h 1203 2 16 617 Register 11A5h offset 11A5h reset 2h 1203 2 16 618 Register 11A8h offset 11A8h reset 0h 1203 2 16 619 Register 11A9h offset 11A9h reset 2h 1204 2 16 620 Register 11ACh offset 11ACh reset 0h 1204 2 16 621 Register 11ADh offset 11ADh reset 2h 1204 2 16 622 Register 11B0h offset 11B0h reset 0h 1205 2 16 623 Re...

Page 58: ...458h offset 1458h reset 0h 1219 2 16 669 Register 17D0h offset 17D0h reset 0h 1219 2 16 670 Register 17D1h offset 17D1h reset 0h 1220 2 16 671 Register 17D6h offset 17D6h reset 0h 1220 2 16 672 Register 17D7h offset 17D7h reset 0h 1220 2 16 673 Register 17D8h offset 17D8h reset 0h 1221 2 16 674 Register 17D9h offset 17D9h reset 0h 1221 2 16 675 Register 17DAh offset 17DAh reset 0h 1221 2 16 676 Re...

Page 59: ...80Ch offset 180Ch reset 0h 1236 2 16 722 Register 180Dh offset 180Dh reset 0h 1237 2 16 723 Register 180Eh offset 180Eh reset 0h 1237 2 16 724 Register 180Fh offset 180Fh reset 0h 1237 2 16 725 Register 1810h offset 1810h reset 0h 1238 2 16 726 Register 1811h offset 1811h reset 0h 1238 2 16 727 Register 1812h offset 1812h reset 0h 1238 2 16 728 Register 1813h offset 1813h reset 0h 1239 2 16 729 Re...

Page 60: ...845h offset 1845h reset 0h 1254 2 16 775 Register 1846h offset 1846h reset 0h 1254 2 16 776 Register 1847h offset 1847h reset 0h 1254 2 16 777 Register 1848h offset 1848h reset 0h 1254 2 16 778 Register 1849h offset 1849h reset 0h 1255 2 16 779 Register 184Ah offset 184Ah reset 0h 1255 2 16 780 Register 184Bh offset 184Bh reset 0h 1255 2 16 781 Register 184Ch offset 184Ch reset 0h 1256 2 16 782 Re...

Page 61: ...Register 1881h offset 1881h reset 0h 1263 2 16 806 Register 1882h offset 1882h reset 0h 1263 2 16 807 Register 1883h offset 1883h reset 0h 1263 2 16 808 Register 1884h offset 1884h reset 0h 1264 2 16 809 Register 1885h offset 1885h reset 0h 1264 2 16 810 Register 1886h offset 1886h reset 0h 1264 2 16 811 Register 1887h offset 1887h reset 0h 1264 A Appendix SPI Interface 1266 ...

Page 62: ...www ti com 62 SBAU337 May 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated Contents ...

Page 63: ...History 63 SBAU337 May 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated Contents Revision History NOTE Page numbers for previous revisions may differ from page numbers in the current version ...

Page 64: ...in AGC Internal AGC Controller Configuration Macro section Changed the description below the table in AGC Internal AGC Controller Configuration Macro section Changed the Opcode from 0x60 to 0x5F in AGC Min Max DSA Attenuation Configuration Macro section Added description to AGC Customer RF Macro section Added description to AGC External LNA Gain Control Configuration Macro section Added descriptio...

Page 65: ...cumentation Feedback Copyright 2020 Texas Instruments Incorporated Revision History DATE REVISION NOTES Added Update TX Channel Frequency Set Single Band section Added TX TONE generator Configuration section Added AGC External DVGA Configuration Macro section ...

Page 66: ...es for simple configurations and register writes to initiate macros Macro commands abstract out the internal device configuration sequence to a simple set of configuration and simplify the host interaction They reduce complex configurations into simple writes avoid computation complexity on the host side and provide simple status information in response This document describes the Macro Interface ...

Page 67: ...ons and thus simplify the host interaction Macro commands are triggered via regular register writes to AFE79xx through SPI The AFE79xx is always a slave on the SPI and the Host is the master on the SPI This document describes the Macro Interface protocol and lists the commands along with their functionality 1 1 1 Macro Interface Protocol The Macro execution has two phases Macro command initiation ...

Page 68: ...pcode register serves two purposes initiate a trigger to the AFE79xx controller and also indicate the Macro command to be executed This trigger step is mandatory and has to be the last step in the Macro initiation Since the second step triggers an interrupt to the microcontroller the parameters mentioned in the first step need to be programmed before triggering the Macro command The acknowledgment...

Page 69: ...SBAU337 May 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated Macro Figure 1 2 Macro Interface data memory and control register The Macro Opcode register Trigger operand registers and the Macro Memory is available on SPI write and read path Thus to initiate the Macro a series of SPI registers need to be written Eg 1 Select Customer Macro Interface page in SPI page se...

Page 70: ...and 3 Addr OPCODE_BA OPCODE SPI READ_DATA Addr STATUS_BA READ_DATA Repeat till READ_DATA 0x1 1 Addr STATUS_BA READ_DATA Repeat till READ_DATA 0x1 1 SPI ADDR 0xF0 SPI READ_DATA Read results Host AFE Design Details www ti com 70 SBAU337 May 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated Macro Figure 1 4 Interaction between Host and AFE79xx Polling method ...

Page 71: ...OPERAND_BA Read results v Œu D Œ Z Ç_ Next Macro Confirm READ_DATA 0x1 1 www ti com Design Details 71 SBAU337 May 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated Macro Figure 1 5 Interaction between Host and AFE79xx Macro Interrupt method To initiate Macro with large data transfer mode the following sequence is recommended 1 Activate SPI page for Macro Memory 2 Wri...

Page 72: ... 2 DATA N 1 Addr MACRO_MEM_BA Burst Mode Address MACRO_MEM_BA Data 0 Data 1 Data 2 Data 3 N 2 N 1 Address OPCODE_BA SPI Page Change Customer Base address of Status Registers Base address of Opcode Base address of Operand Base address of Macro Memory Legend Design Details www ti com 72 SBAU337 May 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated Macro Figure 1 6 SPI ...

Page 73: ...0 Addr MACRO_ MEM_BA DATA 1 DATA 2 DATA N 1 Burst write SPI ADDR 0x20 SPI Page Change SPI DATA DATA 0 SPI DATA DATA 0 SPI DATA DATA 0 SPI DATA DATA 0 Addr STATUS_BA Addr STATUS_BA Addr OPCODE_BA Addr OPERAND_BA SPI Page Change to Customer Page SPI Page Change Customer Host AFE www ti com Design Details 73 SBAU337 May 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated ...

Page 74: ...A 2 DATA N 1 SPI ADDR 0x20 SPI Page Change Macro Mem SPI DATA DATA 0 SPI DATA DATA 0 SPI DATA DATA 0 SPI DATA DATA 0 Addr STATUS_BA Addr STATUS_BA Addr OPCODE_BA Addr OPERAND_BA SPI Page Change SPI Page Change Customer Host AFE v Œu D Œ Z Ç_ Next Macro Read results Confirm READ_DATA 0x1 1 Design Details www ti com 74 SBAU337 May 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments I...

Page 75: ...tus fields and information to help debug Error Status Extended Error code In addition to this 18 x 32 bit registers Macro Result are allocated for results and contain the results from the Macros Each of these registers is 32 bits in length and hence corresponds to 4 SPI reads explicit addressed mode or burst mode Figure 1 9 Fields within Macro Status Registers 1 1 1 4 2 Macro Execution Status The ...

Page 76: ...Value of 1 indicates that MACRO_ERROR was set due to a MACRO_OPCODE that is not allowed in the current state of the device Bit 2 Value of 1 indicates that MACRO_ERROR was set due to errors in the operands of the macro command More information on the nature of operand error is present in subsequent fields Bit 3 Value of 1 indicates that MACRO_ERROR was set due to an error in the execution of the ma...

Page 77: ... and 2FB The term Channel means a logical data stream having data pertaining to a specific system function with the system functions being TX RX and FB In certain device configurations it is possible for two channels to use the same physical signal chain or at least part of it E g in TDD modes the RX and FB channels can time share the same ADC Macro commands will typically take channel parameters ...

Page 78: ...O Set 0x32 FB Channel Frequency NCO Set 0x33 RX FB Nyquist Band Configuration 0x34 TX Nyquist Band Configuration 0x36 Tune System 0x37 Update TX Channel Frequency Set Single Band 0x38 Update RX Channel Frequency Set 0x39 Update FB Channel Frequency Set 0x3E Update TX Channel Frequency Set Dual Band 0x41 RX DSA Gain Phase Factory Calibration Macro 0x42 TX DSA Gain Phase Factory Calibration Macro 0x...

Page 79: ...e and will be initiated upon System Initialization See Section 1 2 2 1 2 1 1 System Channel Configuration This macro specifies the RX FB and TX channel enables for the entire system The AFE79XX supports up to 4 TX RX channels and up to 2 FB channels Table 1 3 System Channel Configuration Macro System Chain configuration Opcode 0x21 Operand Offset Length Value Functionality Results 1 0x00 1 Enable ...

Page 80: ... Enable argument Error Code 2 32 bit Not Used 1 2 1 2 ADC Select Configuration This macro specifies the ADC which is to be used for system FB and RX channels AFE79XX supports sharing of the same ADC for RX and FB channel in TDD mode but not otherwise The device supports 6 ADCs referred to as ADC1 to ADC6 Table 1 5 Macro ADC Select configuration Opcode 0x20 Operand Offset Length Value Functionality...

Page 81: ...o specifies whether the device is to operate in FDD mode or TDD mode Each half Core12 and Core34 is independently configurable Note that only in TDD mode do we allow sharing of ADC between RX and FB channels Table 1 6 5 2 2 TDD FDD Configuration Macro TDD FDD Configuration Opcode 0x22 Operand Offset Length Value Functionality Results 1 0x00 1 0x03 FDD for Core12 and Core34 0x01 FDD for Core12 and ...

Page 82: ...4 1 Value specified in operand 2 is valid for 1TX Bit 5 1 Value specified in operand 2 is valid for 2TX Bit 6 1 Value specified in operand 2 is valid for 3TX Bit 7 1 Value specified in operand 2 is valid for 4TX 2 0x01 1 Number of Bands 1 Single Band 2 Dual Band 2 RESERVED Memory Not used 1 2 1 4 1 Error Reporting Table 1 9 lists the error conditions associated with this macro Table 1 9 Error Stat...

Page 83: ...e is given below x 61 44 MHz 0 1x 61 44 MHz 1 1 5x 92 16 MHz 2 2x 122 88 MHz 3 3x 184 32 MHz 4 4x 245 76 MHz 5 6x 368 64 MHz 6 8x 491 52 MHz 7 12x 737 28 MHz 8 16x 983 04 MHz 9 24x 1474 56 MHz 9 RESERVED Memory Not used 1 2 1 5 1 Error Reporting Table 1 11 lists the error conditions associated with this macro Table 1 11 Error Status Registers Interpretation Error Code 1 16 bit Bit 0 1 Invalid RX I...

Page 84: ... MHz 4 4x 245 76 MHz 5 6x 368 64 MHz 6 8x 491 52 MHz 7 12x 737 28 MHz 8 16x 983 04 MHz 9 24x 1474 56 MHz 9 RESERVED Memory Not used 1 2 1 6 1 Error Reporting Table 1 13 lists the error conditions associated with this macro Table 1 13 Error Status Registers Interpretation Error Code 1 16 bit Bit 0 1 Invalid FB Interface Rate Validity argument Bit 1 1 Invalid Interface Rate Index argument Error Code...

Page 85: ...4 MHz 0 RESERVED 1 RESERVED 2 2x 122 88 MHz 3 3x 184 32 MHz 4 4x 245 76 MHz 5 6x 368 64 MHz 6 8x 491 52 MHz 7 12x 737 28 MHz 8 16x 983 04 MHz 9 24x 1474 56 MHz 10 32x 1966 08 MHz 11 48x 2949 12 MHz 11 RESERVED Memory Not used 1 2 1 7 1 Error Reporting Table 1 15 lists the error conditions associated with this macro Table 1 15 Error Status Registers Interpretation Error Code 1 16 bit Bit 0 1 Invali...

Page 86: ...5 36x 2211 84 MHz 6 40x 2457 6 MHz 7 48x 2949 12 MHz 7 RESERVED Memory Not used 1 2 1 8 1 Error Reporting Table 1 17 lists the error conditions associated with this macro Table 1 17 Error Status Registers Interpretation Error Code 1 16 bit Bit 0 1 Invalid RX ADC Rate Validity argument Bit 1 1 Invalid ADC Rate Index argument Error Code 2 32 bit Not Used 1 2 1 9 FB ADC Rate configuration This macro ...

Page 87: ...28 8 MHz 3 24x 1474 56 MHz 4 32x 1966 08 MHz 5 36x 2211 84 MHz 6 40x 2457 6 MHz 7 48x 2949 12 MHz 7 RESERVED Memory Not used 1 2 1 9 1 Error Reporting Table 1 19 lists the error conditions associated with this macro Table 1 19 Error Status Registers Interpretation Error Code 1 16 bit Bit 0 1 Invalid FB ADC Rate Validity argument Bit 1 1 Invalid ADC Rate Index argument Error Code 2 32 bit Not Used ...

Page 88: ...7 RESERVED Memory Not used 1 2 1 10 1 Error Reporting Table 1 21 lists the error conditions associated with this macro Table 1 21 Error Status Registers Interpretation Error Code 1 16 bit Bit 0 1 Invalid TX DAC Rate Validity argument Bit 1 1 Invalid DAC Rate Index argument Error Code 2 32 bit Not Used 1 2 1 11 Channel Frequency NCO Resolution This macro specifies the resolution of the frequency va...

Page 89: ...d as NCO 1 and NCO 2 NCO Numerically controlled Oscillator The unit of the frequency value specified in the macro is determined by the Channel Frequency Resolution macro hence the resolution supported by this interface is either 1000 Hz or TX DAC RATE 232 To specify a frequency in the first Nyquist zone the frequency value should be lower than TX DAC RATE 2 To specify a frequency in the second Nyq...

Page 90: ...DAC RATE is only allowed 5 0x0A 4 Frequency Value TX Channel frequency for NCO 2 Band 1 in specified resolution In case of 1 kHz resolution mode value of up to TX DAC RATE is only allowed 6 0x0E 4 Frequency Value TX Channel frequency for NCO 2 Band 2 in specified resolution In case of 1 kHz resolution mode value of up to TX DAC RATE is only allowed Memory Not used 1 2 1 12 1 Error Reporting Table ...

Page 91: ... zone of the target channel frequency should be specified through the RX FB Nyquist Zone Configuration Macro Table 1 26 Macro RX Channel frequency set Opcode 0x31 Operand Offset Length Value Functionality Results 1 0x00 1 Validity RX Channel Frequency validity Bit 0 1 Channel Frequency value is applicable to 1RX Bit 1 1 Channel Frequency value is applicable to 2RX Bit 2 1 Channel Frequency value i...

Page 92: ...nvalid second Frequency Value argument Bit 4 1 Invalid third Frequency Value argument Bit 5 1 Invalid fourth Frequency Value argument Error Code 2 32 bit Not Used 1 2 1 14 FB Channel Frequency Set This Macro specifies the channel frequencies or carrier frequencies for the FB channels It allows configuration of up to four frequencies for each channel These are designated as NCO 1 NCO 2 NCO 3 and NC...

Page 93: ...ncy for NCO 1 in specified resolution In case of 1 kHz resolution mode value of up to FB ADC RATE is only allowed 4 0x06 4 Frequency Value FB Channel frequency for NCO 2 in specified resolution In case of 1 kHz resolution mode value of up to FB ADC RATE is only allowed 5 0x0A 4 Frequency Value FB Channel frequency for NCO 3 in specified resolution In case of 1 kHz resolution mode value of up to FB...

Page 94: ...pcode 0x33 Operand Offset Length Value Functionality Results 1 0x00 1 Validity RX FB Channel Nyquist validity Bit 0 1 Nyquist Zone Index value is applicable to 1RX Bit 1 1 Nyquist Zone Index value is applicable to 2RX Bit 2 1 Nyquist Zone Index value is applicable to 3RX Bit 3 1 Nyquist Zone Index value is applicable to 4RX Bit 4 1 Nyquist Zone Index value is applicable to 1FB Bit 5 1 Nyquist Zone...

Page 95: ...TX 2 0x01 1 Value Nyquist Band Index for all the enabled channels in operand 1 0 RESERVED 1 Nyquist Zone 1 2 Nyquist Zone 2 2 RESERVED Memory Not used 1 2 1 16 1 Error Reporting Table 1 33 lists the error conditions associated with this macro Table 1 33 Error Status Registers Interpretation Error Code 1 16 bit Bit 0 1 Invalid Channel Validity argument Bit 1 1 Unsupported Nyquist zone Error Code 2 ...

Page 96: ...ode value of up to TX DAC RATE is only allowed 5 0x0D 4 Frequency Value TX Channel frequency for NCO 2 Band 2 in specified resolution In case of 1 kHz resolution mode value of up to TX DAC RATE is only allowed Memory Not used 1 2 1 17 1 Error Reporting Table 1 35 lists the error conditions associated with this macro Table 1 35 Error Status Registers Interpretation Error Code 1 16 bit RESERVED Erro...

Page 97: ...SERVED Write 1 here Memory Not used 1 2 1 18 1 Error Reporting Table 1 37 lists the error conditions associated with this macro Table 1 37 Error Status Registers Interpretation Error Code 1 16 bit Bit 0 1 Invalid TX Channel Select argument Bit 1 1 Invalid NCO Select argument Bit 2 1 Invalid Frequency Value argument or one of selected TX Channel is disabled Error Code 2 32 bit Not Used 1 2 1 19 Upd...

Page 98: ...ed 1 2 1 19 1 Error Reporting Table 1 39 lists the error conditions associated with this macro Table 1 39 Error Status Registers Interpretation Error Code 1 16 bit Bit 0 1 Invalid RX Channel Select argument Bit 1 1 Invalid NCO Select argument Bit 2 1 Invalid Frequency Value argument Error Code 2 32 bit Not Used 1 2 1 20 Update FB Channel Frequency Set This macro can be used to update channel frequ...

Page 99: ... Used 1 2 2 System Initialization 1 2 2 1 Tune System This Macro will setup the entire device as per the settings configured through the Section 1 2 1 macros Hence this macro command should be issued only after all the system configuration macros e g interface rate channel frequency set data converter rate are issued Table 1 42 Macro Tune System Opcode 0x36 Operand Offset Length Value Functionalit...

Page 100: ... Bit 3 1 ADC Rate Interface Rate Combination for 2FB is not supported If TX DUC Configuration is in error Bit 3 0 RESERVED Bit 4 1 Configuration requested for 1TX is not supported Bit 5 1 Configuration requested for 2TX is not supported Bit 6 1 Configuration requested for 3TX is not supported Bit 7 1 Configuration requested for 4TX is not supported Bit 31 8 Reserved 1 2 2 2 Apply DSA Gain Phase Co...

Page 101: ...riggers the DSA gain phase calibration sequence for RX channels in AFE79XX This should be called after the system tune is done Table 1 47 Macro RX DSA Gain Phase Factory Calibration Opcode 0x41 Operand Offset Length Value Functionality Results 1 0x00 1 Calib Cmd Calibration Command 0 Terminate Factory Calibration Causes the RX DSA calibration algorithm to stop DSA control is restored to the pre ca...

Page 102: ... 4RX Calibration Bits 7 4 RESERVED Used during Continue and Perform Clock Configuration calibration commands 6 0x05 1 Band Selection Band Selection for Rx Bit 1 0 Bands to be enabled for 1RX LSB is for Band1 and MSB is for Band2 Bits 3 2 Bands to be enabled for 2RX Bits 5 4 Bands to be enabled for 3RX Bits 7 6 Bands to be enabled for 4RX Used only during continue calibration command 7 0x06 1 RESER...

Page 103: ...cated by using 3 bits in the 32 bit error code The value mappings are 1 Signal power is low 3 High spur in input signal 4 Signal not in band Other Values are RESERVED Bit 3 1 Large Phase Error encountered across Codes Other bits are RESERVED Error Code 2 32 bit Bit 2 0 Contains information about the first error condition in the above 16 bit register Example Bit 1 of above register is set these 3 b...

Page 104: ...he length of the packet in bytes is reported in MACRO_RESULT_ REG1 2 0x01 1 RESERVED Write 0 here 3 0x02 1 Channel Selection TX Channel Selection Bit 0 1 Do 1TX Calib Bit 1 1 Do 2TX Calib Bit 2 1 Do 3TX Calib Bit 3 1 Do 4TX Calib Only used during continue calibration command 4 0x03 1 FB Channel Selection FB Channel Selection Bit 0 Index of FB to be used for 1TX 0 1FB 1 2FB Bit 1 Index of FB to be ...

Page 105: ...etation Error Code 1 16 bit Bit 0 1 RESERVED Bit 1 1 Error in Calibration Data Capture The nature of data capture error is indicated by using 3 bits in the 32 bit error code The value mappings are 3 No Valid Capture 5 Poor SNR in signal 6 Signal Frequency is not fixed Other Values are RESERVED Bit 2 1 Error in Input Signal Integrity The nature of Input signal integrity error is indicated by using ...

Page 106: ...tion and apply the new tone configuration for the selected channel 2 Apply new tone configuration only 3 RESERVED 4 Restore saved configuration 3 0x02 1 RESERVED Write 0 here 4 0x03 4 Tone Frequency Transmit tone frequency The value specified here is the tone frequency with units being determined based on the Channel Frequency Resolution Macro In case of 1 kHz resolution mode value of up to TX DAC...

Page 107: ... TX12 Channel configuration and configure tone for 1TX Note that configuration save happens on entire TX side that is TX12 or TX34 even if the tone is to be sent out of a single TX Channel Table 1 53 Operand Value Comments 1 0x00 Set TX Channel as 1TX 2 0x01 Save current 1TX and 2TX configuration and apply new configuration for 1TX Note that configuration save always happens on a pair of TX Channe...

Page 108: ...lect 0x0 Select TX from TX12 0x1 Select TX from TX34 2 0x01 1 Attenuation Validity 4 bit field Bit 0 1 Attenuation Setting A0 is valid Bit 1 1 Attenuation Setting A1 is valid Bit 2 1 Attenuation Setting A2 is valid Bit 3 1 Attenuation Setting A3 is valid 3 0x02 2 Attenuation A0 Attenuation value in steps of 0 125 dB for Band1 of the first TX in the selected TX side e g if TX Side Select is 0 this ...

Page 109: ...eps of 0 125 dB for Band2 of the second TX in the selected TX side e g if TX Side Select is 0 this corresponds to 2TX E g field value of 10 implies 1 25 dB attenuation Attenuation 39 dB is NOT allowed Memory Not Used 1 2 4 1 1 Error Reporting Following table lists the error conditions associated with this macro Table 1 57 Error Status Registers Interpretation Error Code 1 16 bit 0 NO_ERROR 1 INVAL...

Page 110: ... Field Bit 0 Big step attack detector enable Bit 1 Small step attack detector enable Bit 2 Big step decay detector enable Bit 3 Small step decay detector enable Bit 4 Power attack detector enable Bit 5 Power decay detector enable In all cases 0 Disable 1 Enable 3 0x02 1 Detector Threshold Big Step Attack Threshold with resolution of 0 25 dB 4 0x03 1 Detector Threshold Small Step Attack Threshold w...

Page 111: ...k detector threshold 2 Small step attack detector threshold 3 Big step decay detector threshold 4 Small step decay detector threshold 5 Power detector attack threshold 6 Power detector decay threshold 1 2 5 2 AGC Detector Time Constant Macro Table 1 59 Macro AGC Detector Time Constant Opcode 0x59 Operand Offset Length Value Functionality Results 1 0x00 1 RX Channel Select Bit 0 1 Value specified i...

Page 112: ...ast attack will be used for the LNA RF Detector The same value that is programmed for the slow attack will be used for the band detector in attack Mode if enabled For the decay time constants there is a single value that can be given through this macro and this value will be used for all the decay detectors that are enabled 1 2 5 3 AGC Digital Detector Relative Time Crossing Macro Table 1 60 Macro...

Page 113: ... that is programmed here is interpreted as fraction of samples crossing signal threshold in given time constant that is assumed to be programmed already So this macro should be given only after the time constant setting macro is given This Fraction is interpreted as a 16 bit precision value with the value 216 corresponding to 100 In every time period the attack detectors will trigger if the signal...

Page 114: ...etector to declare attack Time constant is given in number of samples User has to calculate the number of samples within time constant Total number of samples ADC_Rate Time_Constant in s 8 3 0x04 3 Number of samples at FADC 8 for Small Step Attack detector to declare attack 4 0x07 3 Number of samples at FADC 8 for Big Step Decay detector to declare decay 5 0x0A 3 Number of samples at FADC 8 for Sm...

Page 115: ...perands is valid for 4RX Bit 4 RESERVED Bit 5 RESERVED 2 0x01 2 Pin0Sel Sent on LSB of I See SBAA417 configuration document for more details 3 0x03 2 Pin1Sel Sent on LSB of Q 4 0x05 2 Pin2Sel Sent on penultimate LSB of I 5 0x07 2 Pin3Sel Sent on penultimate LSB of Q 6 0x09 1 Peak detector info on LSBs or Pins 0x00 Pins 0x01 LSBs and Pins 7 0x0A 1 Pulse Expansion Count This value here is in steps o...

Page 116: ...rigger should be held 1 2 5 6 AGC Detectors reset by GPIO Control Macro Table 1 64 Macro AGC Detectors reset by GPIO Control Opcode 0x5D Operand Offset Length Value Functionality Results 1 0x00 1 RX Channel Select Bit 0 1 Value specified in subsequent operands is valid for 1RX Bit 1 1 Value specified in subsequent operands is valid for 2RX Bit 2 1 Value specified in subsequent operands is valid fo...

Page 117: ...subsequent operands is valid for 4RX Bit 4 RESERVED Bit 5 RESERVED 2 0x01 1 TDD Freeze Mode 3 0x02 2 Blanking Time when an External Component Gain Changes See Blanking time for external component Gain change below this table 4 0x04 1 Pin based AGC freeze enable 0x00 Disable pin based AGC Freeze 0x01 Enable pin based AGC Freeze 5 0x05 1 Ext LNA or Ext DVGA Control 0x00 Neither of the controls are a...

Page 118: ...enuation Configuration Macro Table 1 66 Macro AGC Min Max DSA Attenuation Configuration Opcode 0x5F Operand Offset Length Value Functionality Results 1 0x00 1 RX Channel Select Bit 0 1 Value specified in subsequent operands is valid for 1RX Bit 1 1 Value specified in subsequent operands is valid for 2RX Bit 2 1 Value specified in subsequent operands is valid for 3RX Bit 3 1 Value specified in subs...

Page 119: ... 1 Value specified in subsequent operands is valid for 3RX Bit 3 1 Value specified in subsequent operands is valid for 4RX Bit 4 RESERVED Bit 5 RESERVED 2 0x01 1 DVGA Minimum Attenuation 1 LSB 0 5 dB 3 0x02 1 DVGA Maximum Attenuation 1 LSB 0 5 dB 4 0x03 1 Output SPI frequency on the pins connected to DVGA Give the value in steps of 2 MHz and to a value less than 25 MHz Memory Not used 1 2 5 10 AGC...

Page 120: ...ified in subsequent operands is valid for 4RX Bit 4 RESERVED Bit 5 RESERVED 2 0x01 1 0 Single LNA control 1 Dual LNA control 3 0x02 1 LNA gain margin this value is in dB scale where 1 LSB 0 5 dB LNA re enable will happen when Current DSA Attenuation Maximum DSA Attenuation LNA Gain LNA Gain Margin in Single LNA Control Mode Not Applicable in Dual LNA Control 4 0x03 1 0 Disable Band Detectors 1 Ena...

Page 121: ...n subsequent operands is valid for 3RX Bit 3 1 Value specified in subsequent operands is valid for 4RX Bit 4 RESERVED Bit 5 RESERVED 2 0x01 1 LNA decay threshold dBm Value Band 1 Signal level at the input of chip with LNA enabled should be less than this threshold for re enabling the LNA Signed Number in dBm 1LSB 1dB 3 0x02 1 LNA decay threshold dBm Value Band 2 Signal level at the input of chip w...

Page 122: ...e 0 Absolute 1 Relative If time crossings are specified as Absolute Number 4 0x03 3 Number of samples at FBAND Band Detector Clock Rate for Band detector 1 to declare decay for Band 1 5 0x06 3 Number of samples at FBAND Band Detector Clock Rate for Band detector 2 to declare decay for Band 2 If time crossings are specified as Relative Number 4 0x03 2 Fraction of samples crossing signal threshold i...

Page 123: ...ation Macro Additionally there is a mode where this detector can be used in Internal AGC mode as a very big step attack detector or a detector to bypass LNA Table 1 72 Macro AGC Customer RF Opcode 0x65 Operand Offset Length Value Functionality Results 1 0x00 1 RX Channel Select Bit 0 1 Value specified in subsequent operands is valid for 1RX Bit 1 1 Value specified in subsequent operands is valid f...

Page 124: ...ontrol Configuration Macro The LNA gain and phase can be specified through this macro If external LNA gain does not change with temperature then single LNA gain phase value needs to be specified in the operands If external LNA gain changes with temperature then LNA gain phase values for the start temperature start temperature k step temperature where k 0 Number of steps 1 needs to be specified in ...

Page 125: ... bit External LNA Gain value B1 1 LSB 1 32 dB 6 0x08 2 10 bit External LNA Phase value B1 1 LSB 360 1024 degrees Memory Used based on Ext LNA Temperature Model Maximum 32 entries per band Each Entry has 2 bytes for Gain 6 5U and 2 bytes for Phase 10 0 U Band 1 Number of Steps 4 Bytes is consecutively followed by Band 2 Number of Steps 4 Bytes 1 2 5 15 AGC Gain Step Size Configuration Macro Table 1...

Page 126: ...he DSA attenuation will decrease The different types of step sizes that are present are mentioned here 1 Big Step Attack Step Size 2 Small Step Attack Step Size 3 Big Step Decay Step Size and 4 Small Step Decay Step Size As the names suggest the big step attack or decay step size is expected to be larger than the small step attack and decay step size 1 2 5 16 AGC State Control Macro This is the ma...

Page 127: ...C enable Bit 7 1 External AGC disable Bit 8 1 Toggle the AGC enable Bit 9 1 Toggle the ALC enable Bit 10 1 Toggle the external AGC enable Memory Not used 1 2 5 16 1 Error Reporting Table 1 76 Error Status Registers Interpretation Error Status 1 16 bit 0 INVALID_AGC_EN_COMBINATION AGC start rese toggle can be done only one at a time 1 INVALID_ ALC EXT_AGC _EN_COMBINATION ALC start rese toggle can b...

Page 128: ...2 Coarse gain index on LSBs of only I Q 0x03 Coarse gain index on LSBS of both I Q 0x04 Coarse gain index sent on the ALC output pins Memory Not used This Macro is used for configuring the settings for the ALC module The first operand is again the chain mask This is to indicate for what all chains the current Macro is applicable Total Gain Range This will be the total gain range that will be suppo...

Page 129: ...ed in subsequent operands is valid for 2RX Bit 2 1 Value specified in subsequent operands is valid for 3RX Bit 3 1 Value specified in subsequent operands is valid for 4RX Bit 4 RESERVED Bit 5 RESERVED 2 0x01 1 Floating Point Mode 3 0x02 1 Floating Point Format Memory Not used Floating Point Mode Floating Point Mode two modes 1 0x00 If exponent 0 do not send MSB 2 0x01 Send MSB always Floating Poin...

Page 130: ... Coarse Index 0x00 0 bits coarse index 0x01 Reserved 0x02 2 bits coarse index 0x03 3 bits coarse index 0x04 4 bits coarse index 0x05 0x06 0x07 Reserved 4 0x03 1 Coarse Index Invert feature 5 0x04 1 Coarse Index Swap I and Q feature 6 0x05 1 Digital Back Off 7 0x06 1 Gain Change Indication Memory Not used Coarse Step Size The step size of the gain that is to be indicated over the LSBs The possible ...

Page 131: ...elsius C can be specified through this macro Based on the current temperature nearest LNA gain phase value will be used in the AGC The LNA gain phase values across temperature need to be specified in AGC External LNA Gain Control Configuration Macro Table 1 80 Macro LNA Temperature Configuration Opcode 0x6E Operand Offset Length Value Functionality Results 1 0x00 1 RX Channel Select Bit 0 1 Value ...

Page 132: ...unt of delay that needs to be applied on the gain data before being sent on the pins The value programmed here will correspond to number of cycles of interface rate clock This can be used by the customer to match the ALC pin information with latency of the data through the JESD interface 1 3 SLEEP MODE CONTROL AFE79XX supports two sleep modes 1 Deep Sleep i In this mode the wakeup time is in the o...

Page 133: ... when sleep is triggered Bit 1 0 2RX will go to light sleep when sleep is triggered 1 2RX will go to deep sleep when sleep is triggered Bit 2 0 3RX will go to light sleep when sleep is triggered 1 3RX will go to deep sleep when sleep is triggered Bit 3 0 4RX will go to light sleep when sleep is triggered 1 4RX will go to deep sleep when sleep is triggered 3 0x02 1 FB Channel Select Bit 0 1 1FB wil...

Page 134: ... sleep when sleep is triggered Bit 1 0 2TX will go to light sleep when sleep is triggered 1 2TX will go to deep sleep when sleep is triggered Bit 2 0 3TX will go to light sleep when sleep is triggered 1 3TX will go to deep sleep when sleep is triggered Bit 3 0 4TX will go to light sleep when sleep is triggered 1 4TX will go to deep sleep when sleep is triggered 7 0x06 1 RESERVED Write 1 here 8 0x0...

Page 135: ...s functionality 1 Sleep Mode Configuration Opcode 0x55 Table 1 84 Sleep Mode Configuration Opcode 0x55 Operand Value Comments 1 0x0F All RX Channels to be enabled for Sleep 2 0x00 Light Sleep will be done for all RX Channels 3 0x03 All FB Channels to be enabled for Sleep 4 0x00 Light Sleep will be done for all FB Channels 5 0x0F All TX Channels to be enabled for Sleep 6 0x00 Light Sleep will be do...

Page 136: ...d for TX and FB Channels to be 491 52 MHz The ADC sampling rates are chosen to be 2949 12 MHz and the DAC sampling rate is 11796 48 MHz Further it is assumed that Band 1 Channel Frequency is 3500 MHz and Band 2 Channel Frequency 4000 MHz 1 4 1 System Channel Configuration Opcode 0x21 Table 1 87 Operand Value Comments 1 0x0F Enable all 4 RX Channels 2 0x03 Enable all 2 FB Channels 3 0x0F Enable all...

Page 137: ...e 0x2A Table 1 92 Operand Value Comments 1 0x03 Configure Common Setting for all FB Channels 2 0x06 Select Interface rate of 491 52MHz 1 4 7 TX Interface Rate Configuration Opcode 0x2B Table 1 93 Operand Value Comments 1 0x0F Configure Common Setting for all TX Channels 2 0x06 Select Interface rate of 491 52MHz 1 4 8 RX ADC Rate Configuration Opcode 0x2C Table 1 94 Operand Value Comments 1 0x03 Co...

Page 138: ...figured to receive signal centered at 4000 MHz Table 1 98 Operand Value Comments 1 0x0F Configure Common Channel Frequency for all RX 2 0x00 Single NCO Mode 3 0x000867E0 Band 1 frequency of 3500MHz modulo RX ADC Rate 3 0x00100900 Band 2 frequency of 4000MHz modulo RX ADC Rate 4 0x0 Unused 5 0x0 Unused 1 4 13 FB Channel Frequency Configuration Opcode 0x32 It is assumed here that FB channels are con...

Page 139: ...ed 5 0x00000000 Unused 1 4 15 RX FB Nyquist Zone Configuration Opcode 0x33 The channel frequencies are such that they fall in third Nyquist Zone for both RX and FB Channels Table 1 101 Operand Value Comments 1 0x3F Configure Common Nyquist Band for all RX and FB Channels 2 0x03 Third Nyquist Band i e RX ADC RATE to 3 2 RX ADC RATE 1 4 16 TX Nyquist Zone Configuration Opcode 0x34 The channel freque...

Page 140: ...140 SBAU337 May 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated Serial Interface Register Maps Chapter 2 SBAU337 May 2020 Serial Interface Register Maps ...

Page 141: ...RDES JESD_SUBCHIP DAC_JESD ADC_JESD 18h calib_memory reserved MACRO reserved MCU_mem reserved reserved reserved 19h TX TOP reserved reserved reserved reserved 1Bh ALARMS_CLEAR 7 0 1Ch ALARMS_MASK 7 0 1Dh 0 0 0 0 0 0 ALARMS_MASK 8 ALARMS_CLEA R 8 1Eh ALARMS 7 0 1Fh 0 0 0 0 0 0 0 ALARMS 8 2 1 1 Register 0h offset 0h reset 30h Figure 2 1 Register 0h 7 6 5 4 3 2 1 0 GLOBAL_SOF T_RESET 0 GLOBAL_ASC END...

Page 142: ...h offset 2h reset 0h Figure 2 3 Register 2h 7 6 5 4 3 2 1 0 0 0 0 0 0 0 GLOBAL_MODE R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 4 Register 02 Field Descriptions Bit Field Type Reset Description 7 2 0 R W 0h Must read or write 0 1 0 GLOBAL_MODE R W 0h User definable power mode 2 1 4 Register 3h offset 3h reset Ah Figure 2 4 Registe...

Page 143: ... 8 bits of the chip ID Should read 0 2 1 7 Register 6h offset 6h reset 11h Figure 2 7 Register 6h 7 6 5 4 3 2 1 0 CHIP_VER R 11h LEGEND R W Read Write W Write only n value after reset Table 2 8 Register 06 Field Descriptions Bit Field Type Reset Description 7 0 CHIP_VER R 11h Version of this part Should read 11h 2 1 8 Register 7h offset 7h reset 51h Figure 2 8 Register 7h 7 6 5 4 3 2 1 0 VENDOR_ID...

Page 144: ...d Type Reset Description 7 7 reserved R W 0h 6 6 0 R W 0h Must read or write 0 5 0 EC_DIG R W 0h page select for ADC Digital Bit0 RxA Bit1 RxB Bit2 RxC Bit3 RxD Bit4 FBAB Bit5 FBCD 2 1 11 Register 11h offset 11h reset 0h Figure 2 11 Register 11h 7 6 5 4 3 2 1 0 0 0 EC_ANA R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 12 Register 11 Field Descriptions Bit Field...

Page 145: ..._ANA R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 14 Register 13 Field Descriptions Bit Field Type Reset Description 7 6 DSA_PAGE1 R W 0h DSA page control for Rx Bit0 For page AB Bit1 For page CD 5 4 DSA_PAGE0 R W 0h DSA page control Bit0 For page AB Bit1 FOr page CD 3 0 TX_ANA R W 0h Page select for DAC analog Bit0 TxA Bit1 TxB Bit2 TxC Bit3 TxD 2 1 14 Regis...

Page 146: ...page 0 0 PLL R W 0h Page select for PLL control registers 2 1 16 Register 16h offset 16h reset 0h Figure 2 16 Register 16h 7 6 5 4 3 2 1 0 0 SERDES JESD_SUBCHI P DAC_JESD ADC_JESD R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 17 Register 16 Field Descriptions Bit Field Type Reset Description 7 7 0 R W 0h Must read or write 0 6 5 SERDES R W 0h Pag...

Page 147: ...ad Write W Write only n value after reset Table 2 19 Register 19 Field Descriptions Bit Field Type Reset Description 7 4 TX TOP R W 0h Page select for DAC digital Bit0 TxA Bit1 TxB Bit2 TxC Bit3 TxD 3 3 reserved R W 0h 2 2 reserved R W 0h 1 1 reserved R W 0h 0 0 reserved R W 0h 2 1 19 Register 1Bh offset 1Bh reset 0h Figure 2 19 Register 1Bh 7 6 5 4 3 2 1 0 ALARMS_CLEAR 7 0 R W 0h LEGEND R W Read ...

Page 148: ...1 Register 1Dh 7 6 5 4 3 2 1 0 0 0 0 0 0 0 ALARMS_MAS K 8 ALARMS_CLE AR 8 R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 22 Register 1D Field Descriptions Bit Field Type Reset Description 7 2 0 R W 0h Must read or write 0 1 1 ALARMS_MASK 8 R W 0h Mask Global alarms when asserted 0 alarm_spi_global for SPI A B1 1 alarm_spi_acce...

Page 149: ... access for SPI B1 B2 6 alarm SPI streaming roll over SPI A 7 alarm SPI streaming roll over SPI B1 8 alarm SPI streaming roll over SPI B2 2 1 23 Register 1Fh offset 1Fh reset 0h Figure 2 23 Register 1Fh 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ALARMS 8 R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R 0h LEGEND R W Read Write W Write only n value after reset Table 2 24 Register 1F Field Descriptions Bit Fie...

Page 150: ...RO 6Ah reserved LCMGEN_SYNC _ENA RST_LOCK_DE TECT 6Ch LCMGEN_DIV 7 0 6Dh LCMGEN_DIV 15 8 6Eh reserved LCMGEN_SPI_S YSREF LCMGEN_USE_ SPI_SYSREF 6Fh SYSREF_PULSE_CNT_TX 70h SYSREF_PULSE_CNT_RX 71h SYSREF_PULSE_CNT_FB 72h SYSREF_PULSE_CNT_DIG 84h CTL_LDOVCO_FBRES CTL_LDOVCO_VREF LDOVCO_FORC E_OUTTOVDD reserved reserved reserved 2 2 1 Register 2Ah offset 2Ah reset 0h Figure 2 24 Register 2Ah 7 6 5 4 ...

Page 151: ... 4 reserved R W 0h 3 3 reserved R W 1h 2 2 reserved R W 0h 1 1 reserved R W 0h 0 0 reserved R W 0h 2 2 3 Register 40h offset 40h reset 0h Figure 2 26 Register 40h 7 6 5 4 3 2 1 0 CTL_CP_CURR reserved reserved reserved reserved R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 28 Register 40 Field Descriptions Bit Field Type Reset Description 7 5 CTL_...

Page 152: ... 1h R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 30 Register 43 Field Descriptions Bit Field Type Reset Description 7 5 CTL_LPF_R R W 0h lpf res is given by R 638 638 4 CTL_LPF_R 2 0 4 4 reserved R W 1h 3 3 reserved R W 1h 2 0 reserved R W 0h 2 2 6 Register 5Ch offset 5Ch reset 0h Figure 2 29 Register 5Ch 7 6 5 4 3 2 1 0 reserved SYSREF_LATCH_DELAY R W 0h R W 0h LEG...

Page 153: ...ved EN_LOCK_DE TECT EN_CAL R 0h R 0h R 0h R 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 33 Register 66 Field Descriptions Bit Field Type Reset Description 6 6 LOCK_LOST_STIC KY R 0h This register is set to 1 when PLL loses lock after initial lock is obtained Indicates whether the PLL lock is lost anytime after initial lock 1 PLL lock lost 0 PLL lock not l...

Page 154: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 35 Register 6A Field Descriptions Bit Field Type Reset Description 7 2 reserved R W 0h 1 1 LCMGEN_SYNC_ ENA R W 0h bit to enable lcm_counter syncing on sysref entering plldig 0 0 RST_LOCK_DETE CT R W 0h Reset PLL lock detection 2 2 11 Register 6Ch offset 6Ch reset 0h Figure 2 34 Register 6Ch 7 6 5 4 3 2 1 0 LCMGEN_DIV 7 0 R W 0h LEG...

Page 155: ...escription 7 2 reserved R W 0h 1 1 LCMGEN_SPI_SY SREF R W 0h spi based sysref when LCMGEN_USE_SPI_SYSREF 0 0 LCMGEN_USE_SP I_SYSREF R W 0h Make this bit 1 to provide spi based sysref 2 2 14 Register 6Fh offset 6Fh reset 0h Figure 2 37 Register 6Fh 7 6 5 4 3 2 1 0 SYSREF_PULSE_CNT_TX R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 39 Register 6F Field Descriptions Bit Field Ty...

Page 156: ...ld Type Reset Description 7 0 LCMGEN_DIV 7 0 R W 0h Number of sysref pulses leak to DIGITAL 2 2 18 Register 84h offset 84h reset 0h Figure 2 41 Register 84h 7 6 5 4 3 2 1 0 CTL_LDOVCO_FBRES CTL_LDOVCO_VREF LDOVCO_FOR CE_OUTTOVD D reserved reserved reserved R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 43 Register 84 Field Descriptions Bit ...

Page 157: ...CLK _EN_VAL RXC_P2P3_CLK _EN_OVR RXC_P2P3_CLK _EN_VAL RXB_P2P3_CLK _EN_OVR RXB_P2P3_CLK _EN_VAL RXA_P2P3_CLK _EN_OVR RXA_P2P3_CLK _EN_VAL 34h MUX_SEL_RXA_B1_Q_FOR_2R1F_AB MUX_SEL_RXA_B1_I_FOR_2R1F_AB 35h MUX_SEL_RXA_B2_Q_FOR_2R1F_AB MUX_SEL_RXA_B2_I_FOR_2R1F_AB 36h MUX_SEL_RXB_B1_Q_FOR_2R1F_AB MUX_SEL_RXB_B1_I_FOR_2R1F_AB 37h MUX_SEL_RXB_B2_Q_FOR_2R1F_AB MUX_SEL_RXB_B2_I_FOR_2R1F_AB 38h MUX_SEL_RX...

Page 158: ...0_REORDER 5Dh ADC_JESD_SYNC_N3_REORDER ADC_JESD_SYNC_N2_REORDER 5Eh ADC_JESD_SYNC_N5_REORDER ADC_JESD_SYNC_N4_REORDER 60h MUX_SEL_FOR_TXB_CTRL MUX_SEL_FOR_TXA_CTRL 61h MUX_SEL_FOR_TXD_CTRL MUX_SEL_FOR_TXC_CTRL 68h RXOCTETPATH1_SEL RXOCTETPATH0_SEL 69h RXOCTETPATH3_SEL RXOCTETPATH2_SEL 6Ah RXOCTETPATH5_SEL RXOCTETPATH4_SEL 6Bh RXOCTETPATH7_SEL RXOCTETPATH6_SEL 6Ch RXOCTETPATH1_CLK_SEL RXOCTETPATH0_...

Page 159: ..._P01 IQ_SWAP_FBAB _P23 IQ_SWAP_FBAB _P01 B4h TDD_FB_ON_C _2R1F_AB_MAS K TDD_FB_ON_A_ 2R1F_AB_MASK TDD_RX_ON_D _2R1F_AB_MAS K TDD_RX_ON_C _2R1F_AB_MAS K TDD_RX_ON_B _2R1F_AB_MAS K TDD_RX_ON_A _2R1F_AB_MAS K B5h TDD_FB_DYN_ SWITCH_PRIOR ITYSWAP_2R1F _AB TDD_RX_PRIOR ITY_DIS_2R1F_ AB B6h TDD_FB_ON_C _2R1F_CD_MAS K TDD_FB_ON_A_ 2R1F_CD_MAS K TDD_RX_ON_D _2R1F_CD_MAS K TDD_RX_ON_C _2R1F_CD_MAS K TDD_RX...

Page 160: ...R DBG_RXC_AFIF O_DBG_CFG_C LR DBG_RXB_AFIF O_DBG_CFG_C LR DBG_RXA_AFIF O_DBG_CFG_C LR 161h DBG_FIFO_SEL DBG_CFG_FIFO _PTR_SAMPLE 162h DBG_FIFO_SAMPLED_WR_PTR DBG_FIFO_SAMPLED_RD_PTR 164h DBG_RXB_ASYNC_FIFO_ALARM_CLR DBG_RXA_ASYNC_FIFO_ALARM_CLR 165h DBG_RXD_ASYNC_FIFO_ALARM_CLR DBG_RXC_ASYNC_FIFO_ALARM_CLR 166h DBG_FBCD_ASYNC_FIFO_ALARM_CLR DBG_FBAB_ASYNC_FIFO_ALARM_CLR 168h DBG_RXB_ASYNC_FIFO_ALA...

Page 161: ...ARE_OUT_REG1 19Eh SPARE_OUT_REG2 19Fh SPARE_OUT_REG3 1A0h SPARE_OUT_REG4 1A1h SPARE_OUT_REG5 1A2h SPARE_OUT_REG6 1A3h SPARE_OUT_REG7 1A4h SPARE_IN 7 0 1A5h SPARE_IN 15 8 1A6h SPARE_IN 23 16 1A7h SPARE_IN 31 24 2 3 1 Register 20h offset 20h reset 12h Figure 2 42 Register 20h 7 6 5 4 3 2 1 0 SERDESAB_A DDR_BIT13_FL IP SERDESAB_APB_MODE_16B SERDESAB_APB_PIN_INTF_EN SERDESAB_APB_PAGE_ADDR _INDEX R W 0...

Page 162: ...IT13_FLIP R W 0h Set this bit to flip the addr 13 of addr 15 0 of SerdesCD APB bus 0 flip 1 no flip 5 4 SERDESCD_APB_ MODE_16B R W 1h Interface mode for SerdesCD 0 8b APB Intf 1 16b APB Intf 2 32b APB Intf 3 2 SERDESCD_APB_ PIN_INTF_EN R W 0h set this bit to access SerdesCD APB interface through differnt modes 0 SPI2APB 1 GPIO 2 CM4 AHB 1 0 SERDESCD_APB_ PAGE_ADDR_IND EX R W 2h page_address_index ...

Page 163: ...5 STX6 STX7 and STX8 txbclks 0 no inversion 1 invert 3 STX8 txbclk invert 2 STX7 txbclk invert 1 STX6 txbclk invert 0 STX5 txbclk invert 3 0 SERDESAB_TXBC LK_INV_ENA R W Fh register to invert SerdesAB STX1 STX2 STX3 and STX4 txbclks 0 no inversion 1 invert 3 STX4 txbclk invert 2 STX3 txbclk invert 1 STX2 txbclk invert 0 STX1 txbclk invert 2 3 5 Register 26h offset 26h reset FFh Figure 2 46 Registe...

Page 164: ...29h offset 29h reset 3h Figure 2 48 Register 29h 7 6 5 4 3 2 1 0 DUAL_2T2R1F _MODE_CD DUAL_2T2R1F _MODE_AB R W 1h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 51 Register 29 Field Descriptions Bit Field Type Reset Description 1 1 DUAL_2T2R1F_M ODE_CD R W 1h Used for 2r1f_cd instance Default mode is dual 2r1f modes For RX L1 and M16 cases or FB M4 make this bit 0 Recommende...

Page 165: ... register as the correct values and the sequence depends on the mode of usage 2 3 9 Register 2Bh offset 2Bh reset 0h Figure 2 50 Register 2Bh 7 6 5 4 3 2 1 0 SEL_DYN_FBC D_ADC_FBCD _REF SEL_DYN_FBA B_ADC_FBAB_ REF R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 53 Register 2B Field Descriptions Bit Field Type Reset Description 1 1 SEL_DYN_FBCD_ ADC_FBCD_REF R W 0h For ...

Page 166: ...es this behaviour and the gating of data depends on the value of RXB_SIG_INVALID_RD_VAL 2 2 RXB_SIG_INVALID _RD_VAL R W 0h FOR LOW POWER CONSUMPTION When RXB_SIG_INVALID_RD_OVR is 1 setting this register val 0 gates the data setting to val 1 ungates the data 1 1 RXA_SIG_INVALID _RD_OVR R W 0h FOR LOW POWER CONSUMPTION ASYNC FIFOs are gated based on sig invalid from TDD controller Setting this regi...

Page 167: ...fset 2Fh reset 0h Figure 2 54 Register 2Fh 7 6 5 4 3 2 1 0 MUX_SEL_FO R_DUC_TXB_T O_TXD_CLK MUX_SEL_FO R_DUC_TXB_T O_TXC_CLK MUX_SEL_FO R_DUC_TXA_T O_TXB_CLK MUX_OVR_FO R_DUC_CLK R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 57 Register 2F Field Descriptions Bit Field Type Reset Description 4 4 MUX_SEL_FOR_D UC_TXB_TO_TXD _CLK R W 0h FOR LOW POWER CONSU...

Page 168: ...W 8h R W 8h LEGEND R W Read Write W Write only n value after reset Table 2 58 Register 30 Field Descriptions Bit Field Type Reset Description 7 4 RXB_AFIFO_OFFS ET R W 8h RRF to JESD ASYNC FIFO offset for RXB DATA 3 0 RXA_AFIFO_OFFS ET R W 8h RRF to JESD ASYNC FIFO offset for RXA DATA 2 3 15 Register 31h offset 31h reset 88h Figure 2 56 Register 31h 7 6 5 4 3 2 1 0 RXD_AFIFO_OFFSET RXC_AFIFO_OFFSE...

Page 169: ...e gated val 1 p2 p3 clocks are ungated 5 5 RXC_P2P3_CLK_ EN_OVR R W 0h FOR LOW POWER CONSUMPTION Single band cases p2 p3 streams are not valid so clocks to the ASYNC FIFO are gated To override the default behaviour set this enable override register to 1 4 4 RXC_P2P3_CLK_ EN_VAL R W 0h FOR LOW POWER CONSUMPTION When RXC_P2P3_CLK_EN_OVR is set to 1 val 0 p2 p3 clocks are gated val 1 p2 p3 clocks are...

Page 170: ...cts the ddc stream that is to be routed to jesd 2R1F instance0 rxa_0 0 b1_rxa_i rxa_i_s0 1 b2_rxa_i rxa_i_s1 2 b1_rxb_i rxb_i_s0 3 b2_rxb_i rxb_i_s1 4 b1_rxc_i rxc_i_s0 5 b2_rxc_i rxc_i_s1 6 b1_rxd_i rxd_i_s0 7 b2_rxd_i rxd_i_s1 Using LATTE to configure this register is recommended 2 3 19 Register 35h offset 35h reset 22h Figure 2 60 Register 35h 7 6 5 4 3 2 1 0 MUX_SEL_RXA_B2_Q_FOR_2R1F_AB MUX_SE...

Page 171: ...ster 36 Field Descriptions Bit Field Type Reset Description 6 4 MUX_SEL_RXB_B 1_Q_FOR_2R1F_A B R W 4h TO CONTROL DATA GOING TO 2R1F_AB i e STX1 STX2 STX3 STX4 assuming no lane mux Selects the ddc stream that is to be routed to jesd 2R1F instance0 rxb_1 0 b1_rxa_q rxa_q_s0 1 b2_rxa_q rxa_q_s1 2 b1_rxb_q rxb_q_s0 3 b2_rxb_q rxb_q_s1 4 b1_rxc_q rxc_q_s0 5 b2_rxc_q rxc_q_s1 6 b1_rxd_q rxd_q_s0 7 b2_rx...

Page 172: ...cts the ddc stream that is to be routed to jesd 2R1F instance0 rxb_2 0 b1_rxa_i rxa_i_s0 1 b2_rxa_i rxa_i_s1 2 b1_rxb_i rxb_i_s0 3 b2_rxb_i rxb_i_s1 4 b1_rxc_i rxc_i_s0 5 b2_rxc_i rxc_i_s1 6 b1_rxd_i rxd_i_s0 7 b2_rxd_i rxd_i_s1 Using LATTE to configure this register is recommended 2 3 22 Register 38h offset 38h reset 44h Figure 2 63 Register 38h 7 6 5 4 3 2 1 0 MUX_SEL_RXC_B1_Q_FOR_2R1F_AB MUX_SE...

Page 173: ...ster 39 Field Descriptions Bit Field Type Reset Description 6 4 MUX_SEL_RXC_B 2_Q_FOR_2R1F_A B R W 5h TO CONTROL DATA GOING TO 2R1F_AB i e STX1 STX2 STX3 STX4 assuming no lane mux Selects the ddc stream that is to be routed to jesd 2R1F instance0 rxc_3 0 b1_rxa_q rxa_q_s0 1 b2_rxa_q rxa_q_s1 2 b1_rxb_q rxb_q_s0 3 b2_rxb_q rxb_q_s1 4 b1_rxc_q rxc_q_s0 5 b2_rxc_q rxc_q_s1 6 b1_rxd_q rxd_q_s0 7 b2_rx...

Page 174: ...cts the ddc stream that is to be routed to jesd 2R1F instance0 rxd_0 0 b1_rxa_i rxa_i_s0 1 b2_rxa_i rxa_i_s1 2 b1_rxb_i rxb_i_s0 3 b2_rxb_i rxb_i_s1 4 b1_rxc_i rxc_i_s0 5 b2_rxc_i rxc_i_s1 6 b1_rxd_i rxd_i_s0 7 b2_rxd_i rxd_i_s1 Using LATTE to configure this register is recommended 2 3 25 Register 3Bh offset 3Bh reset 77h Figure 2 66 Register 3Bh 7 6 5 4 3 2 1 0 MUX_SEL_RXD_B2_Q_FOR_2R1F_AB MUX_SE...

Page 175: ...ster 40 Field Descriptions Bit Field Type Reset Description 6 4 MUX_SEL_RXC_B 1_Q_FOR_2R1F_ CD R W 0h TO CONTROL DATA GOING TO 2R1F_CD i e STX5 STX6 STX7 STX8 assuming no lane mux Selects the ddc stream that is to be routed to jesd 2R1F instance1 rxc_1 0 b1_rxc_q rxc_q_s0 1 b2_rxc_q rxc_q_s1 2 b1_rxd_q rxd_q_s0 3 b2_rxd_q rxd_q_s1 4 b1_rxa_q rxa_q_s0 5 b2_rxa_q rxa_q_s1 6 b1_rxb_q rxb_q_s0 7 b2_rx...

Page 176: ...cts the ddc stream that is to be routed to jesd 2R1F instance1 rxc_2 0 b1_rxc_i rxc_i_s0 1 b2_rxc_i rxc_i_s1 2 b1_rxd_i rxd_i_s0 3 b2_rxd_i rxd_i_s1 4 b1_rxa_i rxa_i_s0 5 b2_rxa_i rxa_i_s1 6 b1_rxb_i rxb_i_s0 7 b2_rxb_i rxb_i_s1 Using LATTE to configure this register is recommended 2 3 28 Register 42h offset 42h reset 22h Figure 2 69 Register 42h 7 6 5 4 3 2 1 0 MUX_SEL_RXD_B1_Q_FOR_2R1F_CD MUX_SE...

Page 177: ...RXD_B2_I_FOR_2R1F_CD R W 3h R W 3h LEGEND R W Read Write W Write only n value after reset Table 2 73 Register 43 Field Descriptions Bit Field Type Reset Description 6 4 MUX_SEL_RXD_B 2_Q_FOR_2R1F_ CD R W 3h TO CONTROL DATA GOING TO 2R1F_CD i e STX5 STX6 STX7 STX8 assuming no lane mux Selects the ddc stream that is to be routed to jesd 2R1F instance1 rxd_3 0 b1_rxc_q rxc_q_s0 1 b2_rxc_q rxc_q_s1 2 ...

Page 178: ...i e STX1 STX2 STX3 STX4 assuming no lane mux Selects the ddc stream that is to be routed to jesd 2R1F instance0 fbab_2 0 fbab_i_s0 1 fbab_i_s1 2 fbcd_i_s0 3 fbcd_i_s1 Using LATTE to configure this register is recommended 3 2 MUX_SEL_FBAB_ Q0_FOR_2R1F_A B R W 0h TO CONTROL DATA GOING TO 2R1F_AB i e STX1 STX2 STX3 STX4 assuming no lane mux Selects the ddc stream that is to be routed to jesd 2R1F ins...

Page 179: ...ng no lane mux Selects the ddc stream that is to be routed to jesd 2R1F instance0 fbcd_1 0 fbab_q_s0 1 fbab_q_s1 2 fbcd_q_s0 3 fbcd_q_s1 Using LATTE to configure this register is recommended 1 0 MUX_SEL_FBCD_I 0_FOR_2R1F_AB R W 2h TO CONTROL DATA GOING TO 2R1F_AB i e STX1 STX2 STX3 STX4 assuming no lane mux Selects the ddc stream that is to be routed to jesd 2R1F instance0 fbcd_0 0 fbab_i_s0 1 fba...

Page 180: ...suming no lane mux Selects the ddc stream that is to be routed to jesd 2R1F instance1 fbab_0 0 fbcd_i_s0 1 fbcd_i_s1 2 fbab_i_s0 3 fbab_i_s1 Using LATTE to configure this register is recommended 2 3 33 Register 47h offset 47h reset 50h Figure 2 74 Register 47h 7 6 5 4 3 2 1 0 MUX_SEL_FBCD_Q1_FOR_2R1 F_CD MUX_SEL_FBCD_I1_FOR_2R1 F_CD MUX_SEL_FBCD_Q0_FOR_2R1 F_CD MUX_SEL_FBCD_I0_FOR_2R1 F_CD R W 1h ...

Page 181: ...ng LATTE to configure this register is recommended 2 3 34 Register 48h offset 48h reset 10h Figure 2 75 Register 48h 7 6 5 4 3 2 1 0 TXOCTETPATH1_SEL TXOCTETPATH0_SEL R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 78 Register 48 Field Descriptions Bit Field Type Reset Description 6 4 TXOCTETPATH1_ SEL R W 1h Selects the input SERDES Tx lane for data that is normally s...

Page 182: ... 3 36 Register 4Ah offset 4Ah reset 54h Figure 2 77 Register 4Ah 7 6 5 4 3 2 1 0 TXOCTETPATH5_SEL TXOCTETPATH4_SEL R W 5h R W 4h LEGEND R W Read Write W Write only n value after reset Table 2 80 Register 4A Field Descriptions Bit Field Type Reset Description 6 4 TXOCTETPATH5_ SEL R W 5h Selects the input SERDES Tx lane for data that is normally supposed to be on STX6 0 sel lane0 data 1 sel lane1 d...

Page 183: ...gister 4Ch offset 4Ch reset 10h Figure 2 79 Register 4Ch 7 6 5 4 3 2 1 0 TXOCTETPATH1_CLK_SEL TXOCTETPATH0_CLK_SEL R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 82 Register 4C Field Descriptions Bit Field Type Reset Description 6 4 TXOCTETPATH1_ CLK_SEL R W 1h Selects the input SERDES Tx lane for clk data that is normally supposed to be on STX2 0 sel lane0 clk 1 sel ...

Page 184: ...gister 4Eh offset 4Eh reset 54h Figure 2 81 Register 4Eh 7 6 5 4 3 2 1 0 TXOCTETPATH5_CLK_SEL TXOCTETPATH4_CLK_SEL R W 5h R W 4h LEGEND R W Read Write W Write only n value after reset Table 2 84 Register 4E Field Descriptions Bit Field Type Reset Description 6 4 TXOCTETPATH5_ CLK_SEL R W 5h Selects the input SERDES Tx lane clk for data that is normally supposed to be on STX6 0 sel lane0 clk 1 sel ...

Page 185: ...ODE_ TX1 RX_TX_LOOP BACK_MODE_ TX0 R W 1h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 86 Register 50 Field Descriptions Bit Field Type Reset Description 5 5 RX_TX_LOOPBAC K_FIFO_INIT_STA TE R W 1h Init state to release Async FIFO between ADC_JESD and DAC_JESD out of reset 0 Reset State 1 Func State 4 2 RX_TX_LOOPBAC K_FIFO_OFFSET R W 0h serdes loopback FIFO ...

Page 186: ...d or not 0 Normal data No negation 1 2 s complement negation 2 3 44 Register 53h offset 53h reset 0h Figure 2 85 Register 53h 7 6 5 4 3 2 1 0 TXD_B1_Q_DA TA_NEGATION TXD_B1_I_DA TA_NEGATION TXD_B0_Q_DA TA_NEGATION TXD_B0_I_DA TA_NEGATION TXC_B1_Q_DA TA_NEGATION TXC_B1_I_DA TA_NEGATION TXC_B0_Q_DA TA_NEGATION TXC_B0_I_DA TA_NEGATION R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W...

Page 187: ...his register is recommended 2 0 ADC_JESD_SYNC _N0_MUX_SEL R W 0h adc_jesd_sync_ _mux and adc_jesd_sync_ _reorder registers together implement the sync reorder and broadcast funcationlity This register is used for change the sync_n pin order Using LATTE to configure this register is recommended 2 3 46 Register 55h offset 55h reset 32h Figure 2 87 Register 55h 7 6 5 4 3 2 1 0 ADC_JESD_SYNC_N3_MUX_SE...

Page 188: ...rder and broadcast funcationlity This register is used for change the sync_n pin order Using LATTE to configure this register is recommended 2 3 48 Register 57h offset 57h reset 0h Figure 2 89 Register 57h 7 6 5 4 3 2 1 0 ADC_JESD_SY NC_N5_INV ADC_JESD_SY NC_N4_INV ADC_JESD_SY NC_N3_INV ADC_JESD_SY NC_N2_INV ADC_JESD_SY NC_N1_INV ADC_JESD_SY NC_N0_INV R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGE...

Page 189: ...PI value to override the sync_n 5 Has effect only when ADC_JESD_SYNC_N1_SPI_OVR is 1 0 0 ADC_JESD_SYNC _N0_SPI_VAL R W 0h SPI value to override the sync_n 5 Has effect only when ADC_JESD_SYNC_N0_SPI_OVR is 1 2 3 50 Register 59h offset 59h reset 0h Figure 2 91 Register 59h 7 6 5 4 3 2 1 0 ADC_JESD_SY NC_N5_SPI_O VR ADC_JESD_SY NC_N4_SPI_O VR ADC_JESD_SY NC_N3_SPI_O VR ADC_JESD_SY NC_N2_SPI_O VR ADC...

Page 190: ... broadcast to multiple lanes Using LATTE to configure this register is recommended 2 3 52 Register 5Dh offset 5Dh reset 32h Figure 2 93 Register 5Dh 7 6 5 4 3 2 1 0 ADC_JESD_SYNC_N3_REORDER ADC_JESD_SYNC_N2_REORDER R W 3h R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 96 Register 5D Field Descriptions Bit Field Type Reset Description 6 4 ADC_JESD_SYNC _N3_REORDER R W 3h adc_...

Page 191: ...Register 60h 7 6 5 4 3 2 1 0 MUX_SEL_FOR_TXB_CTRL MUX_SEL_FOR_TXA_CTRL R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 98 Register 60 Field Descriptions Bit Field Type Reset Description 6 4 MUX_SEL_FOR_T XB_CTRL R W 1h Selects the OP_SAMP_MODE 12B MODE and ALARMS that are to be routed to jesd TXB 0 sel from 2T0_TXA 1 sel from 2T0_TXB 2 sel from 2T0_TXC 3 sel from 2T0_T...

Page 192: ...from 2T0_TXC 3 sel from 2T0_TXD 4 sel from 2T1_TXA 5 sel from 2T1_TXB 6 sel from 2T1_TXC 7 sel from 2T1_TXD Using LATTE to configure this register is recommended 2 3 56 Register 68h offset 68h reset 10h Figure 2 97 Register 68h 7 6 5 4 3 2 1 0 RXOCTETPATH1_SEL RXOCTETPATH0_SEL R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 100 Register 68 Field Descriptions Bit Field ...

Page 193: ...or data that is normally supposed to be on SRX3 0 sel lane0 data 1 sel lane1 data 2 sel lane2 data 3 sel lane3 data 4 sel lane4 data 5 sel lane5 data 6 sel lane6 data 7 sel lane7 data 2 3 58 Register 6Ah offset 6Ah reset 54h Figure 2 99 Register 6Ah 7 6 5 4 3 2 1 0 RXOCTETPATH5_SEL RXOCTETPATH4_SEL R W 5h R W 4h LEGEND R W Read Write W Write only n value after reset Table 2 102 Register 6A Field D...

Page 194: ...ata that is normally supposed to be on SRX7 0 sel lane0 data 1 sel lane1 data 2 sel lane2 data 3 sel lane3 data 4 sel lane4 data 5 sel lane5 data 6 sel lane6 data 7 sel lane7 data 2 3 60 Register 6Ch offset 6Ch reset 10h Figure 2 101 Register 6Ch 7 6 5 4 3 2 1 0 RXOCTETPATH1_CLK_SEL RXOCTETPATH0_CLK_SEL R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 104 Register 6C Fi...

Page 195: ...ne clk for data that is normally supposed to be on SRX3 0 sel lane0 clk 1 sel lane1 clk 2 sel lane2 clk 3 sel lane3 clk 4 sel lane4 clk 5 sel lane5 clk 6 sel lane6 clk 7 sel lane7 clk 2 3 62 Register 6Eh offset 6Eh reset 54h Figure 2 103 Register 6Eh 7 6 5 4 3 2 1 0 RXOCTETPATH5_CLK_SEL RXOCTETPATH4_CLK_SEL R W 5h R W 4h LEGEND R W Read Write W Write only n value after reset Table 2 106 Register 6...

Page 196: ...l lane3 clk 4 sel lane4 clk 5 sel lane5 clk 6 sel lane6 clk 7 sel lane7 clk 2 3 64 Register 78h offset 78h reset 0h Figure 2 105 Register 78h 7 6 5 4 3 2 1 0 ADC_DATA_G ATING_DIS_FB CD ADC_DATA_G ATING_DIS_FB AB ADC_DATA_G ATING_DIS_R XD ADC_DATA_G ATING_DIS_R XC ADC_DATA_G ATING_DIS_R XB ADC_DATA_G ATING_DIS_R XA R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value...

Page 197: ...fset 79h reset 0h Figure 2 106 Register 79h 7 6 5 4 3 2 1 0 BIT_MASKDIS_RXB BIT_MASKDIS_RXA R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 109 Register 79 Field Descriptions Bit Field Type Reset Description 7 4 BIT_MASKDIS_RX B R W 0h To disable gating in RxB data of the below mentioned LSBS when RxB is OFF since these LSBs might carry OVR data 0001 LSB0 0010 LSB1 010...

Page 198: ...ioned LSBS when FBCD is OFF since these LSBs might carry OVR data 0001 LSB0 0010 LSB1 0100 LSB4 1000 LSB5 3 0 BIT_MASKDIS_FB AB R W 0h To disable gating in FB A data of the below mentioned LSBS when FBAB is OFF since these LSBs might carry OVR data 0001 LSB0 0010 LSB1 0100 LSB4 1000 LSB5 2 3 68 Register 7Ch offset 7Ch reset C3h Figure 2 109 Register 7Ch 7 6 5 4 3 2 1 0 LP_RX_ON_B_SEL_2R1F_AB_MASK ...

Page 199: ...Register 7D Field Descriptions Bit Field Type Reset Description 7 4 LP_RX_ON_D_SE L_2R1F_AB_MAS K R W 0h FOR LOW POWER CONSUMPTION Its a bit mask used to compute sig valid as a combination of rx_on d c b a Used to gate 4 streams of 16b data i e output of 4R mux for 2R1F_AB inst So based on the data mux settings this mask should be chosen 1111 Uses or ed rx_on d c b a 0111 Uses or ed rx_on c b a 00...

Page 200: ..._ON_C_SEL_2R1F_CD_MASK R W 0h R W 3h LEGEND R W Read Write W Write only n value after reset Table 2 115 Register 81 Field Descriptions Bit Field Type Reset Description 7 4 LP_RX_ON_D_SE L_2R1F_CD_MAS K R W 0h FOR LOW POWER CONSUMPTION Its a bit mask used to compute sig valid as a combination of rx_on b a d c Used to gate 4 streams of 16b data i e output of 4R mux for 2R1F_CD inst So based on the d...

Page 201: ... of fb_on a c Used to gate 4 streams of 16b data i e output of 2F mux for 2R1F_CD inst So based on the data mux settings this mask should be chosen 11 uses or ed fb_on a c 01 uses or ed fb_on c 00 uses zero 2 3 73 Register 90h offset 90h reset 0h Figure 2 114 Register 90h 7 6 5 4 3 2 1 0 CFG_CNT_FR EERUN_EN CFG_CLK_CY CLE_CNT_EN CFG_COMPAR ATOR_MODUL E_EN R W 0h R W 0h R W 0h LEGEND R W Read Write...

Page 202: ...jesd fifo rd clk for fbab 7 adc_jesd_ab_clk_rx1_p0 Jesd clk for rxa 8 adc_jesd_ab_clk_rx2_p0 Jesd clk for rxb 9 adc_jesd_ab_clk_fb_p0 Jesd clk for fbab 10 w_rxa_adc_clk_dft 0 RRF_to_JESD clk for rxa 11 w_rxc_adc_clk_dft 0 RRF_to_JESD clk for rxc 12 w_fbab_adc_clk_dft 0 RRF_to_JESD clk for fbab 13 w_fbcd_adc_clk_dft 0 RRF_to_JESD clk for fbcd 14 w_ddc_rd_clk_rxc Jesd clk for rxc 15 w_ddc_rd_clk_fbc...

Page 203: ..._dft 0 RRF_to_JESD clk for fbab 13 w_fbcd_adc_clk_dft 0 RRF_to_JESD clk for fbcd 14 w_ddc_rd_clk_rxc Jesd clk for rxc 15 w_ddc_rd_clk_fbcd Jesd clk for fbcd Clk sel for INST1 0 Lane0 Serdes ab rx clk coming from lane mux 1 Lane0 Serdes cd rx clk coming from lane mux 2 Dither tx div4 clk phase 0 3 JESD_to_TXTOP clk for txa 4 JESD_to_TXTOP clk for txb 5 JESD_to_TXTOP clk for txc 6 JESD_to_TXTOP clk ...

Page 204: ..._COMP_ SLOW_CNT_OBS_ SEL R W 0h Select control for observing one of the bit in clock comparator slow counter 3 0 CFG_CLK_COMP_ FAST_CNT_OBS_ SEL R W 0h Select control for observing one of the bit in clock comparator fast counter 2 3 78 Register 95h offset 95h reset 0h Figure 2 119 Register 95h 7 6 5 4 3 2 1 0 CFG_CLK_CO MPARATOR_I NST_SEL R W 0h LEGEND R W Read Write W Write only n value after res...

Page 205: ...scriptions Bit Field Type Reset Description 7 0 FAST_CLK_CNT 7 0 R 0h Fast clock count value 2 3 81 Register 99h offset 99h reset 0h Figure 2 122 Register 99h 7 6 5 4 3 2 1 0 FAST_CLK_CNT 15 8 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 125 Register 99 Field Descriptions Bit Field Type Reset Description 7 0 FAST_CLK_CNT 1 5 8 R 0h Fast clock count value 2 3 82 Register 9Ah ...

Page 206: ...ption 7 7 RX_CLK_LFSR_S EED_LOAD R W 0h Loads the LFSR seed value when this is set to 1 Need to be used along with tx_clk_lfsr_seed_val register 0 Use default LFSR seed value 1 Load LFSR seed value from register 6 6 RX_CLK_SYSREF _VAL R W 0h spi based sysref 5 5 RX_CLK_SYSREF _SEL R W 0h select spi based sysref which is rx_clk_sysref_val 4 2 RX_CLK_SYSREF _DELAY R W 0h delaying the sysref to the d...

Page 207: ...div8 clocks will have 4 clock phases 1 div8 clocks will have a single phase 0 Enable multi phase 1 Disable multi phase 2 3 86 Register 9Eh offset 9Eh reset 3h Figure 2 127 Register 9Eh 7 6 5 4 3 2 1 0 FB_CLK_LFSR _SEED_LOAD FB_CLK_SYSR EF_VAL FB_CLK_SYSR EF_SEL FB_CLK_SYSREF_DELAY FB_CLK_DITH ERED_MODE_ EN FB_CLK_DISA BLE R W 0h R W 0h R W 0h R W 0h R W 1h R W 1h LEGEND R W Read Write W Write only...

Page 208: ...ISABLE R W 0h setting this to 1 will disable clock div8_phase3 0 Enable 1 Disable 3 3 FB_CLK_DIV4_PH ASE2_DISABLE R W 0h setting this to 1 will disable clock div8_phase2 0 Enable 1 Disable 2 2 FB_CLK_DIV4_PH ASE1_DISABLE R W 0h setting this to 1 will disable clock div8_phase1 0 Enable 1 Disable 1 1 FB_CLK_DIV4_PH ASE0_DISABLE R W 0h setting this to 1 will disable clock div8_phase0 0 Enable 1 Disab...

Page 209: ...R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 133 Register A1 Field Descriptions Bit Field Type Reset Description 6 6 TX_CLK_DIV4_CO MMON_PHASE_DI SABLE R W 0h setting this to 1 will disable all clk phases 0 Enable 1 Disable 5 5 TX_CLK_DIV4_PH ASE4_DISABLE R W 1h setting this to 1 will disable clock div8_phase4 0 Enable 1 Disable 4 4 TX_CLK_DIV4_...

Page 210: ...0 R W ABh lfsr seed value Need to be used along with rx_clk_lfsr_seed_load register 2 3 92 Register A6h offset A6h reset CDh Figure 2 133 Register A6h 7 6 5 4 3 2 1 0 RX_CLK_LFSR_SEED_VAL 15 8 R W CDh LEGEND R W Read Write W Write only n value after reset Table 2 136 Register A6 Field Descriptions Bit Field Type Reset Description 7 0 RX_CLK_LFSR_S EED_VAL 15 8 R W CDh lfsr seed value Need to be us...

Page 211: ..._SEED_VAL 7 0 R W ABh LEGEND R W Read Write W Write only n value after reset Table 2 139 Register A9 Field Descriptions Bit Field Type Reset Description 7 0 FB_CLK_LFSR_SE ED_VAL 7 0 R W ABh lfsr seed value Need to be used along with fb_clk_lfsr_seed_load register 2 3 96 Register AAh offset AAh reset CDh Figure 2 137 Register AAh 7 6 5 4 3 2 1 0 FB_CLK_LFSR_SEED_VAL 15 8 R W CDh LEGEND R W Read Wr...

Page 212: ...0 TX_CLK_DIV_VAL _ACC_THRESH R W 10h Accumulator threshold while running dithered mode 2 3 99 Register ADh offset ADh reset ABh Figure 2 140 Register ADh 7 6 5 4 3 2 1 0 TX_CLK_LFSR_SEED_VAL 7 0 R W ABh LEGEND R W Read Write W Write only n value after reset Table 2 143 Register AD Field Descriptions Bit Field Type Reset Description 7 0 TX_CLK_LFSR_SE ED_VAL 7 0 R W ABh lfsr seed value Need to be u...

Page 213: ... R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 146 Register B0 Field Descriptions Bit Field Type Reset Description 7 7 IQ_SWAP_RXD_P 23 R W 0h When 1 swap data on pins p2 and p3 Used for IQ swap 0 No swap 1 swap 6 6 IQ_SWAP_RXD_P 01 R W 0h When 1 swap data on pins p0 and p1 Used for IQ swap 0 No swap 1 swap 5 5 IQ_SWAP_RXC_P 23 R W ...

Page 214: ...wap 2 3 104 Register B4h offset B4h reset 11h Figure 2 145 Register B4h 7 6 5 4 3 2 1 0 TDD_FB_ON_ C_2R1F_AB_M ASK TDD_FB_ON_ A_2R1F_AB_M ASK TDD_RX_ON_ D_2R1F_AB_M ASK TDD_RX_ON_ C_2R1F_AB_M ASK TDD_RX_ON_ B_2R1F_AB_M ASK TDD_RX_ON_ A_2R1F_AB_M ASK R W 0h R W 1h R W 0h R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 148 Register B4 Field Descriptions Bit Field ...

Page 215: ...RITYSWAP_2R 1F_AB TDD_RX_PRIO RITY_DIS_2R1 F_AB R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 149 Register B5 Field Descriptions Bit Field Type Reset Description 2 2 TDD_FB_DYN_SW ITCH_PRIORITYS WAP_2R1F_AB R W 0h by default to 2R1F0 fb_dyn_switch from fb_on_ab has higher prirority over fb_on_cd Set this bit to swap the priority 0 fb_on_ab 1 fb_on_cd 0 0 TDD_RX_PRIOR...

Page 216: ... rx data has rxb information then set the register to 1 0 mask 1 rx_on_b 0 0 TDD_RX_ON_A_2 R1F_CD_MASK R W 0h Used to derive TDD switching signal the decides RX FB data going on the lanes for 2R1F_CD instance If the rx data has rxa information then set the register to 1 0 mask 1 rx_on_a 2 3 107 Register B7h offset B7h reset 0h Figure 2 148 Register B7h 7 6 5 4 3 2 1 0 TDD_FB_DYN_ SWITCH_PRIO RITYS...

Page 217: ...TX_ON_ D_2T_AB_LINK 1_MASK TDD_TX_ON_ C_2T_AB_LINK 1_MASK TDD_TX_ON_ B_2T_AB_LINK 1_MASK TDD_TX_ON_ A_2T_AB_LINK 1_MASK TDD_TX_ON_ D_2T_AB_LINK 0_MASK TDD_TX_ON_ C_2T_AB_LINK 0_MASK TDD_TX_ON_ B_2T_AB_LINK 0_MASK TDD_TX_ON_ A_2T_AB_LINK 0_MASK R W 1h R W 1h R W 1h R W 1h R W 1h R W 1h R W 1h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 153 Register BD Field Descriptions Bi...

Page 218: ...igure 2 151 Register BEh 7 6 5 4 3 2 1 0 TDD_TX_ON_D_2T_CD_MUX_S EL TDD_TX_ON_C_2T_CD_MUX_S EL TDD_TX_ON_B_2T_CD_MUX_S EL TDD_TX_ON_A_2T_CD_MUX_S EL R W 1h R W 0h R W 3h R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 154 Register BE Field Descriptions Bit Field Type Reset Description 7 6 TDD_TX_ON_D_2 T_CD_MUX_SEL R W 1h mux select value for tx_on_a to be set if TXD data com...

Page 219: ...c 5 5 TDD_TX_ON_B_2 T_CD_LINK1_MAS K R W 1h TDD mask value for tx_on_a to be set if TXB data comes from 2T_CD instance and link1 0 mask 1 tx_on_b 4 4 TDD_TX_ON_A_2 T_CD_LINK1_MAS K R W 1h TDD mask value for tx_on_a to be set if TXA data comes from 2T_CD instance and link1 0 mask 1 tx_on_a 3 3 TDD_TX_ON_D_2 T_CD_LINK0_MAS K R W 1h TDD mask value for tx_on_a to be set if TXD data comes from 2T_CD in...

Page 220: ...de_en 1 the divide factor will dynamically change between N and N 1 one lower than the above mentioned divide factors If apb_clk_div_factor 1 and apb_clk_div_factor_odd 1 0 the the divide ratio is 3 4 If apb_clk_div_factor 2 and apb_clk_div_factor_odd 1 the the divide ratio is 4 5 If apb_clk_div_factor 2 and apb_clk_div_factor_odd 0 the the divide ratio is 5 6 If apb_clk_div_factor 4 and apb_clk_d...

Page 221: ...d N 1 one lower than the above mentioned divide factors If apb_clk_div_factor 1 and apb_clk_div_factor_odd 1 0 the the divide ratio is 3 4 If apb_clk_div_factor 2 and apb_clk_div_factor_odd 1 the the divide ratio is 4 5 If apb_clk_div_factor 2 and apb_clk_div_factor_odd 0 the the divide ratio is 5 6 If apb_clk_div_factor 4 and apb_clk_div_factor_odd 1 the the divide ratio is 6 7 If apb_clk_div_fac...

Page 222: ...odd 0 the the divide ratio is 5 6 If apb_clk_div_factor 4 and apb_clk_div_factor_odd 1 the the divide ratio is 6 7 If apb_clk_div_factor 4 and apb_clk_div_factor_odd 0 the the divide ratio is 7 8 If apb_clk_div_factor 8 and apb_clk_div_factor_odd 1 the the divide ratio is 8 9 If apb_clk_div_factor 8 and apb_clk_div_factor_odd 0 the the divide ratio is 9 10 If apb_clk_div_factor 16 and apb_clk_div_...

Page 223: ...tions Bit Field Type Reset Description 7 0 APB_CLK_LFSR_ SEED_VAL 7 0 R W ABh LFSR load Need to be used along with apb_clk_lfsr_load register 2 3 116 Register C6h offset C6h reset CDh Figure 2 157 Register C6h 7 6 5 4 3 2 1 0 APB_CLK_LFSR_SEED_VAL 15 8 R W CDh LEGEND R W Read Write W Write only n value after reset Table 2 160 Register C6 Field Descriptions Bit Field Type Reset Description 7 0 APB_...

Page 224: ...hich overrides the pin sync_n2 Need to be used along with dac_jesd_sync_n2_spi_ovr register 3 3 DAC_JESD_SYNC _N1_SPI_OVR R W 0h Override the dac_jesd sync_n1 pin going out with dac_jesd_sync_n1_spi_val 2 2 DAC_JESD_SYNC _N1_SPI_VAL R W 0h spi based dac_jesd sync_n0 which overrides the pin sync_n1 Need to be used along with dac_jesd_sync_n1_spi_ovr register 1 1 DAC_JESD_SYNC _N0_SPI_OVR R W 0h Ove...

Page 225: ...be sent on sync_n3 pin 0 lane01_sync_n 1 lane23_sync_n 2 lane45_sync_n 3 lane67_sync_n 5 4 DAC_JESD_SYNC _N2_MUX_SEL R W 2h Select which set of lanes dac_jesd sync_n pin to be sent on sync_n2 pin 0 lane01_sync_n 1 lane23_sync_n 2 lane45_sync_n 3 lane67_sync_n 3 2 DAC_JESD_SYNC _N1_MUX_SEL R W 1h Select which set of lanes dac_jesd sync_n pin to be sent on sync_n1 pin 0 lane01_sync_n 1 lane23_sync_n...

Page 226: ... 2T1_TXC_B0_Q 13 sel 2T1_TXC_B1_Q 14 sel 2T1_TXD_B0_Q 15 sel 2T1_TXD_B1_Q Refer to the configuration guide for mode details 3 0 MUX_SEL_FOR_T XA_B0_I R W 0h Selects the JESD stream that is to be routed to jesd TXA_B0_I 0 sel 2T0_TXA_B0_I 1 sel 2T0_TXA_B1_I 2 sel 2T0_TXB_B0_I 3 sel 2T0_TXB_B1_I 4 sel 2T0_TXC_B0_I 5 sel 2T0_TXC_B1_I 6 sel 2T0_TXD_B0_I 7 sel 2T0_TXD_B1_I 8 sel 2T1_TXA_B0_I 9 sel 2T1_...

Page 227: ... 2T1_TXC_B0_Q 13 sel 2T1_TXC_B1_Q 14 sel 2T1_TXD_B0_Q 15 sel 2T1_TXD_B1_Q Refer to the configuration guide for mode details 3 0 MUX_SEL_FOR_T XA_B1_I R W 1h Selects the JESD stream that is to be routed to jesd TXA_B1_I 0 sel 2T0_TXA_B0_I 1 sel 2T0_TXA_B1_I 2 sel 2T0_TXB_B0_I 3 sel 2T0_TXB_B1_I 4 sel 2T0_TXC_B0_I 5 sel 2T0_TXC_B1_I 6 sel 2T0_TXD_B0_I 7 sel 2T0_TXD_B1_I 8 sel 2T1_TXA_B0_I 9 sel 2T1_...

Page 228: ... 2T1_TXC_B0_Q 13 sel 2T1_TXC_B1_Q 14 sel 2T1_TXD_B0_Q 15 sel 2T1_TXD_B1_Q Refer to the configuration guide for mode details 3 0 MUX_SEL_FOR_T XB_B0_I R W 2h Selects the JESD stream that is to be routed to jesd TXB_B0_I 0 sel 2T0_TXA_B0_I 1 sel 2T0_TXA_B1_I 2 sel 2T0_TXB_B0_I 3 sel 2T0_TXB_B1_I 4 sel 2T0_TXC_B0_I 5 sel 2T0_TXC_B1_I 6 sel 2T0_TXD_B0_I 7 sel 2T0_TXD_B1_I 8 sel 2T1_TXA_B0_I 9 sel 2T1_...

Page 229: ... 2T1_TXC_B0_Q 13 sel 2T1_TXC_B1_Q 14 sel 2T1_TXD_B0_Q 15 sel 2T1_TXD_B1_Q Refer to the configuration guide for mode details 3 0 MUX_SEL_FOR_T XB_B1_I R W 3h Selects the JESD stream that is to be routed to jesd TXB_B1_I 0 sel 2T0_TXA_B0_I 1 sel 2T0_TXA_B1_I 2 sel 2T0_TXB_B0_I 3 sel 2T0_TXB_B1_I 4 sel 2T0_TXC_B0_I 5 sel 2T0_TXC_B1_I 6 sel 2T0_TXD_B0_I 7 sel 2T0_TXD_B1_I 8 sel 2T1_TXA_B0_I 9 sel 2T1_...

Page 230: ... 2T1_TXC_B0_Q 13 sel 2T1_TXC_B1_Q 14 sel 2T1_TXD_B0_Q 15 sel 2T1_TXD_B1_Q Refer to the configuration guide for mode details 3 0 MUX_SEL_FOR_T XC_B0_I R W 4h Selects the JESD stream that is to be routed to jesd TXC_B0_I 0 sel 2T0_TXA_B0_I 1 sel 2T0_TXA_B1_I 2 sel 2T0_TXB_B0_I 3 sel 2T0_TXB_B1_I 4 sel 2T0_TXC_B0_I 5 sel 2T0_TXC_B1_I 6 sel 2T0_TXD_B0_I 7 sel 2T0_TXD_B1_I 8 sel 2T1_TXA_B0_I 9 sel 2T1_...

Page 231: ... 2T1_TXC_B0_Q 13 sel 2T1_TXC_B1_Q 14 sel 2T1_TXD_B0_Q 15 sel 2T1_TXD_B1_Q Refer to the configuration guide for mode details 3 0 MUX_SEL_FOR_T XC_B1_I R W 5h Selects the JESD stream that is to be routed to jesd TXC_B1_I 0 sel 2T0_TXA_B0_I 1 sel 2T0_TXA_B1_I 2 sel 2T0_TXB_B0_I 3 sel 2T0_TXB_B1_I 4 sel 2T0_TXC_B0_I 5 sel 2T0_TXC_B1_I 6 sel 2T0_TXD_B0_I 7 sel 2T0_TXD_B1_I 8 sel 2T1_TXA_B0_I 9 sel 2T1_...

Page 232: ... 2T1_TXC_B0_Q 13 sel 2T1_TXC_B1_Q 14 sel 2T1_TXD_B0_Q 15 sel 2T1_TXD_B1_Q Refer to the configuration guide for mode details 3 0 MUX_SEL_FOR_T XD_B0_I R W 6h Selects the JESD stream that is to be routed to jesd TXD_B0_I 0 sel 2T0_TXA_B0_I 1 sel 2T0_TXA_B1_I 2 sel 2T0_TXB_B0_I 3 sel 2T0_TXB_B1_I 4 sel 2T0_TXC_B0_I 5 sel 2T0_TXC_B1_I 6 sel 2T0_TXD_B0_I 7 sel 2T0_TXD_B1_I 8 sel 2T1_TXA_B0_I 9 sel 2T1_...

Page 233: ...1 sel 2T0_TXA_B1_I 2 sel 2T0_TXB_B0_I 3 sel 2T0_TXB_B1_I 4 sel 2T0_TXC_B0_I 5 sel 2T0_TXC_B1_I 6 sel 2T0_TXD_B0_I 7 sel 2T0_TXD_B1_I 8 sel 2T1_TXA_B0_I 9 sel 2T1_TXA_B1_I 10 sel 2T1_TXB_B0_I 11 sel 2T1_TXB_B1_I 12 sel 2T1_TXC_B0_I 13 sel 2T1_TXC_B1_I 14 sel 2T1_TXD_B0_I 15 sel 2T1_TXD_B1_I Refer to the configuration guide for mode details 2 3 129 Register D4h offset D4h reset 0h Figure 2 170 Regis...

Page 234: ...CL K_EN_OVR TXB_DAC_CLK _EN_OVR TXA_DAC_CLK _EN_OVR R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 174 Register 155 Field Descriptions Bit Field Type Reset Description 7 7 TXD_DAC_CLK_E N_OVR R W 0h Register to gate the TXD clocks used internally and going to TX_TOP Need to be used along with txd_dac_clk_en_val register 6 6 TXC_DAC_CLK_E N_OVR R W 0h Reg...

Page 235: ...only n value after reset Table 2 176 Register 157 Field Descriptions Bit Field Type Reset Description 7 4 TXD_DAC_CLK_E N_VAL R W Fh Register to gate the TXD clocks used internally and going to TX_TOP Need to be used along with txd_dac_clk_en_ovr register bit0 TXD_B0_I bit1 TXD_B0_Q bit2 TXD_B1_I bit3 TXD_B1_Q 3 0 TXC_DAC_CLK_E N_VAL R W Fh Register to gate the TXC clocks used internally and going...

Page 236: ..._READY indicator 2 mask SRX3 PHY_READY indicator 1 mask SRX2 PHY_READY indicator 0 mask SRX1 PHY_READY indicator 3 0 SERDESAB_PHY_ READY_CLEAR R W 0h register to clear SerdesAB SRX1 SRX2 SRX3 and SRX4 PHY READY indicator register bits 3 clear SRX4 PHY_READY indicator 2 clear SRX3 PHY_READY indicator 1 clear SRX2 PHY_READY indicator 0 clear SRX1 PHY_READY indicator 2 3 135 Register 15Ah offset 15Ah...

Page 237: ...clear SRX5 PHY READY 2 3 137 Register 15Ch offset 15Ch reset 0h Figure 2 178 Register 15Ch 7 6 5 4 3 2 1 0 SERDESCD_P LL_LOSS_OF_ LOCK_MASK SERDESCD_P LL_LOSS_OF_ LOCK_CLEAR SERDESAB_P LL_LOSS_OF_ LOCK_MASK SERDESAB_P LL_LOSS_OF_ LOCK_CLEAR R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 181 Register 15C Field Descriptions Bit Field Type Reset Description...

Page 238: ... LEGEND R W Read Write W Write only n value after reset Table 2 183 Register 15E Field Descriptions Bit Field Type Reset Description 7 4 SERDESCD_PHY_ READY R 0h register indicating SerdesCD SRX5 SRX6 SRX7 and SRX8 PHY READY register bits 3 SRX8 PHY READY 2 SRX7 PHY READY 1 SRX6 PHY READY 0 SRX5 PHY READY 3 0 SERDESCD_LOS_ INDICATOR R 0h register indicating SerdesCD SRX5 SRX6 SRX7 and SRX8 LOS ind...

Page 239: ...f and clock sticky bits of rrf jesd async fifo 4 4 DBG_FBAB_AFIF O_DBG_CFG_CLR R W 0h To reset sysref and clock sticky bits of rrf jesd async fifo 3 3 DBG_RXD_AFIFO _DBG_CFG_CLR R W 0h To reset sysref and clock sticky bits of rrf jesd async fifo 2 2 DBG_RXC_AFIFO _DBG_CFG_CLR R W 0h To reset sysref and clock sticky bits of rrf jesd async fifo 1 1 DBG_RXB_AFIFO _DBG_CFG_CLR R W 0h To reset sysref a...

Page 240: ... 164h reset 0h Figure 2 185 Register 164h 7 6 5 4 3 2 1 0 DBG_RXB_ASYNC_FIFO_ALARM_CLR DBG_RXA_ASYNC_FIFO_ALARM_CLR R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 188 Register 164 Field Descriptions Bit Field Type Reset Description 7 4 DBG_RXB_ASYNC _FIFO_ALARM_CL R R W 0h clear for RXB to JESD Async FIFO debug debug alarm Only bit0 is valid 3 0 DBG_RXA_ASYNC _FIFO_AL...

Page 241: ...68h 7 6 5 4 3 2 1 0 DBG_RXB_ASYNC_FIFO_ALARM_MASK DBG_RXA_ASYNC_FIFO_ALARM_MASK R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 191 Register 168 Field Descriptions Bit Field Type Reset Description 7 4 DBG_RXB_ASYNC _FIFO_ALARM_M ASK R W 0h mask for RXB to JESD Async FIFO debug alarm Only bit0 is valid 3 0 DBG_RXA_ASYNC _FIFO_ALARM_M ASK R W 0h mask for RXA to JESD Asyn...

Page 242: ... 191 Register 16Ch 7 6 5 4 3 2 1 0 DBG_RXB_ASYNC_FIFO_ALARM DBG_RXA_ASYNC_FIFO_ALARM R 0h R 0h LEGEND R W Read Write W Write only n value after reset Table 2 194 Register 16C Field Descriptions Bit Field Type Reset Description 7 4 DBG_RXB_ASYNC _FIFO_ALARM R 0h overflow underflow flag for RX B to JESD Async fifo Only bit0 is valid 3 0 DBG_RXA_ASYNC _FIFO_ALARM R 0h overflow underflow flag for RX A...

Page 243: ... Register 170h offset 170h reset 0h Figure 2 194 Register 170h 7 6 5 4 3 2 1 0 DBG_RXB_AFIFO_SYSREF_SPACING DBG_RXA_AFIFO_SYSREF_SPACING R 0h R 0h LEGEND R W Read Write W Write only n value after reset Table 2 197 Register 170 Field Descriptions Bit Field Type Reset Description 7 4 DBG_RXB_AFIFO _SYSREF_SPACI NG R 0h Debug For async fifo sysref spacing 3 0 DBG_RXA_AFIFO _SYSREF_SPACI NG R 0h Debug...

Page 244: ...AFI FO_SYS_REF_ WR_STICKY DBG_RXA_AFI FO_RD_CLK_T OGGLE_STICK Y DBG_RXA_AFI FO_WR_CLK_ TOGGLE_STIC KY DBG_RXA_AFI FO_SYS_REF_ RD_STICKY DBG_RXA_AFI FO_SYS_REF_ WR_STICKY R 0h R 0h R 0h R 0h R 0h R 0h R 0h R 0h LEGEND R W Read Write W Write only n value after reset Table 2 200 Register 174 Field Descriptions Bit Field Type Reset Description 7 7 DBG_RXB_AFIFO _RD_CLK_TOGGL E_STICKY R 0h RXB to JESD ...

Page 245: ...f monitor 4 4 DBG_RXD_AFIFO _SYS_REF_WR_S TICKY R 0h RXD to JESD Async FIFO wr sysref monitor 3 3 DBG_RXC_AFIFO _RD_CLK_TOGGL E_STICKY R 0h RXC to JESD Async FIFO rd clk monitor 2 2 DBG_RXC_AFIFO _WR_CLK_TOGGL E_STICKY R 0h RXC to JESD Async FIFO wr clk monitor 1 1 DBG_RXC_AFIFO _SYS_REF_RD_S TICKY R 0h RXC to JESD Async FIFO rd sysref monitor 0 0 DBG_RXC_AFIFO _SYS_REF_WR_S TICKY R 0h RXC to JESD...

Page 246: ...BG_FBAB_AFIF O_SYS_REF_WR_ STICKY R 0h FBAB to JESD Async FIFO wr sysref monitor 2 3 159 Register 180h offset 180h reset 0h Figure 2 200 Register 180h 7 6 5 4 3 2 1 0 ADC_SYNC_N_FROM_PIN R 0h LEGEND R W Read Write W Write only n value after reset Table 2 203 Register 180 Field Descriptions Bit Field Type Reset Description 5 0 ADC_SYNC_N_FR OM_PIN R 0h Spi monitor of adc_sync_n input ports Bit0 For...

Page 247: ...after reset Table 2 206 Register 183 Field Descriptions Bit Field Type Reset Description 7 0 DAC_SYNC_N_PR E_MUX R 0h Spi monitor of dac_sync_n pins from lanes before sync_n mux 2 3 163 Register 188h offset 188h reset 0h Figure 2 204 Register 188h 7 6 5 4 3 2 1 0 DBG_RX_READ_OUT_REG1 7 0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 207 Register 188 Field Descriptions Bit Fie...

Page 248: ...pe Reset Description 7 0 DBG_RX_READ_O UT_REG2 7 0 R 0h Data from first 4R mux output i e mux_sel_rxa_b1_i_for_2r1f_ab is sent to this status register to check for data toggling dbg_rx_read_out_reg1 and dbg_rx_read_out_reg2 has two consecutive samples 2 3 166 Register 18Bh offset 18Bh reset 0h Figure 2 207 Register 18Bh 7 6 5 4 3 2 1 0 DBG_RX_READ_OUT_REG2 15 8 R 0h LEGEND R W Read Write W Write o...

Page 249: ...pe Reset Description 7 0 DBG_FB_READ_O UT_REG1 15 8 R 0h Data from first 2F mux output i e mux_sel_fbab_i0_for_2r1f_ab is sent to this status register to check for data toggling dbg_fb_read_out_reg1 and dbg_fb_read_out_reg2 has two consecutive samples 2 3 169 Register 18Eh offset 18Eh reset 0h Figure 2 210 Register 18Eh 7 6 5 4 3 2 1 0 DBG_FB_READ_OUT_REG2 7 0 R 0h LEGEND R W Read Write W Write on...

Page 250: ...tus register to check for data toggling dbg_tx_read_out_reg1 and dbg_tx_read_out_reg2 has two consecutive samples 2 3 172 Register 191h offset 191h reset 0h Figure 2 213 Register 191h 7 6 5 4 3 2 1 0 DBG_TX_READ_OUT_REG1 15 8 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 216 Register 191 Field Descriptions Bit Field Type Reset Description 7 0 DBG_TX_READ_O UT_REG1 15 8 R 0h D...

Page 251: ...r 194 Field Descriptions Bit Field Type Reset Description 5 5 DBG_FB_ON_C R 0h Sig valid from TDD controller is assigned to this status register post synchronizer 4 4 DBG_FB_ON_A R 0h Sig valid from TDD controller is assigned to this status register post synchronizer 3 3 DBG_RX_ON_D R 0h Sig valid from TDD controller is assigned to this status register post synchronizer 2 2 DBG_RX_ON_C R 0h Sig va...

Page 252: ...ure 2 218 Register 19Ch 7 6 5 4 3 2 1 0 SPARE_OUT_REG0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 221 Register 19C Field Descriptions Bit Field Type Reset Description 7 0 SPARE_OUT_REG 0 R W 0h spare registers out 2 3 178 Register 19Dh offset 19Dh reset 0h Figure 2 219 Register 19Dh 7 6 5 4 3 2 1 0 SPARE_OUT_REG1 R W 0h LEGEND R W Read Write W Write only n value after re...

Page 253: ...h Figure 2 222 Register 1A0h 7 6 5 4 3 2 1 0 SPARE_OUT_REG4 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 225 Register 1A0 Field Descriptions Bit Field Type Reset Description 7 0 SPARE_OUT_REG 4 R W 0h spare registers out 2 3 182 Register 1A1h offset 1A1h reset 0h Figure 2 223 Register 1A1h 7 6 5 4 3 2 1 0 SPARE_OUT_REG5 R W 0h LEGEND R W Read Write W Write only n value aft...

Page 254: ...G 7 R W 0h spare registers out 2 3 185 Register 1A4h offset 1A4h reset 0h Figure 2 226 Register 1A4h 7 6 5 4 3 2 1 0 SPARE_IN 7 0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 229 Register 1A4 Field Descriptions Bit Field Type Reset Description 7 0 SPARE_IN 7 0 R 0h spare registers in 2 3 186 Register 1A5h offset 1A5h reset 0h Figure 2 227 Register 1A5h 7 6 5 4 3 2 1 0 SPARE_...

Page 255: ...ter 1A6 Field Descriptions Bit Field Type Reset Description 7 0 SPARE_IN 23 16 R 0h spare registers in 2 3 188 Register 1A7h offset 1A7h reset 0h Figure 2 229 Register 1A7h 7 6 5 4 3 2 1 0 SPARE_IN 31 24 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 232 Register 1A7 Field Descriptions Bit Field Type Reset Description 7 0 SPARE_IN 31 24 R 0h spare registers in ...

Page 256: ..._FIFO_TX3_OF FSET_OVR MAPPER_SYNC _FIFO_TX2_OF FSET_OVR MAPPER_SYNC _FIFO_TX1_OF FSET_OVR 29h MAPPER_SYNC_FIFO_TX2_OFFSET_VAL MAPPER_SYNC_FIFO_TX1_OFFSET_VAL 2Ah MAPPER_SYNC_FIFO_TX4_OFFS ET_VAL MAPPER_SYNC_FIFO_TX3_OFFS ET_VAL 2Bh MAPPER_SYNC _FIFO_TX4_MO DE_VAL MAPPER_SYNC _FIFO_TX3_MO DE_VAL MAPPER_SYNC_FIFO_TX2_MODE_VAL MAPPER_SYNC_FIFO_TX1_MODE_VAL 2Ch ROOT_CLK_TX1_DIV_M 2Dh ROOT_CLK_TX1_DIV_...

Page 257: ..._CF 5Dh LINK1_RES1 5Eh LINK1_RES2 5Fh LINK1_ILA_CON FIG_OVERRIDE LINK1_CTRL_C ONFIG_OVERRI DE LINK0_ILA_CON FIG_OVERRIDE 60h LID0 61h LID1 62h LID2 63h LID3 64h JESD_CLEAR_DATA LANE_ENA 65h K_COUNTER_THRESH 66h V_COUNTER_THRESH 67h I_COUNTER_THRESH 68h LINK0_RBD_M1 7 0 69h LINK0_RBD_M1 15 8 6Ah LINK1_RBD_M1 7 0 6Bh LINK1_RBD_M1 15 8 6Ch LINK0_K_M1 6Dh LINK1_K_M1 6Eh LINK0_BUFFER_READ_PTR_OFFSET LI...

Page 258: ..._COUNTER_ALL_LANES_READY 7 0 91h LANE0_F_COUNTER_ALL_LANES_READY 15 8 92h LANE1_F_COUNTER_ALL_LANES_READY 7 0 93h LANE1_F_COUNTER_ALL_LANES_READY 15 8 94h LANE2_F_COUNTER_ALL_LANES_READY 7 0 95h LANE2_F_COUNTER_ALL_LANES_READY 15 8 96h LANE3_F_COUNTER_ALL_LANES_READY 7 0 97h LANE3_F_COUNTER_ALL_LANES_READY 15 8 98h LINK1_SYSREF_CNT_ON_RELEASE_OPPORTUNITY LINK0_SYSREF_CNT_ON_RELEASE_OPPORTUNITY 99h...

Page 259: ... JESD_SHORTTEST_INPUT6 15 8 C6h JESD_SHORTTEST_INPUT7 7 0 C7h JESD_SHORTTEST_INPUT7 15 8 C8h JESD_SHORTTEST_INPUT8 7 0 C9h JESD_SHORTTEST_INPUT8 15 8 CAh JESD_SHORTTEST_INPUT9 7 0 CBh JESD_SHORTTEST_INPUT9 15 8 CCh JESD_SHORTTEST_INPUT10 7 0 CDh JESD_SHORTTEST_INPUT10 15 8 CEh JESD_SHORTTEST_INPUT11 7 0 CFh JESD_SHORTTEST_INPUT11 15 8 D0h JESD_SHORTTEST_INPUT12 7 0 D1h JESD_SHORTTEST_INPUT12 15 8 ...

Page 260: ...P_CLEAR 7 0 111h ALARMS_TO_PAP_CLEAR 15 8 112h ALARMS_TO_PAP_CLEAR 23 16 113h ALARMS_TO_PAP_CLEAR 31 24 114h ALARMS_TO_PAP_CLEAR 39 32 115h ALARMS_TO_PAP_CLEAR 47 40 116h ALARMS_TO_PAP_CLEAR 55 48 117h ALARMS_TO_PAP_CLEAR 63 56 118h ALARMS 7 0 119h ALARMS 15 8 11Ah ALARMS 23 16 11Bh ALARMS 31 24 11Ch ALARMS 39 32 11Dh ALARMS 47 40 11Eh ALARMS 55 48 11Fh ALARMS 63 56 120h ALARMS_TO_PAP 7 0 121h ALA...

Page 261: ... CTRL_TX2_JESD_CLK_DIV2_P2 CTRL_TX2_JESD_CLK_DIV2_P1 CTRL_TX2_JESD_CLK_DIV2_P0 148h MAPPER_SYNC_FIFO_TX1_OFFSET_S4TO2 MAPPER_SYNC_FIFO_TX1_OFFSET_S4TO4 149h MAPPER_SYNC_FIFO_TX1_OFFSET_S2TO2 MAPPER_SYNC_FIFO_TX1_OFFSET_S4TO1 14Ah MAPPER_SYNC_FIFO_TX1_OFFSET_S1TO1 MAPPER_SYNC_FIFO_TX1_OFFSET_S2TO1 14Ch MAPPER_SYNC_FIFO_TX2_OFFSET_S4TO2 MAPPER_SYNC_FIFO_TX2_OFFSET_S4TO4 14Dh MAPPER_SYNC_FIFO_TX2_OFF...

Page 262: ...3 Skip one sysref pulse then use only the next one 4 Skip one sysref pulse then use all pulses 5 skip two sysrefs and then use one 6 skip two sysrefs and then use all 2 4 3 Register 22h offset 22h reset 45h Figure 2 232 Register 22h 7 6 5 4 3 2 1 0 LINK0_JESD_SAMPLE_MODE LINK0_JESD_MODE R W 1h R W 5h LEGEND R W Read Write W Write only n value after reset Table 2 236 Register 22 Field Descriptions ...

Page 263: ...820 7 48410 8 28810 9 28610 10 48610 11 2 8 12 1 0 12 24820 13 48310 14 24310 15 44310 16 1 8 12 1 0 17 1 8 16 1 0 18 42111 19 42220 20 NA 21 NA 22 22210 23 12310 24 22310 25 12410 26 12610 27 48820 28 4 16 8 1 0 29 2 16 12 1 0 30 4 16 12 1 0 31 2 16 16 1 0 32 1 16 24 1 0 33 1 8 24 1 0 34 2 16 24 1 0 35 12620 36 24620 37 48620 38 22840 39 44840 40 NA 41 NA 42 NA 43 NA 44 NA 45 NA 46 NA 47 NA 48 NA...

Page 264: ... S 1 1 SB S 1 2 SB S 2 3 SB S 4 5 0 LINK1_JESD_MOD E R W 5h Defines the LMFSHd mode for path for lanes 2 3 6 7 path 0 24410 1 14810 2 14610 3 24610 4 1 4 12 1 0 5 44210 6 12820 7 48410 8 28810 9 28610 10 48610 11 2 8 12 1 0 12 24820 13 48310 14 24310 15 44310 16 1 8 12 1 0 17 1 8 16 1 0 18 42111 19 42220 20 NA 21 NA 22 22210 23 12310 24 22310 25 12410 26 12610 27 48820 28 4 16 8 1 0 29 2 16 12 1 0...

Page 265: ... R W 1h UNUSED 3 3 FIFO_ERROR_ZE ROS_DATA_ENA R W 1h When asserted FIFO errors zero the data out of the JESD block For test purposes this could be turned off to allow test patterns in the FIFO 2 2 ZERO_INVALID_D ATA R W 1h When asserted the data from the JESD block is zeroed in the mapper to prevent goofy output from the DAC For test purposes this bit should be desasserted but in normal use cases ...

Page 266: ...with gearbox_init_state_ovr 0 no override 1 override 2 2 GEARBOX_INIT_S TATE_LANE2_VAL R W 1h Override lane2 6 sysref based gearbox init_state with spi based init_state To be used along with gearbox_init_state_ovr 0 no override 1 override 1 1 GEARBOX_INIT_S TATE_LANE1_VAL R W 1h Override lane1 5 sysref based gearbox init_state with spi based init_state To be used along with gearbox_init_state_ovr ...

Page 267: ...N C_FIFO_TX3_1 _EN MAPPER_SYN C_FIFO_TX2_2 _EN MAPPER_SYN C_FIFO_TX2_1 _EN MAPPER_SYN C_FIFO_TX1_2 _EN MAPPER_SYN C_FIFO_TX1_1 _EN R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 241 Register 27 Field Descriptions Bit Field Type Reset Description 7 7 MAPPER_SYNC_F IFO_TX4_2_EN R W 0h TESTMODE 6 6 MAPPER_SYNC_F IFO_TX4_1_EN R W ...

Page 268: ..._fifo_tx3_offset_val 1 1 MAPPER_SYNC_F IFO_TX2_OFFSET _OVR R W 0h Enable mapper sync fifo offset override through this register To be used along with mapper_sync_fifo_tx2_offset_val 0 0 MAPPER_SYNC_F IFO_TX1_OFFSET _OVR R W 0h Enable mapper sync fifo offset override through this register To be used along with mapper_sync_fifo_tx1_offset_val 2 4 10 Register 29h offset 29h reset 88h Figure 2 239 Reg...

Page 269: ...W Read Write W Write only n value after reset Table 2 245 Register 2B Field Descriptions Bit Field Type Reset Description 7 7 MAPPER_SYNC_F IFO_TX4_MODE_ VAL R W 0h UNUSED 6 6 MAPPER_SYNC_F IFO_TX3_MODE_ VAL R W 0h UNUSED 5 3 MAPPER_SYNC_F IFO_TX2_MODE_ VAL R W 0h set mapper sync fifo mode through this register To be used along with mapper_sync_fifo_tx2_mode_ovr 2 0 MAPPER_SYNC_F IFO_TX1_MODE_ VAL...

Page 270: ...ister 2Eh 7 6 5 4 3 2 1 0 ROOT_CLK_TX2_DIV_M R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 248 Register 2E Field Descriptions Bit Field Type Reset Description 4 0 ROOT_CLK_TX2_ DIV_M R W 1h For lanes 2 3 6 7 M value in Divide ratio of M N for generating the root clock for DAC_JESD from 48x clock All the other internal clocks like DUC_WR_CLK and JESD_RX_CLK are derieved from...

Page 271: ...1_DIV_N_M1 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 251 Register 31 Field Descriptions Bit Field Type Reset Description 4 0 DUC_CLK_TX1_DI V_N_M1 R W 0h For lanes 0 1 4 5 N_M1 value in Divide ratio of M N for generating the DUC_WR_CLK for DAC_JESD from ROOT_CLK 2 4 19 Register 32h offset 32h reset 1h Figure 2 248 Register 32h 7 6 5 4 3 2 1 0 DUC_CLK_TX2_DIV_M R W 1h LE...

Page 272: ... 0 1 4 5 M value in Divide ratio of M N for generating the JESD_RX_CLK for DAC_JESD from ROOT_CLK 2 4 22 Register 35h offset 35h reset 0h Figure 2 251 Register 35h 7 6 5 4 3 2 1 0 JESD_CLK_TX1_DIV_N_M1 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 255 Register 35 Field Descriptions Bit Field Type Reset Description 4 0 JESD_CLK_TX1_D IV_N_M1 R W 0h For lanes 0 1 4 5 N_M1 val...

Page 273: ...I V_DITHER_EN DUC_CLK_DIV _DITHER_EN DUC_CLK_IO_ DIV_DITHER_ EN TX_ROOT_CL K_DIV_DITHE R_EN R W 0h R W 0h R W 0h R W 1h R W 1h R W 1h R W 1h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 258 Register 38 Field Descriptions Bit Field Type Reset Description 7 7 CLK_DIV_LFSR_S EED_LOAD R W 0h LFSR load override to load lfsr_seed_val into the LFSR module To be used along with cl...

Page 274: ...LEGEND R W Read Write W Write only n value after reset Table 2 260 Register 3A Field Descriptions Bit Field Type Reset Description 7 0 CLK_DIV_LFSR_S EED_VAL 15 8 R W 0h LFSR load value to load lfsr_seed_val into the LFSR module To be used along with clk_div_lfsr_seed_ovr 2 4 28 Register 3Bh offset 3Bh reset 2h Figure 2 257 Register 3Bh 7 6 5 4 3 2 1 0 CLK_DIV_LFSR_SEED_VAL 23 16 R W 2h LEGEND R W...

Page 275: ...iption 7 4 SERDES_FIFO_O FFSET_LANE3 R W 8h Used to set the difference between read and write pointers in the SERDES JESD FIFO for lane3 lane7 3 0 SERDES_FIFO_O FFSET_LANE2 R W 8h Used to set the difference between read and write pointers in the SERDES JESD FIFO for lane2 lane6 2 4 31 Register 3Eh offset 3Eh reset 0h Figure 2 260 Register 3Eh 7 6 5 4 3 2 1 0 SERDES_FIFO_ERROR_DIFF2_UNMASK R W 0h L...

Page 276: ...ed to convert 33 bits from gearbox to 66 bits for IP use 0 0 1 1 2 2 3 3 2 4 33 Register 40h offset 40h reset 0h Figure 2 262 Register 40h 7 6 5 4 3 2 1 0 COMMA_ALIG N_TIMER_EN COMMA_ALIG N_REALIGN_M ASK LINK1_COMM A_ALIGN_LOC K_RESET_DIS ABLE LINK0_COMM A_ALIGN_LOC K_RESET_DIS ABLE LINK1_COMM A_ALIGN_RES ET LINK0_COMM A_ALIGN_RES ET R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write ...

Page 277: ...it Field Type Reset Description 6 0 COMMA_ALIGN_B IT_COUNTER_INI T R W 0h Load the internal index counter with this value 2 4 35 Register 42h offset 42h reset 10h Figure 2 264 Register 42h 7 6 5 4 3 2 1 0 COMMA_ALIGN_VALID_THRESH R W 10h LEGEND R W Read Write W Write only n value after reset Table 2 268 Register 42 Field Descriptions Bit Field Type Reset Description 6 0 COMMA_ALIGN_V ALID_THRESH R...

Page 278: ... W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 271 Register 45 Field Descriptions Bit Field Type Reset Description 7 4 LINK0_BID R W 0h Lane configuration 3 0 LINK0_ADJCNT R W 0h Lane configuration 2 4 39 Register 46h offset 46h reset 0h Figure 2 268 Register 46h 7 6 5 4 3 2 1 0 LINK0_ADJDIR LINK0_PHADJ R W 0h R W 0h LEGEND R W Read Write W Write only n value after res...

Page 279: ... 0 LINK0_ILA_F_M1 R W 3h JESD F 1 configuration value used only for ILA checking may be set independently of the actual JESD mode 2 4 42 Register 49h offset 49h reset 1Fh Figure 2 271 Register 49h 7 6 5 4 3 2 1 0 LINK0_ILA_K_M1 R W 1Fh LEGEND R W Read Write W Write only n value after reset Table 2 275 Register 49 Field Descriptions Bit Field Type Reset Description 7 0 LINK0_ILA_K_M1 R W 1Fh JESD K...

Page 280: ...d Write W Write only n value after reset Table 2 278 Register 4C Field Descriptions Bit Field Type Reset Description 7 5 LINK0_SUBCLASS V R W 1h Selects the JESD subclass Note 1 is subclass 1 and 0 is subclass 0 they are the only modes supported not used for operation but used for configuration See min_latency_ena for use in subclass 0 4 0 LINK0_ILA_NPRIM E_M1 R W Fh JESD N 1 configuration value u...

Page 281: ...INK0_CF R W 0h Lane configuration 2 4 48 Register 4Fh offset 4Fh reset 0h Figure 2 277 Register 4Fh 7 6 5 4 3 2 1 0 LINK0_RES1 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 281 Register 4F Field Descriptions Bit Field Type Reset Description 7 0 LINK0_RES1 R W 0h Lane configuration 2 4 49 Register 50h offset 50h reset 0h Figure 2 278 Register 50h 7 6 5 4 3 2 1 0 LINK0_RES2 R...

Page 282: ... 7 0 LINK1_DID R W 0h Lane configuration 2 4 52 Register 53h offset 53h reset 0h Figure 2 281 Register 53h 7 6 5 4 3 2 1 0 LINK1_BID LINK1_ADJCNT R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 285 Register 53 Field Descriptions Bit Field Type Reset Description 7 4 LINK1_BID R W 0h Lane configuration 3 0 LINK1_ADJCNT R W 0h Lane configuration 2 4 53 Register 54h offset...

Page 283: ...e 2 284 Register 56h 7 6 5 4 3 2 1 0 LINK1_ILA_F_M1 R W 3h LEGEND R W Read Write W Write only n value after reset Table 2 288 Register 56 Field Descriptions Bit Field Type Reset Description 7 0 LINK1_ILA_F_M1 R W 3h JESD F 1 configuration value used only for ILA checking may be set independently of the actual JESD mode 2 4 56 Register 57h offset 57h reset 1Fh Figure 2 285 Register 57h 7 6 5 4 3 2 ...

Page 284: ... the actual JESD mode 2 4 59 Register 5Ah offset 5Ah reset 2Fh Figure 2 288 Register 5Ah 7 6 5 4 3 2 1 0 LINK1_SUBCLASSV LINK1_ILA_NPRIME_M1 R W 1h R W Fh LEGEND R W Read Write W Write only n value after reset Table 2 292 Register 5A Field Descriptions Bit Field Type Reset Description 7 5 LINK1_SUBCLASS V R W 1h Selects the JESD subclass Note 1 is subclass 1 and 0 is subclass 0 they are the only m...

Page 285: ...ster 5C Field Descriptions Bit Field Type Reset Description 7 7 LINK1_ILA_HD R W 1h JESD HD configuration value used only for ILA checking may be set independently of the actual JESD mode 4 0 LINK1_CF R W 0h Lane configuration 2 4 62 Register 5Dh offset 5Dh reset 0h Figure 2 291 Register 5Dh 7 6 5 4 3 2 1 0 LINK1_RES1 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 295 Regist...

Page 286: ...ink1 ILA values with register based ILA values for 6 6 LINK1_CTRL_CON FIG_OVERRIDE R W 0h TESTMODE 5 5 LINK0_ILA_CONFI G_OVERRIDE R W 0h By default ILA values only L M F S Hd K N N are set by jesd_mode Set this bit to override the Link0 ILA values with register based ILA values for 2 4 65 Register 60h offset 60h reset 0h Figure 2 294 Register 60h 7 6 5 4 3 2 1 0 LID0 R W 0h LEGEND R W Read Write W...

Page 287: ... W Write only n value after reset Table 2 301 Register 63 Field Descriptions Bit Field Type Reset Description 4 0 LID3 R W 3h JESD Lane ID for lane3 7 2 4 69 Register 64h offset 64h reset Fh Figure 2 298 Register 64h 7 6 5 4 3 2 1 0 JESD_CLEAR_DATA LANE_ENA R W 0h R W Fh LEGEND R W Read Write W Write only n value after reset Table 2 302 Register 64 Field Descriptions Bit Field Type Reset Descripti...

Page 288: ... offset 67h reset 4h Figure 2 301 Register 67h 7 6 5 4 3 2 1 0 I_COUNTER_THRESH R W 4h LEGEND R W Read Write W Write only n value after reset Table 2 305 Register 67 Field Descriptions Bit Field Type Reset Description 3 0 I_COUNTER_THR ESH R W 4h JESDB invalid counter threshold for Code group synchronization JESDC UNUSED 2 4 73 Register 68h offset 68h reset 0h Figure 2 302 Register 68h 7 6 5 4 3 2...

Page 289: ... LEGEND R W Read Write W Write only n value after reset Table 2 308 Register 6A Field Descriptions Bit Field Type Reset Description 7 0 LINK1_RBD_M1 7 0 R W 0h This is the number of clock cycles one clock cycle freq LaneRate 40 for JESDB or LaneRate 33 for JESDC to release the data from the JESD RBD buffers if all the R characters JESDB or EMB lock JESDC across the used lanes have arrived for lane...

Page 290: ...Dh offset 6Dh reset 1Fh Figure 2 307 Register 6Dh 7 6 5 4 3 2 1 0 LINK1_K_M1 R W 1Fh LEGEND R W Read Write W Write only n value after reset Table 2 311 Register 6D Field Descriptions Bit Field Type Reset Description 7 0 LINK1_K_M1 R W 1Fh JESDB The number of frames in a multi frame for lanes 2 3 6 7 K should always set to integer multiple of 4 0 K 1 32 JESDC The number of multiblocks in extended m...

Page 291: ...TER R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 314 Register 70 Field Descriptions Bit Field Type Reset Description 7 0 LINK0_INIT_O_CO UNTER R W 0h For Lanes 0 1 4 5 on sysref to lmfc the internal o counter JESDB mb_counter JESDC can be loaded with init_o_counter value 2 4 82 Register 71h offset 71h reset 0h Figure 2 311 Register 71h 7 6 5 4 3 2 1 0 LINK0_INIT_F_COUNTER ...

Page 292: ...0h Figure 2 314 Register 74h 7 6 5 4 3 2 1 0 LINK1_AUTOL OAD_JESD_E RRCNT LINK0_AUTOL OAD_JESD_E RRCNT LINK1_SYNC_ ERROR_CNT_ CLR LINK0_SYNC_ ERROR_CNT_ CLR R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 318 Register 74 Field Descriptions Bit Field Type Reset Description 3 3 LINK1_AUTOLOA D_JESD_ERRCNT R W 0h For Lanes 2 3 6 7 when 1 the error count upda...

Page 293: ...eating ILA sequence 3 3 DISABLE_ERR_R EPORT R W 0h Assertion means that errors will not be reported on the sync_n output 2 2 MP_LINK_ENA R W 0h UNUSED 1 1 NO_LANE_SYNC R W 0h Assert if the TX side does not support lane initialization This way the RX wont flag errors in the configuration portion of the ILA 0 0 MIN_LATENCY_E NA R W 0h This is needed for subclass 0 support 2 4 87 Register 76h offset ...

Page 294: ...iframe alignment error bit6 JESDB frame alignment error bit5 JESDB link configuration error bit4 JESDB elastic buffer overflow bad RBD value bit3 JESDB elastic buffer match error The first non K doesnt match match_ctrl and match_data programmed values bit2 JESDB code synchronization error bit1 JESDB 8b 10b not in table code error Bit0 JESDB 8b 10b disparity error bit7 JESDC EoEMB alignment error b...

Page 295: ...nc header invalid error 11 or 00 received in expected sync header location Bit0 JESDC sync header CRC error 2 4 91 Register 7Ah offset 7Ah reset 0h Figure 2 320 Register 7Ah 7 6 5 4 3 2 1 0 LINK0_ERROR_ENA R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 324 Register 7A Field Descriptions Bit Field Type Reset Description 7 0 LINK0_ERROR_E NA R W 0h These bits select the errors...

Page 296: ...it0 JESDB 8b 10b disparity error bit7 JESDC EoEMB alignment error bit6 JESDC EoMB alignment error bit5 JESDC cmd data in crc mode not matching with spi register bits bit4 JESDC elastic buffer overflow bad RBD value bit3 JESDC TIED to 0 bit2 JESDC extended multiblock alignment error bit1 JESDC sync header invalid error 11 or 00 received in expected sync header location Bit0 JESDC sync header CRC er...

Page 297: ... over the error notification JESDC This bit selects whether the fixed ones error causes a sync request for lanes 2 3 6 7 0 0 LINK0_FRAME_SY NC_ERR_SYNC_R EQUEST_ENA R W 1h JESB This bit selects whether frame synchornization error generated due to continous K characters in middle of data causes a sync request for lanes 0 1 4 5 Sync requests take priority over the error notification JESDC This bit s...

Page 298: ... syncz signal and reset the links JESDC error count threshold for end of multiblock alignment error after which it will pull the syncz signal and reset the links 3 0 MULTIFRAME_ALI GN_ERR_CNT_TH RESH R W 1h JESDB error count threshold for multiframe alignment error after which it will pull the syncz signal and reset the links JESDC error count threshold for end of extended multiblock alignment err...

Page 299: ...ister 83h offset 83h reset 11h Figure 2 329 Register 83h 7 6 5 4 3 2 1 0 DEC_8B10B_DISP_ERR_CNT_THRESH DEC_8B10B_CODE_ERR_CNT_THRESH R W 1h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 333 Register 83 Field Descriptions Bit Field Type Reset Description 7 4 DEC_8B10B_DISP _ERR_CNT_THRE SH R W 1h JESDB error count threshold for 8b 10b disparity error after which it will pull...

Page 300: ...ter 86h 7 6 5 4 3 2 1 0 LANE2_SYNC_ERR_CNT R 1h LEGEND R W Read Write W Write only n value after reset Table 2 336 Register 86 Field Descriptions Bit Field Type Reset Description 7 0 LANE2_SYNC_ER R_CNT R 1h lane2 6 sync error count value read 2 4 104 Register 87h offset 87h reset 1h Figure 2 333 Register 87h 7 6 5 4 3 2 1 0 LANE3_SYNC_ERR_CNT R 1h LEGEND R W Read Write W Write only n value after ...

Page 301: ...d_counter value when lane0 4 is ready JESDC Measured rbd_counter value when lane0 4 is ready 2 4 107 Register 8Ah offset 8Ah reset 0h Figure 2 336 Register 8Ah 7 6 5 4 3 2 1 0 LANE1_F_COUNTER_ANY_LANE_READY 7 0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 340 Register 8A Field Descriptions Bit Field Type Reset Description 7 0 LANE1_F_COUNT ER_ANY_LANE_R EADY 7 0 R 0h JESDB M...

Page 302: ...15 8 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 343 Register 8D Field Descriptions Bit Field Type Reset Description 7 0 LANE2_F_COUNT ER_ANY_LANE_R EADY 15 8 R 0h JESDB Measured rbd_counter value when lane2 6 is ready JESDC Measured rbd_counter value when lane2 6 is ready 2 4 111 Register 8Eh offset 8Eh reset 0h Figure 2 340 Register 8Eh 7 6 5 4 3 2 1 0 LANE3_F_COUNTER_ANY...

Page 303: ...nes are ready JESDC Measured rbd_counter value when all enabled lanes are ready 2 4 114 Register 91h offset 91h reset 0h Figure 2 343 Register 91h 7 6 5 4 3 2 1 0 LANE0_F_COUNTER_ALL_LANES_READY 15 8 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 347 Register 91 Field Descriptions Bit Field Type Reset Description 7 0 LANE0_F_COUNT ER_ALL_LANES_ READY 15 8 R 0h JESDB Measured r...

Page 304: ...et 0h Figure 2 346 Register 94h 7 6 5 4 3 2 1 0 LANE2_F_COUNTER_ALL_LANES_READY 7 0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 350 Register 94 Field Descriptions Bit Field Type Reset Description 7 0 LANE2_F_COUNT ER_ALL_LANES_ READY 7 0 R 0h JESDB Measured rbd_counter value when all enabled lanes are ready JESDC Measured rbd_counter value when all enabled lanes are ready 2...

Page 305: ... JESDC Measured rbd_counter value when all enabled lanes are ready 2 4 120 Register 97h offset 97h reset 0h Figure 2 349 Register 97h 7 6 5 4 3 2 1 0 LANE3_F_COUNTER_ALL_LANES_READY 15 8 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 353 Register 97 Field Descriptions Bit Field Type Reset Description 7 0 LANE3_F_COUNT ER_ALL_LANES_ READY 15 8 R 0h JESDB Measured rbd_counter va...

Page 306: ... Step 3 as modulo link0_rbd_m1 from Step 3 link0_sysref_cnt_on_release_opportunity F K 4 and run the simulation Step 6 Now if you read back the register link0_sysref_cnt_on_release_opportunity it should read back as 0 For JESDC Step 1 First run the simulation with some link0_rbd_m1 register programmed Step 2 Read the lane0_f_counter_all_lanes_ready status register Step 3 Program the link0_rbd_m1 r...

Page 307: ...ome link0_rbd_m1 register programmed Step 2 Read the lane0_f_counter_all_lanes_ready status register Step 3 Program the link0_rbd_m1 registers with the modulo lane0_f_counter_all_lanes_ready 2 64 K and run the simulation Step 4 Now read the link0_sysref_cnt_on_release_opportunity status register Step 5 Again Program the link0_rbd_m1 registers with the link0_rbd_m1 from Step 3 as modulo link0_rbd_m...

Page 308: ..._CNT_OVR R W 0h TESTMODE 2 0 LINK1_MAPPER_S YSREF_CNT_VAL R W 0h TESTMODE 2 4 124 Register 9Ch offset 9Ch reset 0h Figure 2 353 Register 9Ch 7 6 5 4 3 2 1 0 LINK0_RELEA SE_OPPORTU NITY_PIPE_DL Y_OVR LINK0_MAPPE R_RESET LINK0_RELEASE_OPPORTUNITY_PIPE_DLY_VAL R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 357 Register 9C Field Descriptions Bit Field Type Reset De...

Page 309: ...28 5 SEARCH_PATTERN_STATE value JESDC SYNC_HEADER SEARCH_PATTERN_STATE value bits 1 0 SRX1 5 bits 3 2 SRX2 6 bits 5 4 SRX3 7 bits 7 6 SRX4 8 For stable link the bits for each lane enabled should read as 10 Note Refer to the TI application note for details on error interpretation 2 4 127 Register A1h offset A1h reset 0h Figure 2 356 Register A1h 7 6 5 4 3 2 1 0 JESD_SH_STATE_PREV R 0h LEGEND R W Re...

Page 310: ...uld read as 10 Note Refer to the TI application note for details on error interpretation 2 4 129 Register A3h offset A3h reset 0h Figure 2 358 Register A3h 7 6 5 4 3 2 1 0 JESD_CS_STATE_PREV R 0h LEGEND R W Read Write W Write only n value after reset Table 2 362 Register A3 Field Descriptions Bit Field Type Reset Description 7 0 JESD_CS_STATE _PREV R 0h JESDB Previous CS_STATE value JESDC Previous...

Page 311: ... reset Table 2 364 Register A5 Field Descriptions Bit Field Type Reset Description 7 0 JESD_FS_STATE_ PREV R 0h JESDB Previous FS_STATE value JESDC UNUSED bits 1 0 SRX1 5 bits 3 2 SRX2 6 bits 5 4 SRX3 7 bits 7 6 SRX4 8 For stable link JESDB the bits for each lane enabled should read as 00 Note Refer to the TI application note for details on error interpretation 2 4 132 Register A6h offset A6h rese...

Page 312: ...LINK0_EMB_A LIGN_RESET R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 367 Register AC Field Descriptions Bit Field Type Reset Description 4 4 EMB_ALIGN_PAT T_SEL R W 0h JESDC Select bit65 or bit64 for the EMB lock bit65 is latest 0 bit 64 next bit after the first bit received 1 bit 65 first bit to be received JESDB UNUSED 3 3 LINK1_EMB_ALIG N_LOCK...

Page 313: ...to lock state JESDB UNUSED 2 4 136 Register AEh offset AEh reset 0h Figure 2 365 Register AEh 7 6 5 4 3 2 1 0 JESDC_ENCODING_MODE JESDC_CRC_ MODE JESDC_80B_M ODE_EN DATA_BITS_R EORDER_AFT ER_CRC DATA_BYTES_ REORDER_AF TER_CRC DATA_BITS_R EORDER_BEF ORE_CRC DATA_BYTES_ REORDER_BE FORE_CRC R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2...

Page 314: ...Figure 2 367 Register B1h 7 6 5 4 3 2 1 0 JESDC_CMD_DATA 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 371 Register B1 Field Descriptions Bit Field Type Reset Description 7 0 JESDC_CMD_DAT A 15 8 R W 0h JESDC This pre programmed spi register is to set the command channel checker to check against the command data stream from JESD 204C Tx IP of FPGA or ASIC JESDB UNUSED ...

Page 315: ..._ SWAP_EN R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 374 Register B4 Field Descriptions Bit Field Type Reset Description 7 7 LINK1_MAPPER_T X4_I1_Q0_SWAP_ EN R W 0h Enables swaping of I1 and Q0 samples Useful when S 2 6 6 LINK1_MAPPER_T X3_I1_Q0_SWAP_ EN R W 0h Enables swaping of I1 and Q0 samples Useful when S 2 5 5 LINK1...

Page 316: ...gram octets in jesd_shorttest_patterns 0 15 2 4 143 Register B7h offset B7h reset 0h Figure 2 372 Register B7h 7 6 5 4 3 2 1 0 TX_JESD_RAMPTEST_INCR TX_JESD_TEST_SIG_GEN_MODE R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 376 Register B7 Field Descriptions Bit Field Type Reset Description 7 4 TX_JESD_RAMPT EST_INCR R W 0h increment value of ramp test pattern 2 0 TX_JE...

Page 317: ...ter BAh 7 6 5 4 3 2 1 0 JESD_SHORTTEST_INPUT1 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 379 Register BA Field Descriptions Bit Field Type Reset Description 7 0 JESD_SHORTTES T_INPUT1 7 0 R W 0h short test pattern input 2 4 147 Register BBh offset BBh reset 0h Figure 2 376 Register BBh 7 6 5 4 3 2 1 0 JESD_SHORTTEST_INPUT1 15 8 R W 0h LEGEND R W Read Write W Write on...

Page 318: ...it Field Type Reset Description 7 0 JESD_SHORTTES T_INPUT2 15 8 R W 0h short test pattern input 2 4 150 Register BEh offset BEh reset 0h Figure 2 379 Register BEh 7 6 5 4 3 2 1 0 JESD_SHORTTEST_INPUT3 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 383 Register BE Field Descriptions Bit Field Type Reset Description 7 0 JESD_SHORTTES T_INPUT3 7 0 R W 0h short test pattern ...

Page 319: ...er C1h 7 6 5 4 3 2 1 0 JESD_SHORTTEST_INPUT4 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 386 Register C1 Field Descriptions Bit Field Type Reset Description 7 0 JESD_SHORTTES T_INPUT4 15 8 R W 0h short test pattern input 2 4 154 Register C2h offset C2h reset 0h Figure 2 383 Register C2h 7 6 5 4 3 2 1 0 JESD_SHORTTEST_INPUT5 7 0 R W 0h LEGEND R W Read Write W Write on...

Page 320: ...Bit Field Type Reset Description 7 0 JESD_SHORTTES T_INPUT6 7 0 R W 0h short test pattern input 2 4 157 Register C5h offset C5h reset 0h Figure 2 386 Register C5h 7 6 5 4 3 2 1 0 JESD_SHORTTEST_INPUT6 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 390 Register C5 Field Descriptions Bit Field Type Reset Description 7 0 JESD_SHORTTES T_INPUT6 15 8 R W 0h short test patter...

Page 321: ...ter C8h 7 6 5 4 3 2 1 0 JESD_SHORTTEST_INPUT8 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 393 Register C8 Field Descriptions Bit Field Type Reset Description 7 0 JESD_SHORTTES T_INPUT8 7 0 R W 0h short test pattern input 2 4 161 Register C9h offset C9h reset 0h Figure 2 390 Register C9h 7 6 5 4 3 2 1 0 JESD_SHORTTEST_INPUT8 15 8 R W 0h LEGEND R W Read Write W Write on...

Page 322: ... Field Type Reset Description 7 0 JESD_SHORTTES T_INPUT9 15 8 R W 0h short test pattern input 2 4 164 Register CCh offset CCh reset 0h Figure 2 393 Register CCh 7 6 5 4 3 2 1 0 JESD_SHORTTEST_INPUT10 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 397 Register CC Field Descriptions Bit Field Type Reset Description 7 0 JESD_SHORTTES T_INPUT10 7 0 R W 0h short test pattern ...

Page 323: ... CFh 7 6 5 4 3 2 1 0 JESD_SHORTTEST_INPUT11 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 400 Register CF Field Descriptions Bit Field Type Reset Description 7 0 JESD_SHORTTES T_INPUT11 15 8 R W 0h short test pattern input 2 4 168 Register D0h offset D0h reset 0h Figure 2 397 Register D0h 7 6 5 4 3 2 1 0 JESD_SHORTTEST_INPUT12 7 0 R W 0h LEGEND R W Read Write W Write o...

Page 324: ...t Field Type Reset Description 7 0 JESD_SHORTTES T_INPUT13 7 0 R W 0h short test pattern input 2 4 171 Register D3h offset D3h reset 0h Figure 2 400 Register D3h 7 6 5 4 3 2 1 0 JESD_SHORTTEST_INPUT13 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 404 Register D3 Field Descriptions Bit Field Type Reset Description 7 0 JESD_SHORTTES T_INPUT13 15 8 R W 0h short test patte...

Page 325: ...2 1 0 JESD_SHORTTEST_INPUT15 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 407 Register D6 Field Descriptions Bit Field Type Reset Description 7 0 JESD_SHORTTES T_INPUT15 7 0 R W 0h short test pattern input 2 4 175 Register D7h offset D7h reset 0h Figure 2 404 Register D7h 7 6 5 4 3 2 1 0 JESD_SHORTTEST_INPUT15 15 8 R W 0h LEGEND R W Read Write W Write only n value afte...

Page 326: ...it Field Type Reset Description 7 4 CLEAR_SERDES_ RXBCLK_FLAG R W 0h clear serdes_rxbclk_lane 0 3 _monitor_flag 3 0 CLEAR_VALID_DA TA_OUT_FLAG R W 0h JESDB C clear valid_data_out_lane 0 3 4 7 _monitor_flag 2 4 178 Register EAh offset EAh reset 0h Figure 2 407 Register EAh 7 6 5 4 3 2 1 0 CLEAR_TX_DAC_SYSREF_FLAG CLEAR_TX_DAC_CLK_FLAG R W 0h R W 0h LEGEND R W Read Write W Write only n value after r...

Page 327: ...d_rx_div2_clk monitor flag 2 4 181 Register EDh offset EDh reset 0h Figure 2 410 Register EDh 7 6 5 4 3 2 1 0 CLEAR_DUC_SYSREF_FLAG CLEAR_DUC_CLK_FLAG R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 414 Register ED Field Descriptions Bit Field Type Reset Description 7 4 CLEAR_DUC_SYS REF_FLAG R W 0h clear duc_wr_sysref monitor flag 3 0 CLEAR_DUC_CLK _FLAG R W 0h clear ...

Page 328: ...7 _monitor_flag 2 4 184 Register F0h offset F0h reset 0h Figure 2 413 Register F0h 7 6 5 4 3 2 1 0 TX_DAC_SYSREF_FLAG TX_DAC_CLK_FLAG R 0h R 0h LEGEND R W Read Write W Write only n value after reset Table 2 417 Register F0 Field Descriptions Bit Field Type Reset Description 7 4 TX_DAC_SYSREF _FLAG R 0h tx_dac_sysref monitor flag 3 0 TX_DAC_CLK_FL AG R 0h tx_dac_clk monitor flag 2 4 185 Register F1...

Page 329: ...onitor flag 2 4 187 Register F3h offset F3h reset 0h Figure 2 416 Register F3h 7 6 5 4 3 2 1 0 DUC_SYSREF_TX1_FLAG DUC_CLK_TX1_FLAG R 0h R 0h LEGEND R W Read Write W Write only n value after reset Table 2 420 Register F3 Field Descriptions Bit Field Type Reset Description 7 4 DUC_SYSREF_TX 1_FLAG R 0h duc_wr_sysref monitor flag 3 0 DUC_CLK_TX1_FL AG R 0h duc_wr_clk monitor flag 2 4 188 Register F4...

Page 330: ...ter F6h 7 6 5 4 3 2 1 0 DUC_SYSREF_TX2_FLAG DUC_CLK_TX2_FLAG R 0h R 0h LEGEND R W Read Write W Write only n value after reset Table 2 423 Register F6 Field Descriptions Bit Field Type Reset Description 7 4 DUC_SYSREF_TX 2_FLAG R 0h duc_wr_sysref monitor flag 3 0 DUC_CLK_TX2_FL AG R 0h duc_wr_clk monitor flag 2 4 191 Register F8h offset F8h reset 0h Figure 2 420 Register F8h 7 6 5 4 3 2 1 0 ALARMS_...

Page 331: ...dicator 12 SRX1 5 Serdes FIFO error 13 SRX2 6 Serdes FIFO error 14 SRX3 7 Serdes FIFO error 15 SRX4 8 Serdes FIFO error Note Refer to the TI application note for details on error interpretation 2 4 193 Register FAh offset FAh reset 0h Figure 2 422 Register FAh 7 6 5 4 3 2 1 0 ALARMS_MASK 23 16 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 426 Register FA Field Descriptions ...

Page 332: ...only n value after reset Table 2 428 Register FC Field Descriptions Bit Field Type Reset Description 7 0 ALARMS_MASK 3 9 32 R W 0h Masks alarms register to the alarm pin will not affect alarm read from SPI 39 32 SRX1 5 JESD errors Each of the bits for the above mentioned lane errors are mapped to bit7 JESDB multiframe alignment error bit6 JESDB frame alignment error bit5 JESDB link configuration e...

Page 333: ...ation error bit4 JESDB elastic buffer overflow bad RBD value bit3 JESDB elastic buffer match error The first non K doesnt match match_ctrl and match_data programmed values bit2 JESDB code synchronization error bit1 JESDB 8b 10b not in table code error Bit0 JESDB 8b 10b disparity error bit7 JESDC EoEMB alignment error bit6 JESDC EoMB alignment error bit5 JESDC cmd data in crc mode not matching with...

Page 334: ...uffer match error The first non K doesnt match match_ctrl and match_data programmed values bit2 JESDB code synchronization error bit1 JESDB 8b 10b not in table code error Bit0 JESDB 8b 10b disparity error bit7 JESDC EoEMB alignment error bit6 JESDC EoMB alignment error bit5 JESDC cmd data in crc mode not matching with spi register bits bit4 JESDC elastic buffer overflow bad RBD value bit3 JESDC TI...

Page 335: ...a in crc mode not matching with spi register bits bit4 JESDC elastic buffer overflow bad RBD value bit3 JESDC TIED to 0 bit2 JESDC extended multiblock alignment error bit1 JESDC sync header invalid error 11 or 00 received in expected sync header location Bit0 JESDC sync header CRC error Note Refer to the TI application note for details on error interpretation 2 4 199 Register 100h offset 100h rese...

Page 336: ... error 15 SRX4 8 Serdes FIFO error Note Refer to the TI application note for details on error interpretation 2 4 201 Register 102h offset 102h reset 0h Figure 2 430 Register 102h 7 6 5 4 3 2 1 0 ALARMS_CLEAR 23 16 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 434 Register 102 Field Descriptions Bit Field Type Reset Description 7 0 ALARMS_CLEAR 23 16 R W 0h Clear alarms regi...

Page 337: ...e only n value after reset Table 2 436 Register 104 Field Descriptions Bit Field Type Reset Description 7 0 ALARMS_CLEAR 39 32 R W 0h Clear alarms register to the alarm pin Alarms won t be generated if 1 so it must be programmed to 0 for alarms to continue 39 32 SRX1 5 JESD errors Each of the bits for the above mentioned lane errors are mapped to bit7 JESDB multiframe alignment error bit6 JESDB fr...

Page 338: ... bit5 JESDB link configuration error bit4 JESDB elastic buffer overflow bad RBD value bit3 JESDB elastic buffer match error The first non K doesnt match match_ctrl and match_data programmed values bit2 JESDB code synchronization error bit1 JESDB 8b 10b not in table code error Bit0 JESDB 8b 10b disparity error bit7 JESDC EoEMB alignment error bit6 JESDC EoMB alignment error bit5 JESDC cmd data in c...

Page 339: ...e bit3 JESDB elastic buffer match error The first non K doesnt match match_ctrl and match_data programmed values bit2 JESDB code synchronization error bit1 JESDB 8b 10b not in table code error Bit0 JESDB 8b 10b disparity error bit7 JESDC EoEMB alignment error bit6 JESDC EoMB alignment error bit5 JESDC cmd data in crc mode not matching with spi register bits bit4 JESDC elastic buffer overflow bad R...

Page 340: ...alignment error bit5 JESDC cmd data in crc mode not matching with spi register bits bit4 JESDC elastic buffer overflow bad RBD value bit3 JESDC TIED to 0 bit2 JESDC extended multiblock alignment error bit1 JESDC sync header invalid error 11 or 00 received in expected sync header location Bit0 JESDC sync header CRC error Note Refer to the TI application note for details on error interpretation 2 4 ...

Page 341: ...it Field Type Reset Description 7 0 ALARMS_TO_PAP _MASK 23 16 R W 0h Masks alarms_to_pap register effecting pap alarms will not affect alarm read from SPI 23 16 TIED to 0 Note Refer to the TI application note for details on error interpretation 2 4 210 Register 10Bh offset 10Bh reset 0h Figure 2 439 Register 10Bh 7 6 5 4 3 2 1 0 ALARMS_TO_PAP_MASK 31 24 R W 0h LEGEND R W Read Write W Write only n ...

Page 342: ...k configuration error bit4 JESDB elastic buffer overflow bad RBD value bit3 JESDB elastic buffer match error The first non K doesnt match match_ctrl and match_data programmed values bit2 JESDB code synchronization error bit1 JESDB 8b 10b not in table code error Bit0 JESDB 8b 10b disparity error bit7 JESDC EoEMB alignment error bit6 JESDC EoMB alignment error bit5 JESDC cmd data in crc mode not mat...

Page 343: ...ic buffer match error The first non K doesnt match match_ctrl and match_data programmed values bit2 JESDB code synchronization error bit1 JESDB 8b 10b not in table code error Bit0 JESDB 8b 10b disparity error bit7 JESDC EoEMB alignment error bit6 JESDC EoMB alignment error bit5 JESDC cmd data in crc mode not matching with spi register bits bit4 JESDC elastic buffer overflow bad RBD value bit3 JESD...

Page 344: ...ic buffer match error The first non K doesnt match match_ctrl and match_data programmed values bit2 JESDB code synchronization error bit1 JESDB 8b 10b not in table code error Bit0 JESDB 8b 10b disparity error bit7 JESDC EoEMB alignment error bit6 JESDC EoMB alignment error bit5 JESDC cmd data in crc mode not matching with spi register bits bit4 JESDC elastic buffer overflow bad RBD value bit3 JESD...

Page 345: ...crc mode not matching with spi register bits bit4 JESDC elastic buffer overflow bad RBD value bit3 JESDC TIED to 0 bit2 JESDC extended multiblock alignment error bit1 JESDC sync header invalid error 11 or 00 received in expected sync header location Bit0 JESDC sync header CRC error Note Refer to the TI application note for details on error interpretation 2 4 215 Register 110h offset 110h reset 0h ...

Page 346: ...15 SRX4 8 Serdes FIFO error Note Refer to the TI application note for details on error interpretation 2 4 217 Register 112h offset 112h reset 0h Figure 2 446 Register 112h 7 6 5 4 3 2 1 0 ALARMS_TO_PAP_CLEAR 23 16 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 450 Register 112 Field Descriptions Bit Field Type Reset Description 7 0 ALARMS_TO_PAP _CLEAR 23 16 R W 0h Clear ala...

Page 347: ...Write only n value after reset Table 2 452 Register 114 Field Descriptions Bit Field Type Reset Description 7 0 ALARMS_TO_PAP _CLEAR 39 32 R W 0h Clear alarms_to_pap register to the pap alarms Alarms won t be generated if 1 so it must be programmed to 0 for alarms to continue 39 32 SRX1 5 JESD errors Each of the bits for the above mentioned lane errors are mapped to bit7 JESDB multiframe alignment...

Page 348: ...nt error bit5 JESDB link configuration error bit4 JESDB elastic buffer overflow bad RBD value bit3 JESDB elastic buffer match error The first non K doesnt match match_ctrl and match_data programmed values bit2 JESDB code synchronization error bit1 JESDB 8b 10b not in table code error Bit0 JESDB 8b 10b disparity error bit7 JESDC EoEMB alignment error bit6 JESDC EoMB alignment error bit5 JESDC cmd d...

Page 349: ... value bit3 JESDB elastic buffer match error The first non K doesnt match match_ctrl and match_data programmed values bit2 JESDB code synchronization error bit1 JESDB 8b 10b not in table code error Bit0 JESDB 8b 10b disparity error bit7 JESDC EoEMB alignment error bit6 JESDC EoMB alignment error bit5 JESDC cmd data in crc mode not matching with spi register bits bit4 JESDC elastic buffer overflow ...

Page 350: ...8b 10b disparity error bit7 JESDC EoEMB alignment error bit6 JESDC EoMB alignment error bit5 JESDC cmd data in crc mode not matching with spi register bits bit4 JESDC elastic buffer overflow bad RBD value bit3 JESDC TIED to 0 bit2 JESDC extended multiblock alignment error bit1 JESDC sync header invalid error 11 or 00 received in expected sync header location Bit0 JESDC sync header CRC error Note R...

Page 351: ...ead Write W Write only n value after reset Table 2 458 Register 11A Field Descriptions Bit Field Type Reset Description 7 0 ALARMS 23 16 R 0h 23 16 TIED to 0 Note Refer to the TI application note for details on error interpretation 2 4 226 Register 11Bh offset 11Bh reset 0h Figure 2 455 Register 11Bh 7 6 5 4 3 2 1 0 ALARMS 31 24 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 4...

Page 352: ...rflow bad RBD value bit3 JESDB elastic buffer match error The first non K doesnt match match_ctrl and match_data programmed values bit2 JESDB code synchronization error bit1 JESDB 8b 10b not in table code error Bit0 JESDB 8b 10b disparity error bit7 JESDC EoEMB alignment error bit6 JESDC EoMB alignment error bit5 JESDC cmd data in crc mode not matching with spi register bits bit4 JESDC elastic buf...

Page 353: ...JESDC sync header CRC error Note Refer to the TI application note for details on error interpretation 2 4 229 Register 11Eh offset 11Eh reset 0h Figure 2 458 Register 11Eh 7 6 5 4 3 2 1 0 ALARMS 55 48 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 462 Register 11E Field Descriptions Bit Field Type Reset Description 7 0 ALARMS 55 48 R 0h 55 48 SRX3 7 JESD errors Each of the bit...

Page 354: ...zation error bit1 JESDB 8b 10b not in table code error Bit0 JESDB 8b 10b disparity error bit7 JESDC EoEMB alignment error bit6 JESDC EoMB alignment error bit5 JESDC cmd data in crc mode not matching with spi register bits bit4 JESDC elastic buffer overflow bad RBD value bit3 JESDC TIED to 0 bit2 JESDC extended multiblock alignment error bit1 JESDC sync header invalid error 11 or 00 received in exp...

Page 355: ...icator 12 SRX1 Serdes FIFO error 13 SRX2 Serdes FIFO error 14 SRX3 Serdes FIFO error 15 SRX4 Serdes FIFO error Note Refer to the TI application note for details on error interpretation 2 4 233 Register 122h offset 122h reset 0h Figure 2 462 Register 122h 7 6 5 4 3 2 1 0 ALARMS_TO_PAP 23 16 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 466 Register 122 Field Descriptions Bit F...

Page 356: ...e only n value after reset Table 2 468 Register 124 Field Descriptions Bit Field Type Reset Description 7 0 ALARMS_TO_PAP 39 32 R 0h JESD alarms going to PAP 39 32 SRX1 5 JESD errors Each of the bits for the above mentioned lane errors are mapped as bit7 JESDB multiframe alignment error bit6 JESDB frame alignment error bit5 JESDB link configuration error bit4 JESDB elastic buffer overflow bad RBD ...

Page 357: ...astic buffer overflow bad RBD value bit3 JESDB elastic buffer match error The first non K doesnt match match_ctrl and match_data programmed values bit2 JESDB code synchronization error bit1 JESDB 8b 10b not in table code error Bit0 JESDB 8b 10b disparity error bit7 JESDC EoEMB alignment error bit6 JESDC EoMB alignment error bit5 JESDC cmd data in crc mode not matching with spi register bits bit4 J...

Page 358: ...DC sync header CRC error Note Refer to the TI application note for details on error interpretation 2 4 238 Register 127h offset 127h reset 0h Figure 2 467 Register 127h 7 6 5 4 3 2 1 0 ALARMS_TO_PAP 63 56 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 471 Register 127 Field Descriptions Bit Field Type Reset Description 7 0 ALARMS_TO_PAP 63 56 R 0h JESD alarms going to PAP 63 5...

Page 359: ...nable pulsed alarms from lane2 to generate alarm to pap 5 5 DIRECT_LANE1_E RRORS_TO_PAP_ EN R W 0h Enable pulsed alarms from lane1 to generate alarm to pap 4 4 DIRECT_LANE0_E RRORS_TO_PAP_ EN R W 0h Enable pulsed alarms from lane0 to generate alarm to pap 3 3 MASK_ALL_ALAR MS_TO_PAP R W 0h Masks all DAC_JESD alarms reaching pap alarsm when asserted 2 2 CLEAR_ALL_ALA RMS_TO_PAP R W 0h Clears all DA...

Page 360: ...ALARMS_TO_PAP_EN TXA_LANE_ALARMS_TO_PAP_EN R W Fh R W Fh LEGEND R W Read Write W Write only n value after reset Table 2 475 Register 12C Field Descriptions Bit Field Type Reset Description 7 4 TXB_LANE_ALAR MS_TO_PAP_EN R W Fh Enable alarms from lanes to generate alarm_to_txb_pap 3 0 TXA_LANE_ALAR MS_TO_PAP_EN R W Fh Enable alarms from lanes to generate alarm_to_txa_pap 2 4 243 Register 12Dh offse...

Page 361: ... 2 1 0 LINK0_SYNC_RELEASE_RBD_M1 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 478 Register 139 Field Descriptions Bit Field Type Reset Description 7 0 LINK0_SYNC_REL EASE_RBD_M1 15 8 R W 0h For lanes 0 1 4 5 By default in JESDB syncz assertion happens on a multiframe end We can use this register along with the rbd_counter to time the syncz assertion TO enable this fea...

Page 362: ...ter 13Ch offset 13Ch reset 0h Figure 2 477 Register 13Ch 7 6 5 4 3 2 1 0 LANE0_SKEW R 0h LEGEND R W Read Write W Write only n value after reset Table 2 481 Register 13C Field Descriptions Bit Field Type Reset Description 4 0 LANE0_SKEW R 0h JESDB Measure lane0 skew from lane0 getting ctrl R character to all the lanes getting ctrl R character JESDC Measure lane0 skew from lane0 getting emb lock to ...

Page 363: ...lue after reset Table 2 484 Register 13F Field Descriptions Bit Field Type Reset Description 4 0 LANE3_SKEW R 0h JESDB Measure lane3 skew from lane3 getting ctrl R character to all the lanes getting ctrl R character JESDC Measure lane3 skew from lane3 getting emb lock to all the lanes getting emb locks character 2 4 252 Register 140h offset 140h reset 0h Figure 2 481 Register 140h 7 6 5 4 3 2 1 0 ...

Page 364: ... Register 142h 7 6 5 4 3 2 1 0 CTRL_TX1_DUC_CLK_P3 CTRL_TX1_DUC_CLK_P2 CTRL_TX1_DUC_CLK_P1 CTRL_TX1_DUC_CLK_P0 R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 487 Register 142 Field Descriptions Bit Field Type Reset Description 7 6 CTRL_TX1_DUC_ CLK_P3 R W 0h bit 1 select bit 0 as clk en bit 0 0 DIS 1 EN 5 4 CTRL_TX1_DUC_ CLK_P2 R W 0h bit 1 select bit 0 ...

Page 365: ...JESD_ CLK_P3 R W 0h bit 1 select bit 0 as clk en bit 0 0 DIS 1 EN 5 4 CTRL_TX1_JESD_ CLK_P2 R W 0h bit 1 select bit 0 as clk en bit 0 0 DIS 1 EN 3 2 CTRL_TX1_JESD_ CLK_P1 R W 0h bit 1 select bit 0 as clk en bit 0 0 DIS 1 EN 1 0 CTRL_TX1_JESD_ CLK_P0 R W 0h bit 1 select bit 0 as clk en bit 0 0 DIS 1 EN 2 4 257 Register 145h offset 145h reset 0h Figure 2 486 Register 145h 7 6 5 4 3 2 1 0 CTRL_TX2_JE...

Page 366: ...ESD_ CLK_DIV2_P0 R W 0h bit 1 select bit 0 as clk en bit 0 0 DIS 1 EN 2 4 259 Register 147h offset 147h reset 0h Figure 2 488 Register 147h 7 6 5 4 3 2 1 0 CTRL_TX2_JESD_CLK_DIV2_P 3 CTRL_TX2_JESD_CLK_DIV2_P 2 CTRL_TX2_JESD_CLK_DIV2_P 1 CTRL_TX2_JESD_CLK_DIV2_P 0 R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 492 Register 147 Field Descriptions Bit Field...

Page 367: ...Field Descriptions Bit Field Type Reset Description 7 4 MAPPER_SYNC_F IFO_TX1_OFFSET _S2TO2 R W 4h TESTMODE 3 0 MAPPER_SYNC_F IFO_TX1_OFFSET _S4TO1 R W 8h TESTMODE 2 4 262 Register 14Ah offset 14Ah reset 24h Figure 2 491 Register 14Ah 7 6 5 4 3 2 1 0 MAPPER_SYNC_FIFO_TX1_OFFSET_S1TO1 MAPPER_SYNC_FIFO_TX1_OFFSET_S2TO1 R W 2h R W 4h LEGEND R W Read Write W Write only n value after reset Table 2 495 ...

Page 368: ... Table 2 497 Register 14D Field Descriptions Bit Field Type Reset Description 7 4 MAPPER_SYNC_F IFO_TX2_OFFSET _S2TO2 R W 4h TESTMODE 3 0 MAPPER_SYNC_F IFO_TX2_OFFSET _S4TO1 R W 8h TESTMODE 2 4 265 Register 14Eh offset 14Eh reset 24h Figure 2 494 Register 14Eh 7 6 5 4 3 2 1 0 MAPPER_SYNC_FIFO_TX2_OFFSET_S1TO1 MAPPER_SYNC_FIFO_TX2_OFFSET_S2TO1 R W 2h R W 4h LEGEND R W Read Write W Write only n valu...

Page 369: ...ters are samples and save to the registers serdes_fifo_wr_ptr_sample serdes_fifo_rd_ptr_sample 2 4 267 Register 151h offset 151h reset 0h Figure 2 496 Register 151h 7 6 5 4 3 2 1 0 SERDES_FIFO_RD_PTR_SAMPLE SERDES_FIFO_WR_PTR_SAMPLE R 0h R 0h LEGEND R W Read Write W Write only n value after reset Table 2 500 Register 151 Field Descriptions Bit Field Type Reset Description 7 4 SERDES_FIFO_R D_PTR_S...

Page 370: ... 0 0 RX1_JESD_MODE 35h 0 0 RX2_JESD_MODE 36h 0 0 FB_JESD_MODE 37h 0 0 0 0 0 FB_CTRLMODE _12B_TRUNC_E N RX2_CTRLMOD E_12B_TRUNC_ EN RX1_CTRLMOD E_12B_TRUNC_ EN 38h 0 0 0 RX1_SAMPLE_ CNT_MAX_OVR RX1_SAMPLE_CNT_MAX_OVR_VAL 39h 0 0 0 RX2_SAMPLE_ CNT_MAX_OVR RX2_SAMPLE_CNT_MAX_OVR_VAL 3Ah 0 0 0 FB_SAMPLE_C NT_MAX_OVR FB_SAMPLE_CNT_MAX_OVR_VAL 3Ch 0 0 SEL_FB_JESD_ MODE_1S_2S_ OVR SEL_FB_JESD_ MODE_1S_2S...

Page 371: ..._LFSR_SEED_VAL 23 16 63h 0 0 0 0 0 0 0 CFG_RX_LFSR_ LOAD 64h CFG_FB_LFSR_SEED_VAL 7 0 65h CFG_FB_LFSR_SEED_VAL 15 8 66h CFG_FB_LFSR_SEED_VAL 23 16 67h 0 0 0 0 0 0 0 CFG_FB_LFSR_ LOAD 68h 0 0 0 0 0 0 0 SERDES_INPUT _ORDER_FLIP_ DISABLE 69h SERDES_FIFO_READ_DLY_LANE1 SERDES_FIFO_READ_DLY_LANE0 6Ah SERDES_FIFO_READ_DLY_LANE3 SERDES_FIFO_READ_DLY_LANE2 6Ch 0 0 0 0 LANE3_GEARB OX_INIT_STATE LANE2_GEARB...

Page 372: ...END LINK1_DISABLE _F_CHAR LINK1_DISABLE _A_CHAR LINK1_NO_LAN E_SYNC 9Eh 0 0 0 0 LINK1_SYNC_F _CTR_INCR_OV R_EN LINK1_SYNC_F_CTR_INCR_OVR_VAL 9Fh 0 0 0 0 0 LINK1_JESD_TEST_SEQ_SEL A0h LINK1_INIT_O_MF_COUNTER 7 0 A1h 0 0 0 LINK1_INIT_O_MF_COUNTER 12 8 A2h 0 0 0 0 0 0 0 LINK1_ERR_CN T_CLR A4h LINK2_DID A5h LINK2_ADJCNT LINK2_BID A6h 0 LINK2_ADJDIR LINK2_PHADJ 0 0 0 0 0 A7h LINK2_SCR 0 0 LINK2_ILA_L_M...

Page 373: ...E_FB SAMPLE_DROP_MODE_RX2 SAMPLE_DROP_MODE_RX1 E1h 0 0 0 0 RXA_SD_CLK_DIV_N_M1 RXA_SD_CLK_DIV_M E2h 0 0 0 0 RXB_SD_CLK_DIV_N_M1 RXB_SD_CLK_DIV_M E3h 0 0 0 0 FBAB_SD_CLK_DIV_N_M1 FBAB_SD_CLK_DIV_M F0h 0 0 0 0 ALARMS_SERDES_FIFO_ERRORS_CLEAR F1h 0 0 0 0 ALARMS_SERDES_FIFO_ERRORS_MASK F2h 0 0 0 0 SERDES_FIFO_ERROR_DIFF2_MASK F3h 0 0 0 0 0 0 0 SERDES_FIFO_ PTR_SAMPLE F4h ALARMS_SERDES_FIFO_ERRORS_UNMA...

Page 374: ...h CLEAR_JESD_C LK_RX2_P0_MS F_RD CLEAR_JESD_C LK_RX1_P0_MS F_RD CLEAR_JESD_C LK_DIV2_FB_P3 CLEAR_JESD_C LK_DIV2_FB_P1 CLEAR_JESD_C LK_DIV2_RX2_P 2 CLEAR_JESD_C LK_DIV2_RX1_P 0 CLEAR_JESD_C LK_FB_P3 CLEAR_JESD_C LK_FB_P1 126h 0 0 0 CLEAR_SERDE S_TXBCLK3 CLEAR_SERDE S_TXBCLK2 CLEAR_SERDE S_TXBCLK1 CLEAR_SERDE S_TXBCLK0 CLEAR_JESD_C LK_FB_P0_MSF _RD 128h CLEAR_JESD_S YSREF_FB_P0 CLEAR_JESD_S YSREF_RX...

Page 375: ...offset 21h reset 1h Figure 2 498 Register 21h 7 6 5 4 3 2 1 0 0 0 0 0 JESD_SYSTEM_MODE R W 0h R W 0h R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 503 Register 21 Field Descriptions Bit Field Type Reset Description 7 4 0 R W 0h Must read or write 0 3 0 JESD_SYSTEM_M ODE R W 1h FDD_2R1F_MODE 0 FDD_1R1F_MODE OR TDD_DEDICATED_MODE 1 IDENTICAL_2RX_MODE 2 IDENTICAL...

Page 376: ...ister 23h 7 6 5 4 3 2 1 0 0 0 0 0 LANE_ENA R W 0h R W 0h R W 0h R W 0h R W Fh LEGEND R W Read Write W Write only n value after reset Table 2 505 Register 23 Field Descriptions Bit Field Type Reset Description 7 4 0 R W 0h Must read or write 0 3 0 LANE_ENA R W Fh Turns on individual lanes bit 0 STX1 5 bit 1 STX2 6 bit 2 STX3 7 bit 3 STX4 8 2 5 5 Register 24h offset 24h reset 0h Figure 2 501 Registe...

Page 377: ...ead Write W Write only n value after reset Table 2 508 Register 27 Field Descriptions Bit Field Type Reset Description 7 4 0 R W 0h Must read or write 0 3 0 MASK_INIT_STAT E_TO_DATA_MUX R W Fh By default sysref aligned init_state is used to mask the data going on lanes If not needed make it zero bit 0 STX1 5 bit 1 STX2 6 bit 2 STX3 7 bit 3 STX4 8 2 5 8 Register 2Ch offset 2Ch reset 0h Figure 2 504...

Page 378: ...ster 2E Field Descriptions Bit Field Type Reset Description 7 4 0 R W 0h Must read or write 0 3 3 TDD_FBABZ_FBC D_DYN_SWITCH_I NV R W 0h Polarity inversion of the switching signal fbabz_fbcd 2 2 TDD_FBABZ_FBC D_DYN_SWITCH_ OVR R W 0h When 1 the spi val is used to switch the fbabz_fbcd signal in adc_jesd 1 1 TDD_FBABZ_FBC D_DYN_SWITCH_ VAL R W 0h After ovr is 1 0 No swap in fbab fbcd 1 Swap fbab fb...

Page 379: ... 30h 7 6 5 4 3 2 1 0 0 0 FB_DATA_ORDER_MUX_SEL RX3_RX4_DATA_ORDER_MUX _SEL RX_DATA_ORDER_MUX_SEL R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 512 Register 30 Field Descriptions Bit Field Type Reset Description 7 6 0 R W 0h Must read or write 0 5 4 FB_DATA_ORDER _MUX_SEL R W 0h 0 FB1 FB2 or FB1 duplicated depends on mapper mode 1 RX2 FB2 3 2 RX3_...

Page 380: ...4 3 2 1 0 0 0 0 0 0 0 FB_DATA_DU PLICATE_OVR _EN FB_DATA_DU PLICATE_EN R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 514 Register 32 Field Descriptions Bit Field Type Reset Description 7 2 0 R W 0h Must read or write 0 1 1 FB_DATA_DUPLIC ATE_OVR_EN R W 0h To override default fb data duplicate mode By default fb data duplicate...

Page 381: ...ons continued Bit Field Type Reset Description 1 1 RX2_USE_MAPPE R_ALIGN_B0_OVR R W 1h Not recommended to be set by the user Should be 1 0 0 RX1_USE_MAPPE R_ALIGN_B0_OVR R W 1h Not recommended to be set by the user Should be 1 2 5 15 Register 34h offset 34h reset 0h Figure 2 511 Register 34h 7 6 5 4 3 2 1 0 0 0 RX1_JESD_MODE R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after res...

Page 382: ...82 SBAU337 May 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated Serial Interface Register Maps Table 2 516 Register 34 Field Descriptions Bit Field Type Reset Description 7 6 0 R W 0h Must read or write 0 ...

Page 383: ..._IQ 23 MODE_1S_141610_IQ 24 MODE_1S_183210_IQ 25 MODE_1S_1163210_IQ 26 MODE_1S_1162410_IQ 27 MODE_1S_TOR_22210 50 S 2 MODE_2S_24820_IQ 0 MODE_2S_12810_IQ 1 MODE_2S_24620_IQ 2 MODE_2S_44620_IQ 3 MODE_2S_44420_IQ 4 MODE_2S_22320_IQ 5 MODE_2S_142420_IQ 6 MODE_2S_41240_IQ 7 MODE_2S_41121_IQ 8 MODE_2S_44210_IQ 9 MODE_2S_42220_IQ 10 MODE_2S_14810_IQ 11 MODE_2S_121620_IQ_DUP 12 MODE_2S_241220_IQ 13 MODE_...

Page 384: ... continued Bit Field Type Reset Description MODE_2S_141620_IQ 39 MODE_2S_141220_IQ 40 MODE_2S_24310_IQ 41 MODE_2S_24610_IQ 42 MODE_2S_14610_IQ 43 MODE_2S_141210_IQ 44 MODE_2S_42111_IQ 45 MODE_2S_44840_IQ 46 MODE_2S_VSWR_24410 50 2 5 16 Register 35h offset 35h reset 0h Figure 2 512 Register 35h 7 6 5 4 3 2 1 0 0 0 RX2_JESD_MODE R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after r...

Page 385: ...85 SBAU337 May 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated Serial Interface Register Maps Table 2 517 Register 35 Field Descriptions Bit Field Type Reset Description 7 6 0 R W 0h Must read or write 0 ...

Page 386: ..._IQ 23 MODE_1S_141610_IQ 24 MODE_1S_183210_IQ 25 MODE_1S_1163210_IQ 26 MODE_1S_1162410_IQ 27 MODE_1S_TOR_22210 50 S 2 MODE_2S_24820_IQ 0 MODE_2S_12810_IQ 1 MODE_2S_24620_IQ 2 MODE_2S_44620_IQ 3 MODE_2S_44420_IQ 4 MODE_2S_22320_IQ 5 MODE_2S_142420_IQ 6 MODE_2S_41240_IQ 7 MODE_2S_41121_IQ 8 MODE_2S_44210_IQ 9 MODE_2S_42220_IQ 10 MODE_2S_14810_IQ 11 MODE_2S_121620_IQ_DUP 12 MODE_2S_241220_IQ 13 MODE_...

Page 387: ... continued Bit Field Type Reset Description MODE_2S_141620_IQ 39 MODE_2S_141220_IQ 40 MODE_2S_24310_IQ 41 MODE_2S_24610_IQ 42 MODE_2S_14610_IQ 43 MODE_2S_141210_IQ 44 MODE_2S_42111_IQ 45 MODE_2S_44840_IQ 46 MODE_2S_VSWR_24410 50 2 5 17 Register 36h offset 36h reset 1Eh Figure 2 513 Register 36h 7 6 5 4 3 2 1 0 0 0 FB_JESD_MODE R W 0h R W 0h R W 1Eh LEGEND R W Read Write W Write only n value after ...

Page 388: ...88 SBAU337 May 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated Serial Interface Register Maps Table 2 518 Register 36 Field Descriptions Bit Field Type Reset Description 7 6 0 R W 0h Must read or write 0 ...

Page 389: ..._IQ 23 MODE_1S_141610_IQ 24 MODE_1S_183210_IQ 25 MODE_1S_1163210_IQ 26 MODE_1S_1162410_IQ 27 MODE_1S_TOR_22210 50 S 2 MODE_2S_24820_IQ 0 MODE_2S_12810_IQ 1 MODE_2S_24620_IQ 2 MODE_2S_44620_IQ 3 MODE_2S_44420_IQ 4 MODE_2S_22320_IQ 5 MODE_2S_142420_IQ 6 MODE_2S_41240_IQ 7 MODE_2S_41121_IQ 8 MODE_2S_44210_IQ 9 MODE_2S_42220_IQ 10 MODE_2S_14810_IQ 11 MODE_2S_121620_IQ_DUP 12 MODE_2S_241220_IQ 13 MODE_...

Page 390: ... R W 0h Must read or write 0 2 2 FB_CTRLMODE_1 2B_TRUNC_EN R W 1h When enabled in 12b fb mapper modes the 16 bit adc data is truncated to 12 bits instead of rounding 0 Use 12b round 1 Use 12b truncate 1 1 RX2_CTRLMODE_ 12B_TRUNC_EN R W 1h When enabled in 12b rx mapper modes the 16 bit adc data is truncated to 12 bits instead of rounding Affects rx2 0 Use 12b round 1 Use 12b truncate 0 0 RX1_CTRLMO...

Page 391: ...E_CN T_MAX_OVR_VAL R W 0h When ovr is 1 this value is used as max sample count in rx2 mapper 2 5 21 Register 3Ah offset 3Ah reset 0h Figure 2 517 Register 3Ah 7 6 5 4 3 2 1 0 0 0 0 FB_SAMPLE_ CNT_MAX_OV R FB_SAMPLE_CNT_MAX_OVR_VAL R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 522 Register 3A Field Descriptions Bit Field Type Reset Description 7 5...

Page 392: ...apper input S 1 2 5 23 Register 3Dh offset 3Dh reset 0h Figure 2 519 Register 3Dh 7 6 5 4 3 2 1 0 MAPPER_SYN C_FIFO_RX1_ OFFSET_OVR MAPPER_SYNC_FIFO_RX1_OFFSET_VAL MAPPER_SYN C_FIFO_RX1_ MODE_OVR MAPPER_SYNC_FIFO_RX1_M ODE_VAL R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 524 Register 3D Field Descriptions Bit Field Type Reset Description 7 7 MAPPER_SYN...

Page 393: ... ODE_OVR MAPPER_SYNC_FIFO_FB_MO DE_VAL R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 526 Register 3F Field Descriptions Bit Field Type Reset Description 7 7 MAPPER_SYNC_F IFO_FB_OFFSET_ OVR R W 0h By default the mapper mode is derived from LMFS Use override to change this behavior 6 3 MAPPER_SYNC_F IFO_FB_OFFSET_ VAL R W 0h The offset value to be used w...

Page 394: ... R W 0h R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 529 Register 42 Field Descriptions Bit Field Type Reset Description 7 5 0 R W 0h Must read or write 0 4 0 RX2_ROOT_CLK_ DIV_M R W 2h M value of root divider Output of this divider goes to ddc and jesd clock dividers 2 5 29 Register 43h offset 43h reset 2h Figure 2 525 Register 43h 7 6 5 4 3 2 1 0 0 0 0 RX2_ROOT_CLK_DIV_N...

Page 395: ...r Output of this divider goes to ddc and jesd clock dividers 2 5 32 Register 46h offset 46h reset 1h Figure 2 528 Register 46h 7 6 5 4 3 2 1 0 0 0 0 DDC_RD_CLK_RX1_DIV_M R W 0h R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 533 Register 46 Field Descriptions Bit Field Type Reset Description 7 5 0 R W 0h Must read or write 0 4 0 DDC_RD_CLK_RX 1_DIV_M R W 1h M va...

Page 396: ...igure 2 531 Register 49h 7 6 5 4 3 2 1 0 0 0 0 DDC_RD_CLK_RX2_DIV_N_M1 R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 536 Register 49 Field Descriptions Bit Field Type Reset Description 7 5 0 R W 0h Must read or write 0 4 0 DDC_RD_CLK_RX 2_DIV_N_M1 R W 0h N 1 value of ddc divider Output of this divider clock frequency should match the RXB RXD interface r...

Page 397: ...Register 4Ch 7 6 5 4 3 2 1 0 0 0 0 JESD_CLK_RX1_DIV_M R W 0h R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 539 Register 4C Field Descriptions Bit Field Type Reset Description 7 5 0 R W 0h Must read or write 0 4 0 JESD_CLK_RX1_ DIV_M R W 1h M value of jesd divider Output of this divider clock frequency should match STX1 5 rate i e lane _rate 40 or lane_rate 33 ...

Page 398: ...7 Register 4Fh 7 6 5 4 3 2 1 0 0 0 0 JESD_CLK_RX2_DIV_N_M1 R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 542 Register 4F Field Descriptions Bit Field Type Reset Description 7 5 0 R W 0h Must read or write 0 4 0 JESD_CLK_RX2_ DIV_N_M1 R W 0h N 1 value of jesd divider Output of this divider clock frequency should match STX2 6 rate i e lane _rate 40 or lan...

Page 399: ... Reset Description 7 6 CTRL_RX2_ROOT _CLK_P2 R W 1h Used for M N clock divider disabling for lower power When MSB 0 M N divider is enabled disabled based on functionality When MSB 1 M N divider is enabled disabled using spi register i e LSB bit LSB 0 M N divider disabled LSB 1 M N divider enabled 5 4 CTRL_RX2_ROOT _CLK_P0 R W 1h Used for M N clock divider disabling for lower power When MSB 0 M N d...

Page 400: ... divider disabled LSB 1 M N divider enabled 1 0 CTRL_FB_ROOT_ CLK_P0 R W 1h Used for M N clock divider disabling for lower power When MSB 0 M N divider is enabled disabled based on functionality When MSB 1 M N divider is enabled disabled using spi register i e LSB bit LSB 0 M N divider disabled LSB 1 M N divider enabled 2 5 46 Register 56h offset 56h reset 15h Figure 2 542 Register 56h 7 6 5 4 3 2...

Page 401: ...SB 1 M N divider is enabled disabled using spi register i e LSB bit LSB 0 M N divider disabled LSB 1 M N divider enabled 5 4 CTRL_JESD_CLK_ RX2_P0 R W 0h Used for M N clock divider disabling for lower power When MSB 0 M N divider is enabled disabled based on functionality When MSB 1 M N divider is enabled disabled using spi register i e LSB bit LSB 0 M N divider disabled LSB 1 M N divider enabled ...

Page 402: ...M N divider enabled 1 0 CTRL_JESD_CLK_ FB_P0 R W 1h Used for M N clock divider disabling for lower power When MSB 0 M N divider is enabled disabled based on functionality When MSB 1 M N divider is enabled disabled using spi register i e LSB bit LSB 0 M N divider disabled LSB 1 M N divider enabled 2 5 49 Register 5Ah offset 5Ah reset 15h Figure 2 545 Register 5Ah 7 6 5 4 3 2 1 0 CTRL_JESD_CLK_RX1_P...

Page 403: ... Write only n value after reset Table 2 551 Register 5C Field Descriptions Bit Field Type Reset Description 7 5 0 R W 0h Must read or write 0 4 4 JESD_CLK_DIV2_ DITHER_EN R W 1h 0 dither disabled 1 dither enabled 3 3 JESD_CLK_DITHE R_EN R W 1h 0 dither disabled 1 dither enabled 2 2 DDC_RD_CLK_DI THER_EN R W 1h 0 dither disabled 1 dither enabled 1 1 FB_ROOT_CLK_DI THER_EN R W 1h 0 dither disabled 1...

Page 404: ...END R W Read Write W Write only n value after reset Table 2 554 Register 61 Field Descriptions Bit Field Type Reset Description 7 0 CFG_RX_LFSR_S EED_VAL 15 8 R W 0h When cfg_rx_lfsr_load is 1 this spi value is used as LFSR seed for all rx M N dividers 2 5 54 Register 62h offset 62h reset 0h Figure 2 550 Register 62h 7 6 5 4 3 2 1 0 CFG_RX_LFSR_SEED_VAL 23 16 R W 0h LEGEND R W Read Write W Write o...

Page 405: ...AL 7 0 R W 0h When cfg_fb_lfsr_load is 1 this spi value is used as LFSR seed for all fb M N dividers 2 5 57 Register 65h offset 65h reset 0h Figure 2 553 Register 65h 7 6 5 4 3 2 1 0 CFG_FB_LFSR_SEED_VAL 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 558 Register 65 Field Descriptions Bit Field Type Reset Description 7 0 CFG_FB_LFSR_S EED_VAL 15 8 R W 0h When cfg_fb_lfs...

Page 406: ...PU T_ORDER_FLI P_DISABLE R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 561 Register 68 Field Descriptions Bit Field Type Reset Description 7 1 0 R W 0h Must read or write 0 0 0 SERDES_INPUT_ ORDER_FLIP_DIS ABLE R W 0h By default the JESD IP gives data to transmit MSB first But serdes sends LSB first so requires a data flip at...

Page 407: ...1h R W 1h R W 1h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 564 Register 6C Field Descriptions Bit Field Type Reset Description 7 4 0 R W 0h Must read or write 0 3 3 LANE3_GEARBOX _INIT_STATE R W 1h Used to reset STX4 8 gearbox when init_state_gearbox_spi_ovr 1 2 2 LANE2_GEARBOX _INIT_STATE R W 1h Used to reset STX3 7 gearbox when init_state_gearbox_spi_ovr 1 1 1 LANE1_G...

Page 408: ...t STX4 8 serdes fifo when init_state_serdesfifo_spi_ovr 1 2 2 LANE2_SERDES_ FIFO_INIT_STATE R W 1h Used to reset STX3 7 serdes fifo when init_state_serdesfifo_spi_ovr 1 1 1 LANE1_SERDES_ FIFO_INIT_STATE R W 1h Used to reset STX2 6 serdes fifo when init_state_serdesfifo_spi_ovr 1 0 0 LANE0_SERDES_ FIFO_INIT_STATE R W 1h Used to reset STX1 5 serdes fifo when init_state_serdesfifo_spi_ovr 1 2 5 66 Re...

Page 409: ...ster 75 Field Descriptions Bit Field Type Reset Description 7 4 LINK0_ADJCNT R W 0h JESD link config for STX1 5 3 0 LINK0_BID R W 0h JESD link config for STX1 5 2 5 69 Register 76h offset 76h reset 0h Figure 2 565 Register 76h 7 6 5 4 3 2 1 0 0 LINK0_ADJDIR LINK0_PHADJ 0 0 0 0 0 R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 5...

Page 410: ...567 Register 78h 7 6 5 4 3 2 1 0 LINK0_ILA_F_M1 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 572 Register 78 Field Descriptions Bit Field Type Reset Description 7 0 LINK0_ILA_F_M1 R W 1h JESD link config for STX1 5 Used only when link0_jesd_ila_config_override is 1 Else F derived from LMFS is used 2 5 72 Register 79h offset 79h reset 0h Figure 2 568 Register 79h 7 6 5 4 3 ...

Page 411: ... 0h JESD link config for STX1 5 5 5 0 R W 0h Must read or write 0 4 0 LINK0_ILA_N_M1 R W Fh JESD link config for STX1 5 Used only when link0_jesd_ila_config_override is 1 Else N derived from LMFS is used 2 5 75 Register 7Ch offset 7Ch reset 2Fh Figure 2 571 Register 7Ch 7 6 5 4 3 2 1 0 LINK0_SUBCLASSV LINK0_ILA_NPRIME_M1 R W 1h R W Fh LEGEND R W Read Write W Write only n value after reset Table 2 ...

Page 412: ...r 7E Field Descriptions Bit Field Type Reset Description 7 7 LINK0_ILA_HD R W 0h JESD link config for STX1 5 Used only when link0_jesd_ila_config_override is 1 Else Hd derived from LMFS is used 6 5 0 R W 0h Must read or write 0 4 0 LINK0_CF R W 0h JESD link config for STX1 5 2 5 78 Register 7Fh offset 7Fh reset 0h Figure 2 574 Register 7Fh 7 6 5 4 3 2 1 0 LINK0_RES1 R W 0h LEGEND R W Read Write W ...

Page 413: ...rs 1 Use ila registers for ILA LMFSN parameters 2 5 81 Register 84h offset 84h reset 0h Figure 2 577 Register 84h 7 6 5 4 3 2 1 0 LINK0_K_M1 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 582 Register 84 Field Descriptions Bit Field Type Reset Description 7 0 LINK0_K_M1 R W 0h Number of frames in a multiframe for STX1 5 When link0_jesd_ila_config_override is 0 this register ...

Page 414: ...Reset Description 7 4 0 R W 0h Must read or write 0 3 3 LINK0_SYNC_F_C TR_INCR_OVR_E N R W 0h Config for STX1 5 To ovr sync_n low duration check 2 0 LINK0_SYNC_F_C TR_INCR_OVR_V AL R W 1h Config for STX1 5 When link0_sync_f_ctr_incr_ovr_en sync_n low duration counter is incremented with this spi value Can be 1 or 2 or 4 2 5 84 Register 87h offset 87h reset 0h Figure 2 580 Register 87h 7 6 5 4 3 2 ...

Page 415: ...multiframe_end in a specific pattern 2 5 86 Register 89h offset 89h reset 0h Figure 2 582 Register 89h 7 6 5 4 3 2 1 0 0 0 0 LINK0_INIT_O_MF_COUNTER 12 8 R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 587 Register 89 Field Descriptions Bit Field Type Reset Description 7 5 0 R W 0h Must read or write 0 4 0 LINK0_INIT_O_MF _COUNTER 12 8 R W 0h Config for S...

Page 416: ...X2 6 2 5 89 Register 8Dh offset 8Dh reset 0h Figure 2 585 Register 8Dh 7 6 5 4 3 2 1 0 LINK1_ADJCNT LINK1_BID R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 590 Register 8D Field Descriptions Bit Field Type Reset Description 7 4 LINK1_ADJCNT R W 0h JESD link config for STX2 6 3 0 LINK1_BID R W 0h JESD link config for STX2 6 2 5 90 Register 8Eh offset 8Eh reset 0h Figu...

Page 417: ...L_M1 R W 1h JESD link config for STX2 6 Used only when link1_jesd_ila_config_override is 1 Else L derived from LMFS is used 2 5 92 Register 90h offset 90h reset 1h Figure 2 588 Register 90h 7 6 5 4 3 2 1 0 LINK1_ILA_F_M1 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 593 Register 90 Field Descriptions Bit Field Type Reset Description 7 0 LINK1_ILA_F_M1 R W 1h JESD link confi...

Page 418: ...1 R W 0h R W 0h R W Fh LEGEND R W Read Write W Write only n value after reset Table 2 596 Register 93 Field Descriptions Bit Field Type Reset Description 7 6 LINK1_CS R W 0h JESD link config for STX2 6 5 5 0 R W 0h Must read or write 0 4 0 LINK1_ILA_N_M1 R W Fh JESD link config for STX2 6 Used only when link1_jesd_ila_config_override is 1 Else N derived from LMFS is used 2 5 96 Register 94h offset...

Page 419: ...ter 96h 7 6 5 4 3 2 1 0 LINK1_ILA_HD 0 0 LINK1_CF R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 599 Register 96 Field Descriptions Bit Field Type Reset Description 7 7 LINK1_ILA_HD R W 0h JESD link config for STX2 6 Used only when link1_jesd_ila_config_override is 1 Else Hd derived from LMFS is used 6 5 0 R W 0h Must read or write 0 4 0 LINK1_CF R W 0h ...

Page 420: ...rs are defined from JESD_MODE 7 0 settings when this bit is 0 mem_ila are dont care When 1 mem_link1_ila registers are used to compute link config 0 Use functionally computed ILA LMFSN paramters 1 Use ila registers for ILA LMFSN parameters 2 5 102 Register 9Ch offset 9Ch reset 0h Figure 2 598 Register 9Ch 7 6 5 4 3 2 1 0 LINK1_K_M1 R W 0h LEGEND R W Read Write W Write only n value after reset Tabl...

Page 421: ...itted 2 5 104 Register 9Eh offset 9Eh reset 1h Figure 2 600 Register 9Eh 7 6 5 4 3 2 1 0 0 0 0 0 LINK1_SYNC_ F_CTR_INCR_ OVR_EN LINK1_SYNC_F_CTR_INCR_OVR_VAL R W 0h R W 0h R W 0h R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 605 Register 9E Field Descriptions Bit Field Type Reset Description 7 4 0 R W 0h Must read or write 0 3 3 LINK1_SYNC_F_C TR_INCR_OVR_E N ...

Page 422: ... only n value after reset Table 2 607 Register A0 Field Descriptions Bit Field Type Reset Description 7 0 LINK1_INIT_O_MF _COUNTER 7 0 R W 0h Config for STX2 6 In JESD B Register is used as init value of o_mf_counter in sysref block In JESD C 4 0 used to reset blk_ctr 9 5 used to reset mblk_ctr Value has to be multiples of 8 All values cannot be handled due to assumption of frame_end and multifram...

Page 423: ...e 2 605 Register A4h 7 6 5 4 3 2 1 0 LINK2_DID R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 610 Register A4 Field Descriptions Bit Field Type Reset Description 7 0 LINK2_DID R W 0h JESD link config for STX 3 4 7 8 2 5 110 Register A5h offset A5h reset 0h Figure 2 606 Register A5h 7 6 5 4 3 2 1 0 LINK2_ADJCNT LINK2_BID R W 0h R W 0h LEGEND R W Read Write W Write only n valu...

Page 424: ...SCR R W 0h JESD link config for STX 3 4 7 8 For JESD B C When 1 scrambler present between transport layer and link layer is enabled 1 x 14 x 15 0 scrambler disabled 1 scrambler enabled 6 5 0 R W 0h Must read or write 0 4 0 LINK2_ILA_L_M1 R W 1h JESD link config for STX 3 4 7 8 Used only when link2_jesd_ila_config_override is 1 Else L derived from LMFS is used 2 5 113 Register A8h offset A8h reset ...

Page 425: ...116 Register ABh offset ABh reset Fh Figure 2 612 Register ABh 7 6 5 4 3 2 1 0 LINK2_CS 0 LINK2_ILA_N_M1 R W 0h R W 0h R W Fh LEGEND R W Read Write W Write only n value after reset Table 2 617 Register AB Field Descriptions Bit Field Type Reset Description 7 6 LINK2_CS R W 0h JESD link config for STX 3 4 7 8 5 5 0 R W 0h Must read or write 0 4 0 LINK2_ILA_N_M1 R W Fh JESD link config for STX 3 4 7...

Page 426: ...r AEh 7 6 5 4 3 2 1 0 LINK2_ILA_HD 0 0 LINK2_CF R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 620 Register AE Field Descriptions Bit Field Type Reset Description 7 7 LINK2_ILA_HD R W 0h JESD link config for STX 3 4 7 8 Used only when link2_jesd_ila_config_override is 1 Else Hd derived from LMFS is used 6 5 0 R W 0h Must read or write 0 4 0 LINK2_CF R W ...

Page 427: ... settings when this bit is 0 mem_ila are dont care When 1 mem_link2_ila registers are used to compute link config 0 Use functionally computed ILA LMFSN paramters 1 Use ila registers for ILA LMFSN parameters 6 0 0 R W 0h Must read or write 0 2 5 123 Register B4h offset B4h reset 0h Figure 2 619 Register B4h 7 6 5 4 3 2 1 0 LINK2_K_M1 R W 0h LEGEND R W Read Write W Write only n value after reset Tab...

Page 428: ...transmitted 2 5 125 Register B6h offset B6h reset 1h Figure 2 621 Register B6h 7 6 5 4 3 2 1 0 0 0 0 0 LINK2_SYNC_ F_CTR_INCR_ OVR_EN LINK2_SYNC_F_CTR_INCR_OVR_VAL R W 0h R W 0h R W 0h R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 626 Register B6 Field Descriptions Bit Field Type Reset Description 7 4 0 R W 0h Must read or write 0 3 3 LINK2_SYNC_F_C TR_INCR_OV...

Page 429: ...ly n value after reset Table 2 628 Register B8 Field Descriptions Bit Field Type Reset Description 7 0 LINK2_INIT_O_MF _COUNTER 7 0 R W 0h Config for STX 3 4 7 8 In JESD B Register is used as init value of o_mf_counter in sysref block In JESD C 4 0 used to reset blk_ctr 9 5 used to reset mblk_ctr Value has to be multiples of 8 All values cannot be handled due to assumption of frame_end and multifr...

Page 430: ... BCh reset 0h Figure 2 626 Register BCh 7 6 5 4 3 2 1 0 0 0 0 LID0 R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 631 Register BC Field Descriptions Bit Field Type Reset Description 7 5 0 R W 0h Must read or write 0 4 0 LID0 R W 0h JESD link config for STX1 5 2 5 131 Register BDh offset BDh reset 1h Figure 2 627 Register BDh 7 6 5 4 3 2 1 0 0 0 0 LID1 R ...

Page 431: ...1_SYNC_FIFO_S2_TO_S1 _OFFSET LINK1_SYNC_FIFO_S1_TO_S2 _OFFSET LINK0_SYNC_FIFO_S2_TO_S1 _OFFSET LINK0_SYNC_FIFO_S1_TO_S2 _OFFSET R W 0h R W 2h R W 0h R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 635 Register C0 Field Descriptions Bit Field Type Reset Description 7 6 LINK1_SYNC_FIF O_S2_TO_S1_OF FSET R W 0h To modify s 2 to s 1 transfer sync fifo offset of STX2 6 5 4 LINK1_S...

Page 432: ... Table 2 637 Register C8 Field Descriptions Bit Field Type Reset Description 7 1 0 R W 0h Must read or write 0 0 0 SYNC_HEADER_F LIP R W 0h Relevant for JESD C When 1 the final sync header transmitted on the link is flipped 2 5 137 Register C9h offset C9h reset 0h Figure 2 633 Register C9h 7 6 5 4 3 2 1 0 0 0 0 0 JESDC_ENCO DING_80B_66 BZ JESDC_CRC_ MODE JESDC_ENCODING_MODE R W 0h R W 0h R W 0h R ...

Page 433: ...35 Register CBh 7 6 5 4 3 2 1 0 0 0 0 0 0 0 reserved SCR_64B_BIT_ SWAP_DISABL E R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 640 Register CB Field Descriptions Bit Field Type Reset Description 7 2 0 R W 0h Must read or write 0 1 1 reserved R W 0h 0 0 SCR_64B_BIT_SW AP_DISABLE R W 0h In JESD C By default bit order is NOT reve...

Page 434: ...R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 643 Register CE Field Descriptions Bit Field Type Reset Description 7 2 0 R W 0h Must read or write 0 1 0 JESDC_CMD 17 1 6 R W 0h For JESD C 6 bits corresponding to 6 command bits used in CRC and FEC encoding All 18 bits are used in CMD encoding is used 2 5 143 Register CFh offset CFh reset 0h Figure 2 639 Register CFh 7 ...

Page 435: ... Write only n value after reset Table 2 646 Register D1 Field Descriptions Bit Field Type Reset Description 7 0 INIT_PRBS_SEED 15 8 R W 55h JESD C This value is used as inital seed value of PRBS17 which genrates Fill bits in jesd c 80b mode 2 5 146 Register D2h offset D2h reset 0h Figure 2 642 Register D2h 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 INIT_PRBS_SE ED 16 R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R...

Page 436: ...B_INITVAL 15 8 R W 0h 58 bit inital value used by 64b scrambler 1 x 39 x 58 Relevant for JESD C 2 5 149 Register D6h offset D6h reset 0h Figure 2 645 Register D6h 7 6 5 4 3 2 1 0 SCR_64B_INITVAL 23 16 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 650 Register D6 Field Descriptions Bit Field Type Reset Description 7 0 SCR_64B_INITVAL 23 16 R W 0h 58 bit inital value used by ...

Page 437: ... R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 653 Register D9 Field Descriptions Bit Field Type Reset Description 7 0 SCR_64B_INITVAL 47 40 R W 0h 58 bit inital value used by 64b scrambler 1 x 39 x 58 Relevant for JESD C 2 5 153 Register DAh offset DAh reset 0h Figure 2 649 Register DAh 7 6 5 4 3 2 1 0 SCR_64B_INITVAL 55 48 R W 0h LEGEND R W Read Write W Write only n value...

Page 438: ...scription 7 6 0 R W 0h Must read or write 0 5 4 SAMPLE_DROP_ MODE_FB R W 0h 0 No sample drop 1 sample drop by 2 2 sample drop by 3 3 sample drop by 4 3 2 SAMPLE_DROP_ MODE_RX2 R W 0h 0 No sample drop 1 sample drop by 2 2 sample drop by 3 3 sample drop by 4 1 0 SAMPLE_DROP_ MODE_RX1 R W 0h 0 No sample drop 1 sample drop by 2 2 sample drop by 3 3 sample drop by 4 2 5 156 Register E1h offset E1h rese...

Page 439: ... W 0h R W 1h R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 658 Register E2 Field Descriptions Bit Field Type Reset Description 7 4 0 R W 0h Must read or write 0 3 2 RXB_SD_CLK_DIV _N_M1 R W 1h If input is 2 samples per clk SD by 2 M 1 N 1 SD by 3 M 1 N 3 SD by 4 M 1 N 2 if input is 1 sample per clk SD by 2 M 1 N 2 SD by 3 M 1 N 3 SD by 4 M 1 N 4 1 0 RXB_SD_CLK_DIV _M R W 2h...

Page 440: ...F0h offset F0h reset 0h Figure 2 655 Register F0h 7 6 5 4 3 2 1 0 0 0 0 0 ALARMS_SERDES_FIFO_ERRORS_CLEAR R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 660 Register F0 Field Descriptions Bit Field Type Reset Description 7 4 0 R W 0h Must read or write 0 3 0 ALARMS_SERDES _FIFO_ERRORS_ CLEAR R W 0h register to clear serdes_fifo_errors alarm regist...

Page 441: ...R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 663 Register F3 Field Descriptions Bit Field Type Reset Description 7 1 0 R W 0h Must read or write 0 0 0 SERDES_FIFO_PT R_SAMPLE R W 0h When 1 internal fifo pointers are samples and save to the registers serdes_fifo_wr_ptr_sample serdes_fifo_rd_ptr_sample 2 5 163 Register F4h offset F4h reset 0h Figu...

Page 442: ... Read Write W Write only n value after reset Table 2 666 Register F6 Field Descriptions Bit Field Type Reset Description 7 5 0 R W 0h Must read or write 0 4 1 SERDES_FIFO_R D_PTR_SAMPLE R 0h stores the serdes fifo read ptr value when SERDES_FIFO_PTR_SAMPLE is 1 0 0 0 R W 0h Must read or write 0 2 5 166 Register F8h offset F8h reset 0h Figure 2 662 Register F8h 7 6 5 4 3 2 1 0 JESD_INTERNAL_CTR_ON_...

Page 443: ... EASSERT1 7 0 R 0h multiframe counter value on sync_n deassertion at STX2 6 2 5 169 Register FBh offset FBh reset 0h Figure 2 665 Register FBh 7 6 5 4 3 2 1 0 0 0 0 JESD_INTERNAL_CTR_ON_SYNC_DEASSERT1 12 8 R W 0h R W 0h R W 0h R 0h LEGEND R W Read Write W Write only n value after reset Table 2 670 Register FB Field Descriptions Bit Field Type Reset Description 7 5 0 R W 0h Must read or write 0 4 0...

Page 444: ...5 172 Register FEh offset FEh reset 0h Figure 2 668 Register FEh 7 6 5 4 3 2 1 0 JESD_INTERNAL_CTR_ON_SYNC_DEASSERT3 7 0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 673 Register FE Field Descriptions Bit Field Type Reset Description 7 0 JESD_INTERNAL_ CTR_ON_SYNC_D EASSERT3 7 0 R 0h multiframe counter value on sync_n deassertion at STX4 8 2 5 173 Register FFh offset FFh res...

Page 445: ...A 2 DATA 1 0 JESD_SYNC_STA TE_LANE0 R 0h 0 SYNC 1 ILA 2 DATA 2 5 175 Register 101h offset 101h reset 0h Figure 2 671 Register 101h 7 6 5 4 3 2 1 0 JESD_PREV_SYNC_STATE_LA NE3 JESD_PREV_SYNC_STATE_LA NE2 JESD_PREV_SYNC_STATE_LA NE1 JESD_PREV_SYNC_STATE_LA NE0 R 0h R 0h R 0h R 0h LEGEND R W Read Write W Write only n value after reset Table 2 676 Register 101 Field Descriptions Bit Field Type Reset D...

Page 446: ...er reset Table 2 678 Register 103 Field Descriptions Bit Field Type Reset Description 7 4 JESD_MISC_STAT US_LANE3 R 0h bit0 sync_req bit1 first sync req bit2 sysref req bit3 bit wise of of multiframe_end 3 0 JESD_MISC_STAT US_LANE2 R 0h bit0 sync_req bit1 first sync req bit2 sysref req bit3 bit wise of of multiframe_end 2 5 178 Register 104h offset 104h reset 0h Figure 2 674 Register 104h 7 6 5 4 ...

Page 447: ... for STX3 7 2 5 181 Register 107h offset 107h reset 0h Figure 2 677 Register 107h 7 6 5 4 3 2 1 0 JESD_SYNC_ERR_CNT_LANE3 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 682 Register 107 Field Descriptions Bit Field Type Reset Description 7 0 JESD_SYNC_ERR _CNT_LANE3 R 0h Register is relevant for JESD B Number of sync toggles after init_state removal for STX4 8 2 5 182 Register...

Page 448: ...trols first 0 3 rx streams i e rx1 data 0 No test 1 short test 2 ramp 4 alt 0 1 2 5 184 Register 10Ah offset 10Ah reset 0h Figure 2 680 Register 10Ah 7 6 5 4 3 2 1 0 0 RX2_JESD_RAMPTEST_INCR RX2_JESD_TEST_SIG_GEN_MODE R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 685 Register 10A Field Descriptions Bit Field Type Reset Description 7 7 0 R W 0h Must read or wri...

Page 449: ...Write only n value after reset Table 2 687 Register 10C Field Descriptions Bit Field Type Reset Description 7 0 JESD_SHORT_TE ST_PATTERN_INP UT0 7 0 R W 0h Used when jesd_short_test_pattern_override or fb_jesd_short_test_pattern_override are set ADC sample0 2 5 187 Register 10Dh offset 10Dh reset 0h Figure 2 683 Register 10Dh 7 6 5 4 3 2 1 0 JESD_SHORT_TEST_PATTERN_INPUT0 15 8 R W 0h LEGEND R W Re...

Page 450: ...sd_short_test_pattern_override or fb_jesd_short_test_pattern_override are set ADC sample1 2 5 190 Register 110h offset 110h reset 0h Figure 2 686 Register 110h 7 6 5 4 3 2 1 0 JESD_SHORT_TEST_PATTERN_INPUT2 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 691 Register 110 Field Descriptions Bit Field Type Reset Description 7 0 JESD_SHORT_TE ST_PATTERN_INP UT2 7 0 R W 0h Us...

Page 451: ... 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 694 Register 113 Field Descriptions Bit Field Type Reset Description 7 0 JESD_SHORT_TE ST_PATTERN_INP UT3 15 8 R W 0h Used when jesd_short_test_pattern_override or fb_jesd_short_test_pattern_override are set ADC sample3 2 5 194 Register 114h offset 114h reset 0h Figure 2 690 Register 114h 7 6 5 4 3 2 1 0 JESD_SHORT_TEST_PA...

Page 452: ...sd_short_test_pattern_override or fb_jesd_short_test_pattern_override are set ADC sample5 2 5 197 Register 117h offset 117h reset 0h Figure 2 693 Register 117h 7 6 5 4 3 2 1 0 JESD_SHORT_TEST_PATTERN_INPUT5 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 698 Register 117 Field Descriptions Bit Field Type Reset Description 7 0 JESD_SHORT_TE ST_PATTERN_INP UT5 15 8 R W 0h ...

Page 453: ...te only n value after reset Table 2 701 Register 11A Field Descriptions Bit Field Type Reset Description 7 0 JESD_SHORT_TE ST_PATTERN_INP UT7 7 0 R W 0h Used when jesd_short_test_pattern_override or fb_jesd_short_test_pattern_override are set ADC sample7 2 5 201 Register 11Bh offset 11Bh reset 0h Figure 2 697 Register 11Bh 7 6 5 4 3 2 1 0 JESD_SHORT_TEST_PATTERN_INPUT7 15 8 R W 0h LEGEND R W Read ...

Page 454: ... Write W Write only n value after reset Table 2 704 Register 11D Field Descriptions Bit Field Type Reset Description 7 2 0 R W 0h Must read or write 0 1 0 CTRL_RX3_RX4_ CLK_GATING R W 0h When set to 2 b10 all functional clock gating of rx34 mapper is disabled 2 5 204 Register 11Eh offset 11Eh reset 1h Figure 2 700 Register 11Eh 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 EN_SERDES_ FIFO_DATA_G ATING R W 0h R W ...

Page 455: ...Register 121 Field Descriptions Bit Field Type Reset Description 7 4 0 R W 0h Must read or write 0 3 2 CTRL_FB2_MSF_ SIG_INVALID R W 0h When set to 2 b10 all functional data invalid is forced to zero for data pipeline stages 1 0 CTRL_FB1_MSF_ SIG_INVALID R W 0h When set to 2 b10 all functional data invalid is forced to zero for data pipeline stages 2 5 207 Register 122h offset 122h reset 0h Figure...

Page 456: ...ster 2 2 CLEAR_DDC_RD_ CLK_FB R W 0h when set to 1 clears the MONITOR_DDC_RD_CLK_FB register 1 1 CLEAR_DDC_RD_ CLK_RX2 R W 0h when set to 1 clears the MONITOR_DDC_RD_CLK_RX2 register 0 0 CLEAR_DDC_RD_ CLK_RX1 R W 0h when set to 1 clears the MONITOR_DDC_RD_CLK_RX1 register 2 5 209 Register 125h offset 125h reset 0h Figure 2 705 Register 125h 7 6 5 4 3 2 1 0 CLEAR_JESD_ CLK_RX2_P0_ MSF_RD CLEAR_JESD...

Page 457: ...DES_TXBCLK2 register 2 2 CLEAR_SERDES_ TXBCLK1 R W 0h when set to 1 clears the MONITOR_SERDES_TXBCLK1 register 1 1 CLEAR_SERDES_ TXBCLK0 R W 0h when set to 1 clears the MONITOR_SERDES_TXBCLK0 register 0 0 CLEAR_JESD_CL K_FB_P0_MSF_R D R W 0h UNUSED 2 5 211 Register 128h offset 128h reset 0h Figure 2 707 Register 128h 7 6 5 4 3 2 1 0 CLEAR_JESD_ SYSREF_FB_P 0 CLEAR_JESD_ SYSREF_RX2_ P2 CLEAR_JESD_ ...

Page 458: ...ite only n value after reset Table 2 713 Register 129 Field Descriptions Bit Field Type Reset Description 7 7 CLEAR_JESD_SY SREF_RX2_P0_M SF_RD R W 0h UNUSED 6 6 CLEAR_JESD_SY SREF_RX1_P0_M SF_RD R W 0h UNUSED 5 5 CLEAR_JESD_SY SREF_DIV2_FB_P 3 R W 0h when set to 1 clears the MONITOR_JESD_SYSREF_DIV2_FB_P3 register 4 4 CLEAR_JESD_SY SREF_DIV2_FB_P 1 R W 0h when set to 1 clears the MONITOR_JESD_SYS...

Page 459: ... 1 1 MONITOR_DDC_R D_CLK_RX2 R 0h Monitors the DDC read clock status of RXCD Can be cleared by setting the CLEAR_DDC_RD_CLK_RX2 register to 1 0 0 MONITOR_DDC_R D_CLK_RX1 R 0h Monitors the DDC read clock status of RXAB Can be cleared by setting the CLEAR_DDC_RD_CLK_RX1 register to 1 2 5 214 Register 12Dh offset 12Dh reset 0h Figure 2 710 Register 12Dh 7 6 5 4 3 2 1 0 MONITOR_JES D_CLK_RX2_P 0_MSF_R...

Page 460: ...EAR_SERDES_TXBCLK0 register to 1 0 0 MONITOR_JESD_ CLK_FB_P0_MSF_ RD R 0h UNUSED 2 5 216 Register 130h offset 130h reset 0h Figure 2 712 Register 130h 7 6 5 4 3 2 1 0 MONITOR_JES D_SYSREF_FB _P0 MONITOR_JES D_SYSREF_R X2_P2 MONITOR_JES D_SYSREF_R X2_P0 MONITOR_JES D_SYSREF_R X1_P2 MONITOR_JES D_SYSREF_R X1_P0 MONITOR_DD C_RD_SYSRE F_FB MONITOR_DD C_RD_SYSRE F_RX2 MONITOR_DD C_RD_SYSRE F_RX1 R 0h R...

Page 461: ..._FB _P3 MONITOR_JES D_SYSREF_FB _P1 R 0h R 0h R 0h R 0h R 0h R 0h R 0h R 0h LEGEND R W Read Write W Write only n value after reset Table 2 718 Register 131 Field Descriptions Bit Field Type Reset Description 7 7 MONITOR_JESD_ SYSREF_RX2_P0 _MSF_RD R 0h UNUSED 6 6 MONITOR_JESD_ SYSREF_RX1_P0 _MSF_RD R 0h UNUSED 5 5 MONITOR_JESD_ SYSREF_DIV2_FB _P3 R 0h Monitors the internal sysref of FB Can be clea...

Page 462: ... offset 132h reset 0h Figure 2 714 Register 132h 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 MONITOR_JES D_SYSREF_FB _P0_MSF_RD R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R 0h LEGEND R W Read Write W Write only n value after reset Table 2 719 Register 132 Field Descriptions Bit Field Type Reset Description 7 1 0 R W 0h Must read or write 0 0 0 MONITOR_JESD_ SYSREF_FB_P0_ MSF_RD R 0h UNUSED ...

Page 463: ...F_CNTR_TARGET_MSB 15 8 401Ah LF_CNTR_TARGET_LSB 7 0 401Bh LF_CNTR_TARGET_LSB 15 8 401Ch HF_CNTR_TARGET 7 0 401Dh HF_CNTR_TARGET 15 8 401Fh EM_EN 4022h BP2_STATE 4023h BP_1_EN BP_2_EN SM_CONT BP1_STATE 4024h FORCE_EN_ST ATE_NUM FORCE_STATE_NUM 4025h DFE_OVERRID E_EN DFE_TAP1_VALUE 4038h OW_KP 1 0 4039h OWEN_KF OW_KF OWEN_KP OW_KP 2 403Ah CTLE_OVERRID E_EN CTLE_OVERRIDE_VAL 403Bh OWEN_DAC_SE L OW_DA...

Page 464: ...GH 15 8 409Ah READ_PRBS_ERR_LOW 7 0 409Bh READ_PRBS_ERR_LOW 15 8 409Dh LINK_STATUS 40A0h READ_THETA2 40A1h READ_PHASE 40A2h READ_THETA4 40A3h READ_THETA3 40A4h READ_MRGN_CNTR 7 0 40A5h READ_MRGN_CNTR 11 8 40AAh READ_PHASE_WANDER 7 0 40ABh READ_PHASE_WANDER 14 8 40ACh READ_RX_FREQ_ERROR 7 0 40ADh READ_RX_FREQ_ERROR 10 8 4140h TX_SPEED_SEL TX_POLARITY_ FLIP 4141h TX_TEST_DATA _SOURCE TX_PRBS_CLO CK_...

Page 465: ...ICER_BIA S_LANE3 0 49D1h RX_AGCBUFDAC_LANE3 RX_SLICER_BIAS_LANE3 2 1 49D4h RX_SLICER_BIA S_LANE2 0 49D5h RX_AGCBUFDAC_LANE2 RX_SLICER_BIAS_LANE2 2 1 49D8h RX_SLICER_BIA S_LANE1 0 49D9h RX_AGCBUFDAC_LANE1 RX_SLICER_BIAS_LANE1 2 1 49DCh RX_SLICER_BIA S_LANE0 0 49DDh RX_AGCBUFDAC_LANE0 RX_SLICER_BIAS_LANE0 2 1 49DEh TX_INTP_DIS REFCLK_DIV 49DFh INTP_INIT_EN INTP_INIT_VAL 49E0h OW_FREQ_ACC_TOP 6 0 REC...

Page 466: ...RCH _DONE_LN0 OPTICAL_MOD E PLL_CALIBR_D ONE PLL_CALIBR_R ESTART 7020h FIRMWARE_WATCHDOG 7 0 7021h FIRMWARE_WATCHDOG 15 8 7022h CTLE_SEARCH _DISABLE_LN3 CTLE_SEARCH _DISABLE_LN2 CTLE_SEARCH _DISABLE_LN1 CTLE_SEARCH _DISABLE_LN0 7028h FIRMWARE_EXEC_CTRL 7 0 7029h FIRMWARE_EXEC_CTRL 15 8 702Ah CMD_PARAM_OR_STATUSA 702Bh COMMAND RESPONSE 702Ch CMD_PARAM_OR_STATUSB 7 0 702Dh CMD_PARAM_OR_STATUSB 15 8 ...

Page 467: ...E1Fh MCU_WRITE MCU_START CHKSUM_ERR 7E20h DUMMYPAGESELECT NOTE The registers with address 0x40zz and 0x41zz are per lane registers and they can be extended to other lanes using the following map values instead of 0x40zz and 0x41zz For serdes_0 lanes SRX1 STX1 0x42zz and 0x43zz SRX2 STX2 0x40zz and 0x41zz SRX3 STX3 0x44zz and 0x45zz SRX4 STX4 0x46zz and 0x47zz For serdes_1 lanes SRX5 STX5 0x46zz an...

Page 468: ...8h Figure 2 717 Register 4002h 7 6 5 4 3 2 1 0 CNTR_TARGET_DEPTH 7 0 R W 8h LEGEND R W Read Write W Write only n value after reset Table 2 723 Register 4002 Field Descriptions Bit Field Type Reset Description 7 0 CNTR_TARGET_D EPTH 7 0 R W 8h The smaller this value the deeper the eye target 2 6 4 Register 4003h offset 4003h reset 0h Figure 2 718 Register 4003h 7 6 5 4 3 2 1 0 CNTR_TARGET_DEPTH 11 ...

Page 469: ...d_pattern_cntr_target for error rate target with format U12 0 2 6 7 Register 4006h offset 4006h reset 66h Figure 2 721 Register 4006h 7 6 5 4 3 2 1 0 RX_SD_THRESH_DETECT 7 0 R W 66h LEGEND R W Read Write W Write only n value after reset Table 2 727 Register 4006 Field Descriptions Bit Field Type Reset Description 7 0 RX_SD_THRESH_ DETECT 7 0 R W 66h Signal detect threshold level of format U11 11 T...

Page 470: ...er reset Table 2 730 Register 4009 Field Descriptions Bit Field Type Reset Description 7 4 RX_SD_CLOCK_C YCLES R W 7h Number of clock cycles that defines the signal detection window The period is defined as 2 N 6 UI where N is a 4 bit value Zero is not valid for N 3 0 RX_SD_CROSSO VER_COUNT 11 8 R W Ah The count of the number of times the incoming signal must cross the signal detect threshold leve...

Page 471: ... 1 R W 20h The initialization value2 for DFE in in S7 6 format 2 6 14 Register 4012h offset 4012h reset 18h Figure 2 728 Register 4012h 7 6 5 4 3 2 1 0 DFE_INIT_4 R W 18h LEGEND R W Read Write W Write only n value after reset Table 2 734 Register 4012 Field Descriptions Bit Field Type Reset Description 6 0 DFE_INIT_4 R W 18h The initialization value4 for DFE in value in S7 6 format 2 6 15 Register...

Page 472: ...eld Type Reset Description 6 0 LF_CNTR_THRES H R W 3Dh Overflow_threshold for overflow threshold in S7 6 format 2 6 18 Register 4018h offset 4018h reset 0h Figure 2 732 Register 4018h 7 6 5 4 3 2 1 0 LF_CNTR_TARGET_MSB 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 738 Register 4018 Field Descriptions Bit Field Type Reset Description 7 0 LF_CNTR_TARGE T_MSB 7 0 R W 0h Lo...

Page 473: ...ter 401Bh 7 6 5 4 3 2 1 0 LF_CNTR_TARGET_LSB 15 8 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 741 Register 401B Field Descriptions Bit Field Type Reset Description 7 0 LF_CNTR_TARGE T_LSB 15 8 R W 2h Low frequency component counter LSB 2 6 22 Register 401Ch offset 401Ch reset 0h Figure 2 736 Register 401Ch 7 6 5 4 3 2 1 0 HF_CNTR_TARGET 7 0 R W 0h LEGEND R W Read Write W ...

Page 474: ...nabled 2 6 25 Register 4022h offset 4022h reset 0h Figure 2 739 Register 4022h 7 6 5 4 3 2 1 0 BP2_STATE R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 745 Register 4022 Field Descriptions Bit Field Type Reset Description 4 0 BP2_STATE R W 0h Breakpoint 2 state number 2 6 26 Register 4023h offset 4023h reset 0h Figure 2 740 Register 4023h 7 6 5 4 3 2 1 0 BP_1_EN BP_2_EN SM_C...

Page 475: ...4025h offset 4025h reset 0h Figure 2 742 Register 4025h 7 6 5 4 3 2 1 0 DFE_OVERRID E_EN DFE_TAP1_VALUE R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 748 Register 4025 Field Descriptions Bit Field Type Reset Description 7 7 DFE_OVERRIDE_ EN R W 0h When enabled the DFE settings are programmed with the override values and no adaptation occurs For use in testing only 0h...

Page 476: ...e value for KP Format U3 0 2 6 31 Register 403Ah offset 403Ah reset 0h Figure 2 745 Register 403Ah 7 6 5 4 3 2 1 0 CTLE_OVERRI DE_EN CTLE_OVERRIDE_VAL R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 751 Register 403A Field Descriptions Bit Field Type Reset Description 7 7 CTLE_OVERRIDE _EN R W 0h When enabled the CTLE setting is programmed with the override values and ...

Page 477: ...E_VAL R 0h Readback value of CTLE 2 6 34 Register 4047h offset 4047h reset 0h Figure 2 748 Register 4047h 7 6 5 4 3 2 1 0 BP1_REACHE D BP2_REACHE D READ_STATE_NUM R 0h R 0h R 0h LEGEND R W Read Write W Write only n value after reset Table 2 754 Register 4047 Field Descriptions Bit Field Type Reset Description 7 7 BP1_REACHED R 0h Breakpoint 1 reached indicator signal 0h Not reached 1h Reached 6 6 ...

Page 478: ...R W Read Write W Write only n value after reset Table 2 757 Register 4062 Field Descriptions Bit Field Type Reset Description 6 0 DFE_F1_VALUE R 0h DFE F1 read back value 2 6 38 Register 4065h offset 4065h reset 0h Figure 2 752 Register 4065h 7 6 5 4 3 2 1 0 CDR_BW_VAL R 0h LEGEND R W Read Write W Write only n value after reset Table 2 758 Register 4065 Field Descriptions Bit Field Type Reset Desc...

Page 479: ... 7 6 5 4 3 2 1 0 LINK_INIT_VAL_1 10 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 761 Register 4077 Field Descriptions Bit Field Type Reset Description 2 0 LINK_INIT_VAL_1 10 8 R W 0h Initial parameter set values 1 Used during link up 2 6 42 Register 4078h offset 4078h reset F0h Figure 2 756 Register 4078h 7 6 5 4 3 2 1 0 LINK_INIT_VAL_2 7 0 R W F0h LEGEND R W Read Write ...

Page 480: ...Description 7 0 LINK_INIT_VAL_3 7 0 R W 30h Initial parameter set values 3 Used during link up 2 6 45 Register 407Bh offset 407Bh reset 0h Figure 2 759 Register 407Bh 7 6 5 4 3 2 1 0 LINK_INIT_VAL_3 10 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 765 Register 407B Field Descriptions Bit Field Type Reset Description 2 0 LINK_INIT_VAL_3 10 8 R W 0h Initial parameter set va...

Page 481: ... 7 6 5 4 3 2 1 0 TIMING_UPDN_MOD_EN 1 0 R W 3h LEGEND R W Read Write W Write only n value after reset Table 2 768 Register 4082 Field Descriptions Bit Field Type Reset Description 7 6 TIMING_UPDN_M OD_EN 1 0 R W 3h Timing up down mode enable 0h Disable 1h Enable 2 6 49 Register 4083h offset 4083h reset FFh Figure 2 763 Register 4083h 7 6 5 4 3 2 1 0 TUD_UP_RATIO TUD_DN_RATIO TIMING_UPDN_MOD_EN 3 2...

Page 482: ... of the RX PRBS checker 0h PRBS9 1h PRBS15 2h PRBS23 3h PRBS31 1 1 RX_PRBS_CHECK _EN R W 1h Enables the RX PRBS checker logic 0h Disabled 1h Enabled 0 0 RX_POLARITY_FL IP R W 0h Polarity of the incoming RX user data 0h Normal 1h Inverted 2 6 51 Register 4086h offset 4086h reset 0h Figure 2 765 Register 4086h 7 6 5 4 3 2 1 0 OWEN_THETA 2_ACC OW_THETA2_ACC R W 0h R W 0h LEGEND R W Read Write W Write...

Page 483: ...d Descriptions Bit Field Type Reset Description 7 7 OWEN_THETA4_A CC R W 0h Overwrite enable signal for OW_theta4_acc 0h Disable 1h Enable 6 0 OW_THETA4_ACC R W 0h Overwrite value for theta4_acc 7MSB 2 6 54 Register 4089h offset 4089h reset 0h Figure 2 768 Register 4089h 7 6 5 4 3 2 1 0 OWEN_THETA 3_ACC OW_THETA3_ACC R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 774 ...

Page 484: ...ng 1 0 AGC_SETTING1 5 4 R W 1h The AGC setting for the second highest peaking 2 6 57 Register 4090h offset 4090h reset 92h Figure 2 771 Register 4090h 7 6 5 4 3 2 1 0 AGC_SETTING4 AGC_SETTING5_MSB R W 24h R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 777 Register 4090 Field Descriptions Bit Field Type Reset Description 7 2 AGC_SETTING4 R W 24h The AGC setting for the fifth ...

Page 485: ...ure 2 774 Register 4093h 7 6 5 4 3 2 1 0 AGC_SETTING5_LSB AGC_SETTING6 5 2 R W Dh R W 6h LEGEND R W Read Write W Write only n value after reset Table 2 780 Register 4093 Field Descriptions Bit Field Type Reset Description 7 4 AGC_SETTING5_L SB R W Dh 4 LSBs of the AGC setting for the sixth highest peaking 3 0 AGC_SETTING6 5 2 R W 6h The AGC setting for the seventh highest peaking 2 6 61 Register 4...

Page 486: ...lf rate 5h Quarter rate 6h Eighth rate 7h Sixteenth rate 2 6 63 Register 4096h offset 4096h reset 0h Figure 2 777 Register 4096h 7 6 5 4 3 2 1 0 EDGE3 1 0 EDGE2 EDGE1 R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 783 Register 4096 Field Descriptions Bit Field Type Reset Description 7 6 EDGE3 1 0 R W 0h Timing loop Phase 3 edge delay 5 3 EDGE2 R W 0h Timing loo...

Page 487: ...3 2 1 0 READ_PRBS_ERR_HIGH 15 8 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 786 Register 4099 Field Descriptions Bit Field Type Reset Description 7 0 READ_PRBS_ERR _HIGH 15 8 R 0h Read only value of the upper word of the RX PRBS 32 bit error count 2 6 67 Register 409Ah offset 409Ah reset 0h Figure 2 781 Register 409Ah 7 6 5 4 3 2 1 0 READ_PRBS_ERR_LOW 7 0 R 0h LEGEND R W Re...

Page 488: ...ster 409D Field Descriptions Bit Field Type Reset Description 7 7 LINK_STATUS R 0h Status of the PHY 0h PHY not ready 1h PHY ready 2 6 70 Register 40A0h offset 40A0h reset 0h Figure 2 784 Register 40A0h 7 6 5 4 3 2 1 0 READ_THETA2 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 790 Register 40A0 Field Descriptions Bit Field Type Reset Description 6 0 READ_THETA2 R 0h Timing loo...

Page 489: ...A3 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 793 Register 40A3 Field Descriptions Bit Field Type Reset Description 6 0 READ_THETA3 R 0h Timing loop phase 3 readback value 2 6 74 Register 40A4h offset 40A4h reset 0h Figure 2 788 Register 40A4h 7 6 5 4 3 2 1 0 READ_MRGN_CNTR 7 0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 794 Register 40A4 Field Desc...

Page 490: ...iption 7 0 READ_PHASE_W ANDER 7 0 R 0h Timing loop phase wander readback value 2 6 77 Register 40ABh offset 40ABh reset 0h Figure 2 791 Register 40ABh 7 6 5 4 3 2 1 0 READ_PHASE_WANDER 14 8 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 797 Register 40AB Field Descriptions Bit Field Type Reset Description 6 0 READ_PHASE_W ANDER 14 8 R 0h Timing loop phase wander readback value...

Page 491: ...rite only n value after reset Table 2 800 Register 4140 Field Descriptions Bit Field Type Reset Description 6 4 TX_SPEED_SEL R W 0h TX speed select 0h Full rate 4h Half rate 5h Quarter rate 6h Eighth rate 7h Sixteenth rate 0 0 TX_POLARITY_FLI P R W 0h Polarity of the outgoing TX user data 1h Normal 0h Inverted 2 6 81 Register 4141h offset 4141h reset 40h Figure 2 795 Register 4141h 7 6 5 4 3 2 1 0...

Page 492: ...enerator 0h PRBS9 1h PRBS15 2h PRBS23 3h PRBS31 2 6 82 Register 4142h offset 4142h reset AAh Figure 2 796 Register 4142h 7 6 5 4 3 2 1 0 TX_TEST_PATTERN_HIGH 7 0 R W AAh LEGEND R W Read Write W Write only n value after reset Table 2 802 Register 4142 Field Descriptions Bit Field Type Reset Description 7 0 TX_TEST_PATTE RN_HIGH 7 0 R W AAh Upper word of the 32 bit TX test pattern memory 2 6 83 Regi...

Page 493: ...t Field Type Reset Description 7 0 TX_TEST_PATTE RN_LOW 15 8 R W AAh Lower word of the 32 bit TX test pattern memory 2 6 86 Register 41E8h offset 41E8h reset 0h Figure 2 800 Register 41E8h 7 6 5 4 3 2 1 0 VTSTGRPU_TX 2 0 ENTSTPGROU P_TX TESTMODE_TX R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 806 Register 41E8 Field Descriptions Bit Field Type Reset Descripti...

Page 494: ...er 41EBh 7 6 5 4 3 2 1 0 PU_TX_LANE VDRV_VDDR1 VDRV_VDDR2 2 1 R W 1h R W 3h R W 3h LEGEND R W Read Write W Write only n value after reset Table 2 809 Register 41EB Field Descriptions Bit Field Type Reset Description 7 7 PU_TX_LANE R W 1h Power up TX by lane 0h Power down 1h Power up 4 2 VDRV_VDDR1 R W 3h 1 0 VDRV_VDDR2 2 1 R W 3h 2 6 90 Register 41ECh offset 41ECh reset 0h Figure 2 804 Register 41...

Page 495: ... PRE_CURSOR R W 0h TX pre cursor setting 0h 000b Pre cursor 0 4h 100b Pre cursor 0 4 2h 010b Pre cursor 0 8 1h 001b Pre cursor 1 6 2 6 92 Register 41EEh offset 41EEh reset 0h Figure 2 806 Register 41EEh 7 6 5 4 3 2 1 0 TESTMODE_R X 0 VTSTGRPU_RX ENTSTPGROU P_RX R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 812 Register 41EE Field Descriptions Bit Field Type Re...

Page 496: ...1F6h 7 6 5 4 3 2 1 0 RX_CLOCKING_BIAS 4 0 PU_RX_ADC_L ANE R W 18h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 815 Register 41F6 Field Descriptions Bit Field Type Reset Description 7 3 RX_CLOCKING_BI AS 4 0 R W 18h RX clocking bias 2 2 PU_RX_ADC_LAN E R W 1h Power up RX ADC by lane 0h Power down 1h Power up 2 6 96 Register 41F7h offset 41F7h reset 6Ch Figure 2 810 Register...

Page 497: ...tom 2 6 98 Register 41FBh offset 41FBh reset 0h Figure 2 812 Register 41FBh 7 6 5 4 3 2 1 0 EXRESET_INT P ADDCAP_CLK PHASE R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 818 Register 41FB Field Descriptions Bit Field Type Reset Description 5 5 EXRESET_INTP R W 0h Reset RX Interpolator 4 4 ADDCAP_CLKPHA SE R W 0h Clock Phase Edge Delay 2 6 99 Register 41FCh offset 41FC...

Page 498: ...2 R W 1h R W 3h R W 3h LEGEND R W Read Write W Write only n value after reset Table 2 821 Register 41FE Field Descriptions Bit Field Type Reset Description 7 7 RX_AC_COUPLE_ EN R W 1h Enables RX AC coupling 0h DC coupling 1h AC coupling 6 4 VGAVDCOM1 R W 3h 3 1 VGAVDCOM2 R W 3h 2 6 102 Register 41FFh offset 41FFh reset 80h Figure 2 816 Register 41FFh 7 6 5 4 3 2 1 0 PU_RX_AGC_ LANE RX_CTLE_BIA S4 ...

Page 499: ..._INIT1 15 8 R W 80h LEGEND R W Read Write W Write only n value after reset Table 2 824 Register 4877 Field Descriptions Bit Field Type Reset Description 7 0 FREQ_INIT1 15 8 R W 80h 2 6 105 Register 4878h offset 4878h reset 7h Figure 2 819 Register 4878h 7 6 5 4 3 2 1 0 FREQ_INIT2 7 0 R W 7h LEGEND R W Read Write W Write only n value after reset Table 2 825 Register 4878 Field Descriptions Bit Fiel...

Page 500: ..._INIT3 15 8 R W 80h LEGEND R W Read Write W Write only n value after reset Table 2 828 Register 487B Field Descriptions Bit Field Type Reset Description 7 0 FREQ_INIT3 15 8 R W 80h 2 6 109 Register 487Ch offset 487Ch reset 6h Figure 2 823 Register 487Ch 7 6 5 4 3 2 1 0 FREQ_INIT4 7 0 R W 6h LEGEND R W Read Write W Write only n value after reset Table 2 829 Register 487C Field Descriptions Bit Fiel...

Page 501: ...ite only n value after reset Table 2 832 Register 49CB Field Descriptions Bit Field Type Reset Description 7 5 TX_VREG_IBIAS_ LANE2 R W 4h This register is effective only when per lane register 0xF4 9 1 pu_himode_vddr 1 0 TX_VREG_IBIAS_ LANE3 2 1 R W 0h This register is effective only when per lane register 0xF4 9 1 pu_himode_vddr 2 6 113 Register 49CCh offset 49CCh reset 80h Figure 2 827 Register...

Page 502: ... Bit Field Type Reset Description 7 7 RX_SLICER_BIAS _LANE3 0 R W 0h Controls the RX slicer bias setting for lane 4 2 6 116 Register 49D1h offset 49D1h reset 60h Figure 2 830 Register 49D1h 7 6 5 4 3 2 1 0 RX_AGCBUFDAC_LANE3 RX_SLICER_BIAS_LANE3 2 1 R W 3h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 836 Register 49D1 Field Descriptions Bit Field Type Reset Description 7 5...

Page 503: ...g for lane 3 2 6 119 Register 49D8h offset 49D8h reset 0h Figure 2 833 Register 49D8h 7 6 5 4 3 2 1 0 RX_SLICER_BI AS_LANE1 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 839 Register 49D8 Field Descriptions Bit Field Type Reset Description 7 7 RX_SLICER_BIAS _LANE1 0 R W 0h Controls the RX slicer bias setting for lane 2 2 6 120 Register 49D9h offset 49D9h reset 60h Figure...

Page 504: ... RX_SLICER_BIAS_LANE0 2 1 R W 3h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 842 Register 49DD Field Descriptions Bit Field Type Reset Description 7 5 RX_AGCBUFDAC_ LANE0 R W 3h Controls AGC output driver for lane 1 1 0 RX_SLICER_BIAS _LANE0 2 1 R W 0h Controls the RX slicer bias setting for lane 1 2 6 123 Register 49DEh offset 49DEh reset 0h Figure 2 837 Register 49DEh 7...

Page 505: ..._ CLK_SEL R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 845 Register 49E0 Field Descriptions Bit Field Type Reset Description 7 1 OW_FREQ_ACC_ TOP 6 0 R W 0h 0 0 RECOVERED_CL K_SEL R W 0h Mux control bit selecting lane RX recovered clock or external recovered clock as input for TX PLL 0h External recovered clock 1h master rx_sel clk When this is selected bit 15 14 ar...

Page 506: ...P_ TX R W 0h 2 6 128 Register 49E3h offset 49E3h reset F0h Figure 2 842 Register 49E3h 7 6 5 4 3 2 1 0 PU_TX_DRV_L ANE0 PU_TX_DRV_L ANE1 PU_TX_DRV_L ANE2 PU_TX_DRV_L ANE3 TEST_MODE_TX VTSTPGROUP _TX 4 R W 1h R W 1h R W 1h R W 1h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 848 Register 49E3 Field Descriptions Bit Field Type Reset Description 7 7 PU_TX_DRV_LAN E0 R W...

Page 507: ...1 R W 3h R W 3h LEGEND R W Read Write W Write only n value after reset Table 2 850 Register 49E5 Field Descriptions Bit Field Type Reset Description 4 2 TX_PLL_BIAS2 R W 3h Controls the TX PLL bias setting 2 1 0 TX_PLL_BIAS1 2 1 R W 3h Controls the TX PLL bias setting 1 2 6 131 Register 49E6h offset 49E6h reset 10h Figure 2 845 Register 49E6h 7 6 5 4 3 2 1 0 TX_PLL_VCO_ RANGE_MSB R W 1h LEGEND R W...

Page 508: ...ps NRZ rate 26Gbps 4h 22Gbps NRZ rate 24Gbps 5h 21Gbps NRZ rate 23Gbps 6h 20Gbps NRZ rate 22Gbps 7h 19Gbps NRZ rate 21Gbps 2 6 134 Register 49EAh offset 49EAh reset B4h Figure 2 848 Register 49EAh 7 6 5 4 3 2 1 0 PU_TX_PLL TX_CHARGE_PUMP_CUR TX_VCO_CURRENT R W 1h R W 3h R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 854 Register 49EA Field Descriptions Bit Field Type Reset D...

Page 509: ...EL R W 1h Mux control to select either the reference clock or a recovered clock for the TX PLL See register PzF0 for recovered clock options 0h Recovered clock 1h Reference clock 2 6 137 Register 49EDh offset 49EDh reset 9Ch Figure 2 851 Register 49EDh 7 6 5 4 3 2 1 0 TX_PLL_BIAS4 PU_TX_BAND GAP PU_RVDD_TX EN_RVDDVCO _TX R W 4h R W 1h R W 1h R W 1h LEGEND R W Read Write W Write only n value after ...

Page 510: ...r Serdes debug only 2 6 140 Register 49F0h offset 49F0h reset 40h Figure 2 854 Register 49F0h 7 6 5 4 3 2 1 0 PU_RX_INTP_ LANE3 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 860 Register 49F0 Field Descriptions Bit Field Type Reset Description 6 6 PU_RX_INTP_LAN E3 R W 1h Power up RX Lane 3 interpolator 0h Power down 1h Power up 2 6 141 Register 49F1h offset 49F1h reset 92h...

Page 511: ...3 ADC 0h Power down 1h Power up 2 6 143 Register 49F3h offset 49F3h reset AAh Figure 2 857 Register 49F3h 7 6 5 4 3 2 1 0 PU_RX_ADC_ MASTER PU_RX_ADC_L ANE0 PU_RX_ADC_L ANE1 PU_RX_ADC_L ANE2 R W 1h R W 1h R W 1h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 863 Register 49F3 Field Descriptions Bit Field Type Reset Description 7 7 PU_RX_ADC_MAS TER R W 1h Power up RX ADC mas...

Page 512: ...nge settings see Register PzFDh RX PLL VCO RANGE LSB 2 6 146 Register 49FAh offset 49FAh reset 48h Figure 2 860 Register 49FAh 7 6 5 4 3 2 1 0 VRVDD_RX VRVDD2_RX R W 4h R W 4h LEGEND R W Read Write W Write only n value after reset Table 2 866 Register 49FA Field Descriptions Bit Field Type Reset Description 6 4 VRVDD_RX R W 4h 3 1 VRVDD2_RX R W 4h 2 6 147 Register 49FBh offset 49FBh reset 60h Figu...

Page 513: ...bps NRZ rate 21Gbps 2 6 149 Register 49FDh offset 49FDh reset A5h Figure 2 863 Register 49FDh 7 6 5 4 3 2 1 0 RX_PLL_N R W A5h LEGEND R W Read Write W Write only n value after reset Table 2 869 Register 49FD Field Descriptions Bit Field Type Reset Description 7 0 RX_PLL_N R W A5h RX PLL clock multiplier where the PLL frequency PLL reference clock 2 PLL_N The SerDes user rate 2 PLL frequency 2 6 15...

Page 514: ... Write only n value after reset Table 2 872 Register 6E01 Field Descriptions Bit Field Type Reset Description 7 7 SRAM_ECC_EN R W 1h When set enables SRAM ECC generation and checking 6 5 SRAM_ECC_FOR CE_ERR_TYPE R W 0h Allows for forcing SRAM ECC errors for debug 00 No error 01 Complement bit 0 of SRAM input data after ECC 10 Complement bit 1 of SRAM input data after ECC 11 Complement bits 0 and 1...

Page 515: ... Lane 2 data bus width selection bit 0h 39 0 is valid 40 bit data bus width 1h 19 0 is valid 20 bit data bus width 1 1 BUS_WIDTH_LAN E1 R W 0h Lane 1 data bus width selection bit 0h 39 0 is valid 40 bit data bus width 1h 19 0 is valid 20 bit data bus width 0 0 BUS_WIDTH_LAN E0 R W 0h Lane 0 data bus width selection bit 0h 39 0 is valid 40 bit data bus width 1h 19 0 is valid 20 bit data bus width 2...

Page 516: ...eset logic FIFO and PHY 888h ALL_RESET Reset all FIFO PHY register map and CPU 999h REGISTER_RESET Reset register map AAAh CPU_RESET Reset CPU This stops firmware from running To stop firmware execution set this field to 0xAAA and register Zz0B bit 15 to 0 000h Clear Note that you must clear this field between reset operations All other values are INVALID do not use 2 6 158 Register 701Eh offset 7...

Page 517: ...END R W Read Write W Write only n value after reset Table 2 879 Register 7020 Field Descriptions Bit Field Type Reset Description 7 0 FIRMWARE_WAT CHDOG 7 0 R 0h Contents increment by a count of 1 approximately every second Use to verify that firmware is operating 2 6 160 Register 7021h offset 7021h reset 0h Figure 2 874 Register 7021h 7 6 5 4 3 2 1 0 FIRMWARE_WATCHDOG 15 8 R 0h LEGEND R W Read Wr...

Page 518: ...e W Write only n value after reset Table 2 882 Register 7028 Field Descriptions Bit Field Type Reset Description 7 0 FIRMWARE_EXEC _CTRL 7 0 R W 0h Read 0000h Firmware is not downloaded or running 6A6Ah Firmware download was successful and execution has started Write FFF0h To reload firmware write this register to 0xFFF0 and restart CPU by writing a value of 0xAAA and then 0x000 to the DOMAIN_RESE...

Page 519: ...ister 702B Field Descriptions Bit Field Type Reset Description 7 4 COMMAND R W 0h Command 0x0 Command processed response from MCU 0x1 Start eye diagram data collection 0x2 Read eye diagram progress percentage 0x3 Read eye diagram data 0x4 Cancel eye diagram data collection 0x5 0xE Reserved 0xF Read firmware revision hash code 3 0 RESPONSE R W 0h Response Status response from MCU 0x0 Eye diagram pl...

Page 520: ... LEGEND R W Read Write W Write only n value after reset Table 2 888 Register 702F Field Descriptions Bit Field Type Reset Description 7 7 SRAM_BIST_EN R W 0h Enter SRAM BIST mode Prepare for BIST 6 6 SRAM_BIST_STA RT R W 0h SRAM BIST start 5 5 ROM_BIST_CLK_ EN R W 0h ROM BIST Clock Gate 0h Disable 1h Enable 4 4 ROM_BIST_EN R W 0h ROM BIST Test Enable 0h Disable 1h Enable 2 6 169 Register 7031h off...

Page 521: ...ter 7033h 7 6 5 4 3 2 1 0 ROM_BIST_OUT_MSB 15 8 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 891 Register 7033 Field Descriptions Bit Field Type Reset Description 7 0 ROM_BIST_OUT_ MSB 15 8 R 0h ROM BIST test result MSB bits 31 16 2 6 172 Register 7034h offset 7034h reset 0h Figure 2 886 Register 7034h 7 6 5 4 3 2 1 0 ROM_BIST_OUT_LSB 7 0 R 0h LEGEND R W Read Write W Write o...

Page 522: ...DET_LANE0_ OW_EN R W 0h Enable lane 0 signal detect overwrite 6 6 SIG_DET_LANE0_ OW_VAL R W 0h Lane 0 signal detect overwrite 5 5 SIG_DET_LANE1_ OW_EN R W 0h Enable lane 1 signal detect overwrite 4 4 SIG_DET_LANE1_ OW_VAL R W 0h Lane 1 signal detect overwrite 3 3 SIG_DET_LANE2_ OW_EN R W 0h Enable lane 2 signal detect overwrite 2 2 SIG_DET_LANE2_ OW_VAL R W 0h Lane 2 signal detect overwrite 1 1 SI...

Page 523: ...eset 0h Figure 2 891 Register 7E02h 7 6 5 4 3 2 1 0 FIRMWARE_DATA1 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 897 Register 7E02 Field Descriptions Bit Field Type Reset Description 7 0 FIRMWARE_DATA 1 7 0 R W 0h Firmware word holding register When this register is used for eye diagram data access is read only and the value depends on the data written to the register 2...

Page 524: ...set 0h Figure 2 894 Register 7E05h 7 6 5 4 3 2 1 0 FIRMWARE_DATA2 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 900 Register 7E05 Field Descriptions Bit Field Type Reset Description 7 0 FIRMWARE_DATA 2 15 8 R W 0h Firmware word holding register When this register is used for eye diagram data access is read only and the value depends on the data written to the register ...

Page 525: ...eset 0h Figure 2 897 Register 7E08h 7 6 5 4 3 2 1 0 FIRMWARE_DATA4 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 903 Register 7E08 Field Descriptions Bit Field Type Reset Description 7 0 FIRMWARE_DATA 4 7 0 R W 0h Firmware word holding register When this register is used for eye diagram data access is read only and the value depends on the data written to the register 2...

Page 526: ...set 0h Figure 2 900 Register 7E0Bh 7 6 5 4 3 2 1 0 FIRMWARE_DATA5 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 906 Register 7E0B Field Descriptions Bit Field Type Reset Description 7 0 FIRMWARE_DATA 5 15 8 R W 0h Firmware word holding register When this register is used for eye diagram data access is read only and the value depends on the data written to the register ...

Page 527: ...eset 0h Figure 2 903 Register 7E0Eh 7 6 5 4 3 2 1 0 FIRMWARE_DATA7 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 909 Register 7E0E Field Descriptions Bit Field Type Reset Description 7 0 FIRMWARE_DATA 7 7 0 R W 0h Firmware word holding register When this register is used for eye diagram data access is read only and the value depends on the data written to the register 2...

Page 528: ...set 0h Figure 2 906 Register 7E11h 7 6 5 4 3 2 1 0 FIRMWARE_DATA8 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 912 Register 7E11 Field Descriptions Bit Field Type Reset Description 7 0 FIRMWARE_DATA 8 15 8 R W 0h Firmware word holding register When this register is used for eye diagram data access is read only and the value depends on the data written to the register ...

Page 529: ...eset 0h Figure 2 909 Register 7E14h 7 6 5 4 3 2 1 0 FIRMWARE_DATAA 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 915 Register 7E14 Field Descriptions Bit Field Type Reset Description 7 0 FIRMWARE_DATA A 7 0 R W 0h Firmware word holding register When this register is used for eye diagram data access is read only and the value depends on the data written to the register 2...

Page 530: ...h reset 0h Figure 2 912 Register 7E17h 7 6 5 4 3 2 1 0 FIRMWARE_DATAB 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 918 Register 7E17 Field Descriptions Bit Field Type Reset Description 7 0 FIRMWARE_DATA B 15 8 R W 0h Firmware word holding register When this register is used for eye diagram data access is read only and the value depends on the data written to the regis...

Page 531: ...7E1Ah reset 0h Figure 2 915 Register 7E1Ah 7 6 5 4 3 2 1 0 RAM_ADDRESS_LOW 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 921 Register 7E1A Field Descriptions Bit Field Type Reset Description 7 0 RAM_ADDRESS_L OW 7 0 R W 0h RAM_ADDRESS 15 0 When this register is used for eye diagram data access is read only and the value depends on the data written to the register 2 6 20...

Page 532: ...gister 7E1Dh 7 6 5 4 3 2 1 0 FIRMWARE_CHECKSUM 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 924 Register 7E1D Field Descriptions Bit Field Type Reset Description 7 0 FIRMWARE_CHE CKSUM 15 8 R W 0h Specifies the checksum for the entire frame When this register is used for eye diagram data access is read only and the value depends on the data written to the register 2 6...

Page 533: ...s is read only and the value depends on the data written to the register The entire register 15 0 holds the eye diagram data 6 6 MCU_START R W 0h AHB sets this bit to 1 to tell MCU to start execution When this register is used for eye diagram data access is read only and the value depends on the data written to the register 5 5 CHKSUM_ERR R 0h MCU sets this bit to indicate a checksum error has occ...

Page 534: ...t 10Ch reset 0h Figure 2 922 Register 10Ch 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 EN_REFDIV_D MP R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 929 Register 10C Field Descriptions Bit Field Type Reset Description 7 1 0 R W 0h Must read or write 0 0 0 EN_REFDIV_DMP R W 0h reference clock divider Need to be engaged only if reference cloc...

Page 535: ...ad Write W Write only n value after reset Table 2 932 Register 10F Field Descriptions Bit Field Type Reset Description 7 7 0 R W 0h Must read or write 0 6 0 CTL_FBDIV_DIV R W 12h Feedback divider 18 is default assuming 9Ghz dac 2 7 5 Register 110h offset 110h reset 0h Figure 2 926 Register 110h 7 6 5 4 3 2 1 0 0 0 0 0 0 0 CTL_OUTDIV_MUX_TX R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R ...

Page 536: ...X R W 1h Mux for chosing rx clock Similar to tx mux usually here divn is chosen 2 7 8 Register 113h offset 113h reset 2h Figure 2 929 Register 113h 7 6 5 4 3 2 1 0 0 0 0 0 0 CTL_OUTDIV_DIV_RX R W 0h R W 0h R W 0h R W 0h R W 0h R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 936 Register 113 Field Descriptions Bit Field Type Reset Description 7 3 0 R W 0h Must read or write 0 ...

Page 537: ... Maps 2 7 10 Register 115h offset 115h reset 2h Figure 2 931 Register 115h 7 6 5 4 3 2 1 0 0 0 0 0 0 CTL_OUTDIV_DIV_FB R W 0h R W 0h R W 0h R W 0h R W 0h R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 938 Register 115 Field Descriptions Bit Field Type Reset Description 7 3 0 R W 0h Must read or write 0 2 0 CTL_OUTDIV_DIV _FB R W 2h ...

Page 538: ... 23 16 B3h MACRO_OPERAND_REG4 31 24 B4h MACRO_OPERAND_REG5 7 0 B5h MACRO_OPERAND_REG5 15 8 B6h MACRO_OPERAND_REG5 23 16 B7h MACRO_OPERAND_REG5 31 24 B8h MACRO_OPERAND_REG6 7 0 B9h MACRO_OPERAND_REG6 15 8 BAh MACRO_OPERAND_REG6 23 16 BBh MACRO_OPERAND_REG6 31 24 BCh MACRO_OPERAND_REG7 7 0 BDh MACRO_OPERAND_REG7 15 8 BEh MACRO_OPERAND_REG7 23 16 BFh MACRO_OPERAND_REG7 31 24 C0h MACRO_OPERAND_REG8 7 ...

Page 539: ...PERAND_REG18 31 24 ECh MACRO_OPERAND_REG19 7 0 EDh MACRO_OPERAND_REG19 15 8 EEh MACRO_OPERAND_REG19 23 16 EFh MACRO_OPERAND_REG19 31 24 F0h MACRO_ERRO R_IN_EXECUTI ON MACRO_ERRO R_IN_OPERAN D MACRO_ERRO R_OPCODE_NO T_ALLOWED MACRO_ERRO R_IN_OPCODE MACRO_ERRO R MACRO_DONE MACRO_ACK MACRO_READY F1h MACRO_ERROR_OPCODE F2h MACRO_ERROR_EXTENDED_CODE 7 0 F3h MACRO_ERROR_EXTENDED_CODE 15 8 F4h MACRO_ERRO...

Page 540: ...MACRO_RESULT_REG9 31 24 120h MACRO_RESULT_REG10 7 0 121h MACRO_RESULT_REG10 15 8 122h MACRO_RESULT_REG10 23 16 123h MACRO_RESULT_REG10 31 24 124h MACRO_RESULT_REG11 7 0 125h MACRO_RESULT_REG11 15 8 126h MACRO_RESULT_REG11 23 16 127h MACRO_RESULT_REG11 31 24 128h MACRO_RESULT_REG12 7 0 129h MACRO_RESULT_REG12 15 8 12Ah MACRO_RESULT_REG12 23 16 12Bh MACRO_RESULT_REG12 31 24 12Ch MACRO_RESULT_REG13 7...

Page 541: ...G0 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 941 Register A1 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG0 15 8 R W 0h Macro operand register 0 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 3 Register A2h offset A2h reset 0h Figure 2 934 Register A2h 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG0 23 16 R W 0h L...

Page 542: ...rand register 1 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 6 Register A5h offset A5h reset 0h Figure 2 937 Register A5h 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG1 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 945 Register A5 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG1 15 8 R W 0h Macro operand register 1 I...

Page 543: ..._REG2 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 948 Register A8 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG2 7 0 R W 0h Macro operand register 2 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 10 Register A9h offset A9h reset 0h Figure 2 941 Register A9h 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG2 15 8 R W 0h ...

Page 544: ... operand register 2 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 13 Register ACh offset ACh reset 0h Figure 2 944 Register ACh 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG3 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 952 Register AC Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG3 7 0 R W 0h Macro operand register ...

Page 545: ..._REG3 31 24 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 955 Register AF Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG3 31 24 R W 0h Macro operand register 3 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 17 Register B0h offset B0h reset 0h Figure 2 948 Register B0h 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG4 7 0 R W ...

Page 546: ...perand register 4 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 20 Register B3h offset B3h reset 0h Figure 2 951 Register B3h 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG4 31 24 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 959 Register B3 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG4 31 24 R W 0h Macro operand registe...

Page 547: ...EG5 23 16 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 962 Register B6 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG5 23 16 R W 0h Macro operand register 5 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 24 Register B7h offset B7h reset 0h Figure 2 955 Register B7h 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG5 31 24 R W ...

Page 548: ...and register 6 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 27 Register BAh offset BAh reset 0h Figure 2 958 Register BAh 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG6 23 16 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 966 Register BA Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG6 23 16 R W 0h Macro operand register 6...

Page 549: ...G7 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 969 Register BD Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG7 15 8 R W 0h Macro operand register 7 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 31 Register BEh offset BEh reset 0h Figure 2 962 Register BEh 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG7 23 16 R W 0h ...

Page 550: ...rand register 8 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 34 Register C1h offset C1h reset 0h Figure 2 965 Register C1h 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG8 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 973 Register C1 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG8 15 8 R W 0h Macro operand register 8 ...

Page 551: ...D_REG9 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 976 Register C4 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG9 7 0 R W 0h Macro operand register 9 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 38 Register C5h offset C5h reset 0h Figure 2 969 Register C5h 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG9 15 8 R W 0h...

Page 552: ...erand register 9 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 41 Register C8h offset C8h reset 0h Figure 2 972 Register C8h 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG10 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 980 Register C8 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG10 7 0 R W 0h Macro operand register 1...

Page 553: ...EG10 31 24 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 983 Register CB Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG10 31 24 R W 0h Macro operand register 10 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 45 Register CCh offset CCh reset 0h Figure 2 976 Register CCh 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG11 7 0 R ...

Page 554: ...erand register 11 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 48 Register CFh offset CFh reset 0h Figure 2 979 Register CFh 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG11 31 24 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 987 Register CF Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG11 31 24 R W 0h Macro operand regis...

Page 555: ...12 23 16 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 990 Register D2 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG12 23 16 R W 0h Macro operand register 12 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 52 Register D3h offset D3h reset 0h Figure 2 983 Register D3h 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG12 31 24 R ...

Page 556: ...d register 13 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 55 Register D6h offset D6h reset 0h Figure 2 986 Register D6h 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG13 23 16 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 994 Register D6 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG13 23 16 R W 0h Macro operand register ...

Page 557: ...4 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 997 Register D9 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG14 15 8 R W 0h Macro operand register 14 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 59 Register DAh offset DAh reset 0h Figure 2 990 Register DAh 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG14 23 16 R W 0...

Page 558: ...nd register 15 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 62 Register DDh offset DDh reset 0h Figure 2 993 Register DDh 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG15 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1001 Register DD Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG15 15 8 R W 0h Macro operand register ...

Page 559: ...EG16 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1004 Register E0 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG16 7 0 R W 0h Macro operand register 16 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 66 Register E1h offset E1h reset 0h Figure 2 997 Register E1h 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG16 15 8 R W ...

Page 560: ...erand register 16 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 69 Register E4h offset E4h reset 0h Figure 2 1000 Register E4h 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG17 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1008 Register E4 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG17 7 0 R W 0h Macro operand registe...

Page 561: ...EG17 31 24 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1011 Register E7 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG17 31 24 R W 0h Macro operand register 17 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 73 Register E8h offset E8h reset 0h Figure 2 1004 Register E8h 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG18 7 0 ...

Page 562: ...rand register 18 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 76 Register EBh offset EBh reset 0h Figure 2 1007 Register EBh 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG18 31 24 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1015 Register EB Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG18 31 24 R W 0h Macro operand regi...

Page 563: ...Register EE Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPERAN D_REG19 23 16 R W 0h Macro operand register 19 Interpretation of the operand s in this register are dependent on MACRO_OPCODE 2 8 80 Register EFh offset EFh reset 0h Figure 2 1011 Register EFh 7 6 5 4 3 2 1 0 MACRO_OPERAND_REG19 31 24 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1019 Register ...

Page 564: ...esent in the subsequent register fields 2 2 MACRO_DONE R 0h Value of 1 indicates completion of the latest macro command 1 1 MACRO_ACK R 0h Value of 1 indicates acknowledgment of the receipt of the latest macro command 0 0 MACRO_READY R 0h Value of 1 indicates that device is ready is receive a new macro command Value of 0 indicates that the latest macro command is still under process and hence devi...

Page 565: ... F4h 7 6 5 4 3 2 1 0 MACRO_ERROR_EXTENDED_CODE_2 7 0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1024 Register F4 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_ERROR_ EXTENDED_COD E_2 7 0 R 0h Field contains information about the nature of error in case of ERROR_IN_OPERAND or ERROR_IN_EXECUTION Interpretation of this depends on the specific MACRO_OPCODE that...

Page 566: ...OR_EXTENDED_CODE_2 31 24 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1027 Register F7 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_ERROR_ EXTENDED_COD E_2 31 24 R 0h Field contains information about the nature of error in case of ERROR_IN_OPERAND or ERROR_IN_EXECUTION Interpretation of this depends on the specific MACRO_OPCODE that caused the error 2 8 89 R...

Page 567: ...esult register 0 Interpretation of the contents of this register depend on the last macro command 2 8 92 Register FBh offset FBh reset 0h Figure 2 1023 Register FBh 7 6 5 4 3 2 1 0 MACRO_RESULT_REG0 31 24 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1031 Register FB Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG0 31 24 R 0h Macro result register 0 ...

Page 568: ...REG1 23 16 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1034 Register FE Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG1 23 16 R 0h Macro result register 1 Interpretation of the contents of this register depend on the last macro command 2 8 96 Register FFh offset FFh reset 0h Figure 2 1027 Register FFh 7 6 5 4 3 2 1 0 MACRO_RESULT_REG1 31 24 R 0h L...

Page 569: ... register 2 Interpretation of the contents of this register depend on the last macro command 2 8 99 Register 102h offset 102h reset 0h Figure 2 1030 Register 102h 7 6 5 4 3 2 1 0 MACRO_RESULT_REG2 23 16 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1038 Register 102 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG2 23 16 R 0h Macro result register 2 I...

Page 570: ...REG3 15 8 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1041 Register 105 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG3 15 8 R 0h Macro result register 3 Interpretation of the contents of this register depend on the last macro command 2 8 103 Register 106h offset 106h reset 0h Figure 2 1034 Register 106h 7 6 5 4 3 2 1 0 MACRO_RESULT_REG3 23 16 R 0...

Page 571: ...t register 4 Interpretation of the contents of this register depend on the last macro command 2 8 106 Register 109h offset 109h reset 0h Figure 2 1037 Register 109h 7 6 5 4 3 2 1 0 MACRO_RESULT_REG4 15 8 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1045 Register 109 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG4 15 8 R 0h Macro result register 4 I...

Page 572: ...ULT_REG5 7 0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1048 Register 10C Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG5 7 0 R 0h Macro result register 5 Interpretation of the contents of this register depend on the last macro command 2 8 110 Register 10Dh offset 10Dh reset 0h Figure 2 1041 Register 10Dh 7 6 5 4 3 2 1 0 MACRO_RESULT_REG5 15 8 R ...

Page 573: ...esult register 5 Interpretation of the contents of this register depend on the last macro command 2 8 113 Register 110h offset 110h reset 0h Figure 2 1044 Register 110h 7 6 5 4 3 2 1 0 MACRO_RESULT_REG6 7 0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1052 Register 110 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG6 7 0 R 0h Macro result register 6...

Page 574: ...LT_REG6 31 24 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1055 Register 113 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG6 31 24 R 0h Macro result register 6 Interpretation of the contents of this register depend on the last macro command 2 8 117 Register 114h offset 114h reset 0h Figure 2 1048 Register 114h 7 6 5 4 3 2 1 0 MACRO_RESULT_REG7 7 0 ...

Page 575: ...ult register 7 Interpretation of the contents of this register depend on the last macro command 2 8 120 Register 117h offset 117h reset 0h Figure 2 1051 Register 117h 7 6 5 4 3 2 1 0 MACRO_RESULT_REG7 31 24 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1059 Register 117 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG7 31 24 R 0h Macro result register...

Page 576: ..._REG8 23 16 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1062 Register 11A Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG8 23 16 R 0h Macro result register 8 Interpretation of the contents of this register depend on the last macro command 2 8 124 Register 11Bh offset 11Bh reset 0h Figure 2 1055 Register 11Bh 7 6 5 4 3 2 1 0 MACRO_RESULT_REG8 31 24 ...

Page 577: ... register 9 Interpretation of the contents of this register depend on the last macro command 2 8 127 Register 11Eh offset 11Eh reset 0h Figure 2 1058 Register 11Eh 7 6 5 4 3 2 1 0 MACRO_RESULT_REG9 23 16 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1066 Register 11E Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG9 23 16 R 0h Macro result register 9 ...

Page 578: ...G10 15 8 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1069 Register 121 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG10 15 8 R 0h Macro result register 10 Interpretation of the contents of this register depend on the last macro command 2 8 131 Register 122h offset 122h reset 0h Figure 2 1062 Register 122h 7 6 5 4 3 2 1 0 MACRO_RESULT_REG10 23 16 R...

Page 579: ...register 11 Interpretation of the contents of this register depend on the last macro command 2 8 134 Register 125h offset 125h reset 0h Figure 2 1065 Register 125h 7 6 5 4 3 2 1 0 MACRO_RESULT_REG11 15 8 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1073 Register 125 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG11 15 8 R 0h Macro result register 11...

Page 580: ...T_REG12 7 0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1076 Register 128 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG12 7 0 R 0h Macro result register 12 Interpretation of the contents of this register depend on the last macro command 2 8 138 Register 129h offset 129h reset 0h Figure 2 1069 Register 129h 7 6 5 4 3 2 1 0 MACRO_RESULT_REG12 15 8 ...

Page 581: ...ult register 12 Interpretation of the contents of this register depend on the last macro command 2 8 141 Register 12Ch offset 12Ch reset 0h Figure 2 1072 Register 12Ch 7 6 5 4 3 2 1 0 MACRO_RESULT_REG13 7 0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1080 Register 12C Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG13 7 0 R 0h Macro result register ...

Page 582: ..._REG13 31 24 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1083 Register 12F Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG13 31 24 R 0h Macro result register 13 Interpretation of the contents of this register depend on the last macro command 2 8 145 Register 130h offset 130h reset 0h Figure 2 1076 Register 130h 7 6 5 4 3 2 1 0 MACRO_RESULT_REG14 7 ...

Page 583: ...lt register 14 Interpretation of the contents of this register depend on the last macro command 2 8 148 Register 133h offset 133h reset 0h Figure 2 1079 Register 133h 7 6 5 4 3 2 1 0 MACRO_RESULT_REG14 31 24 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1087 Register 133 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG14 31 24 R 0h Macro result regist...

Page 584: ...EG15 23 16 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1090 Register 136 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG15 23 16 R 0h Macro result register 15 Interpretation of the contents of this register depend on the last macro command 2 8 152 Register 137h offset 137h reset 0h Figure 2 1083 Register 137h 7 6 5 4 3 2 1 0 MACRO_RESULT_REG15 31 2...

Page 585: ...egister 16 Interpretation of the contents of this register depend on the last macro command 2 8 155 Register 13Ah offset 13Ah reset 0h Figure 2 1086 Register 13Ah 7 6 5 4 3 2 1 0 MACRO_RESULT_REG16 23 16 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1094 Register 13A Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG16 23 16 R 0h Macro result register 1...

Page 586: ...G17 15 8 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1097 Register 13D Field Descriptions Bit Field Type Reset Description 7 0 MACRO_RESULT_ REG17 15 8 R 0h Macro result register 17 Interpretation of the contents of this register depend on the last macro command 2 8 159 Register 13Eh offset 13Eh reset 0h Figure 2 1090 Register 13Eh 7 6 5 4 3 2 1 0 MACRO_RESULT_REG17 23 16 R...

Page 587: ...this register depend on the last macro command 2 8 161 Register 193h offset 193h reset 0h Figure 2 1092 Register 193h 7 6 5 4 3 2 1 0 MACRO_OPCODE R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1100 Register 193 Field Descriptions Bit Field Type Reset Description 7 0 MACRO_OPCODE R W 0h A write to this register triggers a macro operation in the microcontroller The 8 bit valu...

Page 588: ...1093 Register 6Ch 7 6 5 4 3 2 1 0 SPI_AGC_DSA_FB R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1102 Register 6C Field Descriptions Bit Field Type Reset Description 5 0 SPI_AGC_DSA_FB R W 0h SPI register for changing mission mode gain in FB Uses this value when fbmuxel is indicating msb as 1 Meaning no fb is connected or when enable_fbmuxel_for_fbdsa is 0 2 9 2 Register 6Dh ...

Page 589: ...nly n value after reset Table 2 1105 Register 78 Field Descriptions Bit Field Type Reset Description 5 0 SPI_AGC_DSA_FB _0 R W 0h In case FB muxsel is used for changing the dsa setting for FB These registers needs to be programmed Value of dsa gain when fbmuxel is 0 ie fb is connected to txa 2 9 5 Register 79h offset 79h reset 0h Figure 2 1097 Register 79h 7 6 5 4 3 2 1 0 ENABLE_FBM UXSEL_FOR_F BD...

Page 590: ...1 0 SPI_AGC_DSA_FB_3 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1109 Register 84 Field Descriptions Bit Field Type Reset Description 5 0 SPI_AGC_DSA_FB _3 R W 0h dsa value when fbmuxsel indicates txd is fedback to this channel 2 9 9 Register C8h offset C8h reset 0h Figure 2 1101 Register C8h 7 6 5 4 3 2 1 0 TXA_DSA_FINE TXA_DSA_INDEX R W 0h R W 0h LEGEND R W Read Write W...

Page 591: ... R W Read Write W Write only n value after reset Table 2 1112 Register D0 Field Descriptions Bit Field Type Reset Description 7 0 TXA_DSA_DIG0_G AIN R W 18h DIg gain0 is for band0 There is a mask for these registers as well By choosing the mask only any desired trigger for CP can be created Normally the mask may be programmed so that only ana index trigger the CP dsa change mask is present in SpiA...

Page 592: ...ter D8 Field Descriptions Bit Field Type Reset Description 7 0 TXA_DSA_DIG1_G AIN R W 18h For Band1 2 9 14 Register DCh offset DCh reset 18h Figure 2 1106 Register DCh 7 6 5 4 3 2 1 0 TXB_DSA_DIG1_GAIN R W 18h LEGEND R W Read Write W Write only n value after reset Table 2 1115 Register DC Field Descriptions Bit Field Type Reset Description 7 0 TXB_DSA_DIG1_G AIN R W 18h for band1 ...

Page 593: ..._G6_E N DDh PIN_AGC_MAX_DLY E0h FDSA_PIN_UNCERT_CYC E1h FDSA_MAX_ATTN E4h TM_PKDET_CUST_EXTEND_TIME E8h NO_OVR_LNA_ BYP_WITH_SW AP ECh TM_GPIO_EXIT EDh TM_GPIO_EXIT _EN EEh TM_CUST_PKDET_INDEX 120h USE_INTAGC_F OR_LNA_RXA 124h SPI_AGC_DSA_A 125h LNA_BYP_EN_RXA 12Ch FDSA_OFFSET_VAL_A 12Dh FDSA_INIT_VAL_A 130h RX_SWAP_SETTING_A_1 131h RX_SWAP_SETTING_A_2 132h RX_SWAP_SETTING_A_3 133h SWAP_PIN_GA TE_...

Page 594: ...h MASK_DIG1_TX B 213h USE_SYNC_TRI G_B 214h TXB_SW0_FINE TXB_DSA_INDEX_SWAP0 218h TXB_DSA_DIG0_GAIN_SWAP0 21Ch TXB_DSA_DIG1_GAIN_SWAP0 220h TXB_SW1_FINE TXB_DSA_INDEX_SWAP1 224h TXB_DSA_DIG0_GAIN_SWAP1 228h TXB_DSA_DIG1_GAIN_SWAP1 2 10 1 Register 80h offset 80h reset 3h Figure 2 1107 Register 80h 7 6 5 4 3 2 1 0 GAIN_CTRL_FB R W 3h LEGEND R W Read Write W Write only n value after reset Table 2 111...

Page 595: ...ield Type Reset Description 5 0 FB_SWAP_SETTI NG_2 R W 0h FB DSA setting for swap select of 10 2 10 4 Register 8Ah offset 8Ah reset 0h Figure 2 1110 Register 8Ah 7 6 5 4 3 2 1 0 FB_SWAP_SETTING_3 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1120 Register 8A Field Descriptions Bit Field Type Reset Description 5 0 FB_SWAP_SETTI NG_3 R W 0h FB DSA setting for swap select of 1...

Page 596: ... 2 1113 Register 8Eh 7 6 5 4 3 2 1 0 LNA_BYP_SETTING_3_FB R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1123 Register 8E Field Descriptions Bit Field Type Reset Description 1 0 LNA_BYP_SETTIN G_3_FB R W 0h FB LNA bypass setting for swap select of 11 2 10 8 Register 90h offset 90h reset 0h Figure 2 1114 Register 90h 7 6 5 4 3 2 1 0 SWAP_PIN_G ATE_FB R W 0h LEGEND R W Read Wr...

Page 597: ...END R W Read Write W Write only n value after reset Table 2 1126 Register D4 Field Descriptions Bit Field Type Reset Description 1 0 EXT_LNA_CON_E N_RX R W 1h Enable mask for LNA bypass The default value is 01 which means a single lna is enabled The default need not be changed for typical use cases 2 10 11 Register D5h offset D5h reset 32h Figure 2 1117 Register D5h 7 6 5 4 3 2 1 0 MAX_ANA_ATTN R ...

Page 598: ...W 28h The threshold at which dsa gain switches to LNA This is applicable only DSA_LNA_SW_MODE is set to 1 2 10 14 Register DAh offset DAh reset 1Eh Figure 2 1120 Register DAh 7 6 5 4 3 2 1 0 LNA_ATTEN_VALUE R W 1Eh LEGEND R W Read Write W Write only n value after reset Table 2 1130 Register DA Field Descriptions Bit Field Type Reset Description 5 0 LNA_ATTEN_VAL UE R W 1Eh The external LNA attenua...

Page 599: ...et E0h reset 0h Figure 2 1123 Register E0h 7 6 5 4 3 2 1 0 FDSA_PIN_UNCERT_CYC R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1133 Register E0 Field Descriptions Bit Field Type Reset Description 2 0 FDSA_PIN_UNCE RT_CYC R W 0h Max expected uncertainity in cycles in ADC_rate 4 clock cycles for FDSA 2 10 18 Register E1h offset E1h reset 32h Figure 2 1124 Register E1h 7 6 5 4 3...

Page 600: ...ITH_SWAP R W 1h If this bit is set gain swap doesn t change LNA values However when this is zero swapping change LNA settings to swapped values 2 10 21 Register ECh offset ECh reset 0h Figure 2 1127 Register ECh 7 6 5 4 3 2 1 0 TM_GPIO_EXI T R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1137 Register EC Field Descriptions Bit Field Type Reset Description 0 0 TM_GPIO_EXIT R ...

Page 601: ...set 1h Figure 2 1130 Register 120h 7 6 5 4 3 2 1 0 USE_INTAGC_ FOR_LNA_RX A R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 1140 Register 120 Field Descriptions Bit Field Type Reset Description 0 0 USE_INTAGC_FO R_LNA_RXA R W 1h Choses whether to use internal AGC or external AGC for LNA of RxA 2 10 25 Register 124h offset 124h reset 0h Figure 2 1131 Register 124h 7 6 5 4 3 2 ...

Page 602: ...T_V AL_A R W 0h For FDSA mode offset value the factor which is scaled used in DSA value calculation This value is scaled to derive the final DSA attenuation This is for RxA 2 10 28 Register 12Dh offset 12Dh reset 0h Figure 2 1134 Register 12Dh 7 6 5 4 3 2 1 0 FDSA_INIT_VAL_A R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1144 Register 12D Field Descriptions Bit Field Type Re...

Page 603: ...37 Register 132h 7 6 5 4 3 2 1 0 RX_SWAP_SETTING_A_3 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1147 Register 132 Field Descriptions Bit Field Type Reset Description 5 0 RX_SWAP_SETTI NG_A_3 R W 0h Swap setting for swap select of 11 for RxA 2 10 32 Register 133h offset 133h reset 0h Figure 2 1138 Register 133h 7 6 5 4 3 2 1 0 SWAP_PIN_G ATE_A R W 0h LEGEND R W Read Write...

Page 604: ...eset Description 1 0 LNA_BYP_SETTIN G_2_RXA R W 0h LNA setting for swap select of 10 for RxA 2 10 35 Register 136h offset 136h reset 0h Figure 2 1141 Register 136h 7 6 5 4 3 2 1 0 LNA_BYP_SETTING_3_RXA R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1151 Register 136 Field Descriptions Bit Field Type Reset Description 1 0 LNA_BYP_SETTIN G_3_RXA R W 0h LNA setting for swap sel...

Page 605: ... after reset Table 2 1154 Register 175 Field Descriptions Bit Field Type Reset Description 1 0 LNA_BYP_EN_RX B R W 0h Mission mode LNA gain settable by SPI for RxB Normally LSB is the one to be written In dual LNA mode MSB is used 2 10 39 Register 17Ch offset 17Ch reset 0h Figure 2 1145 Register 17Ch 7 6 5 4 3 2 1 0 FDSA_OFFSET_VAL_B R W 0h LEGEND R W Read Write W Write only n value after reset Ta...

Page 606: ...it Field Type Reset Description 5 0 RX_SWAP_SETTI NG_B_1 R W 0h Swap setting for swap select of 01 for RxB 2 10 42 Register 181h offset 181h reset 0h Figure 2 1148 Register 181h 7 6 5 4 3 2 1 0 RX_SWAP_SETTING_B_2 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1158 Register 181 Field Descriptions Bit Field Type Reset Description 5 0 RX_SWAP_SETTI NG_B_2 R W 0h Swap setting f...

Page 607: ... 5 4 3 2 1 0 LNA_BYP_SETTING_1_RXB R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1161 Register 184 Field Descriptions Bit Field Type Reset Description 1 0 LNA_BYP_SETTIN G_1_RXB R W 0h LNA setting for swap select of 01 for RxB 2 10 46 Register 185h offset 185h reset 0h Figure 2 1152 Register 185h 7 6 5 4 3 2 1 0 LNA_BYP_SETTING_2_RXB R W 0h LEGEND R W Read Write W Write onl...

Page 608: ...et 1BDh reset 0h Figure 2 1155 Register 1BDh 7 6 5 4 3 2 1 0 DIS_TXDSALA TCH R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1165 Register 1BD Field Descriptions Bit Field Type Reset Description 0 0 DIS_TXDSALATC H R W 0h If this bit is set to 1 tx dsa latch will no longer generate gain change 2 10 50 Register 1C0h offset 1C0h reset 0h Figure 2 1156 Register 1C0h 7 6 5 4 3 2 ...

Page 609: ...rite W Write only n value after reset Table 2 1168 Register 1C2 Field Descriptions Bit Field Type Reset Description 0 0 MASK_DIG1_TXA R W 0h Mask change pulse generation with diggain1 2 10 53 Register 1C3h offset 1C3h reset 0h Figure 2 1159 Register 1C3h 7 6 5 4 3 2 1 0 USE_SYNC_T RIG_A R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1169 Register 1C3 Field Descriptions Bit F...

Page 610: ...e 2 1171 Register 1C8 Field Descriptions Bit Field Type Reset Description 7 0 TXA_DSA_DIG0_G AIN_SWAP0 R W 0h TxA diggain0 during swap select of 01 2 10 56 Register 1CCh offset 1CCh reset 0h Figure 2 1162 Register 1CCh 7 6 5 4 3 2 1 0 TXA_DSA_DIG1_GAIN_SWAP0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1172 Register 1CC Field Descriptions Bit Field Type Reset Description 7...

Page 611: ...5 Register 1D8h 7 6 5 4 3 2 1 0 TXA_DSA_DIG1_GAIN_SWAP1 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1175 Register 1D8 Field Descriptions Bit Field Type Reset Description 7 0 TXA_DSA_DIG1_G AIN_SWAP1 R W 0h TxA diggain1 value during swap select of 10 2 10 60 Register 210h offset 210h reset 0h Figure 2 1166 Register 210h 7 6 5 4 3 2 1 0 MASK_ANA_T XB R W 0h LEGEND R W Read ...

Page 612: ... Pulse generation for diggain1 2 10 63 Register 213h offset 213h reset 0h Figure 2 1169 Register 213h 7 6 5 4 3 2 1 0 USE_SYNC_T RIG_B R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1179 Register 213 Field Descriptions Bit Field Type Reset Description 0 0 USE_SYNC_TRIG _B R W 0h If this is set only writing to the TxB causes the Change Pulses generation 2 10 64 Register 214h ...

Page 613: ... W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1182 Register 21C Field Descriptions Bit Field Type Reset Description 7 0 TXB_DSA_DIG1_G AIN_SWAP0 R W 0h TxB diggain1 during swap select 01 2 10 67 Register 220h offset 220h reset 0h Figure 2 1173 Register 220h 7 6 5 4 3 2 1 0 TXB_SW1_FINE TXB_DSA_INDEX_SWAP1 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset T...

Page 614: ...pe Reset Description 7 0 TXB_DSA_DIG0_G AIN_SWAP1 R W 0h TxB diggain0 value during swap select 10 2 10 69 Register 228h offset 228h reset 0h Figure 2 1175 Register 228h 7 6 5 4 3 2 1 0 TXB_DSA_DIG1_GAIN_SWAP1 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1185 Register 228 Field Descriptions Bit Field Type Reset Description 7 0 TXB_DSA_DIG1_G AIN_SWAP1 R W 0h TxB diggain1 va...

Page 615: ...AD_ALARM_PREMASK 23 16 113h SPI_READ_ALARM_PREMASK 31 24 114h SPI_READ_ALARM_BUS0 7 0 115h SPI_READ_ALARM_BUS0 15 8 116h SPI_READ_ALARM_BUS0 23 16 117h SPI_READ_ALARM_BUS0 31 24 118h SPI_READ_ALARM_BUS1 7 0 119h SPI_READ_ALARM_BUS1 15 8 11Ah SPI_READ_ALARM_BUS1 23 16 11Bh SPI_READ_ALARM_BUS1 31 24 150h OBS_FUNC_SPI_CHAIN_AUTOLOAD_ERROR OBS_FUNC_SPI_CHAIN_AUTOLOAD_DONE 151h OBS_FUNC_SPI _EFC_INFORM...

Page 616: ...ptions Bit Field Type Reset Description 7 0 ALARM_MASK_LS B_FOR_ALARM0 1 5 8 R W 0h Mask bits for alarm condition of LSB first 16 alarm condtions A high value at a bit position indicates the corresponding alarm condition is not used in the final alarm generation There are two alarms 0 1 and this one correspond to alarm0 Bit8 0 Bit9 PLL lock alarm Bit10 to Bit15 0 2 11 3 Register 102h offset 102h r...

Page 617: ...ns A high value at a bit position indicates the corresponding alarm condition is not used in the final alarm generation There are two alarms 0 1 and this one correspond to alarm1 Bit0 Jesd subchip alarm Bit1 tx1_pap_alarm_out 0 Bit2 tx2_pap_alarm_out 0 Bit3 tx1_pap_alarm_out 1 Bit4 tx2_pap_alarm_out 1 Bit5 spi_alarm_out Bit6 Bit7 0 2 11 6 Register 105h offset 105h reset 0h Figure 2 1181 Register 1...

Page 618: ...Field Type Reset Description 7 0 ALARM_MASK_M SB_FOR_ALARM1 15 8 R W 80h Mask bits for alarm condition of MSB last 16 alarm condtions A high value at a bit position indicates the corresponding alarm condition is not used in the final alarm generation There are two alarms 0 1 and this one correspond to alarm1 Bit8 to Bit15 0 2 11 9 Register 10Ch offset 10Ch reset 0h Figure 2 1184 Register 10Ch 7 6 ...

Page 619: ... 6 5 4 3 2 1 0 SPI_READ_ALARM_PREMASK 23 16 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1198 Register 112 Field Descriptions Bit Field Type Reset Description 7 0 SPI_READ_ALAR M_PREMASK 23 1 6 R 0h Reads the value of 32 alarms prior to mask 2 11 13 Register 113h offset 113h reset 0h Figure 2 1188 Register 113h 7 6 5 4 3 2 1 0 SPI_READ_ALARM_PREMASK 31 24 R 0h LEGEND R W Rea...

Page 620: ...READ_ALAR M_BUS0 15 8 R 0h Reads the value of 32 alarms after the mask corresponding to Alarm0 2 11 16 Register 116h offset 116h reset 0h Figure 2 1191 Register 116h 7 6 5 4 3 2 1 0 SPI_READ_ALARM_BUS0 23 16 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1202 Register 116 Field Descriptions Bit Field Type Reset Description 7 0 SPI_READ_ALAR M_BUS0 23 16 R 0h Reads the value of...

Page 621: ... 1 0 SPI_READ_ALARM_BUS1 15 8 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1205 Register 119 Field Descriptions Bit Field Type Reset Description 7 0 SPI_READ_ALAR M_BUS1 15 8 R 0h Reads the value of 32 alarms after the mask corresponding to Alarm1 2 11 20 Register 11Ah offset 11Ah reset 0h Figure 2 1195 Register 11Ah 7 6 5 4 3 2 1 0 SPI_READ_ALARM_BUS1 23 16 R 0h LEGEND R W ...

Page 622: ...e Reset Description 7 4 OBS_FUNC_SPI_ CHAIN_AUTOLOA D_ERROR R 0h Observation port for autoload_error 3 0 OBS_FUNC_SPI_ CHAIN_AUTOLOA D_DONE R 0h Observation port for autoload_done 2 11 23 Register 151h offset 151h reset 0h Figure 2 1198 Register 151h 7 6 5 4 3 2 1 0 OBS_FUNC_S PI_EFC_INFO RMATION OBS_FUNC_S PI_EFC_ERRO R R 0h R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1209...

Page 623: ...W Write only n value after reset Table 2 1211 Register 161 Field Descriptions Bit Field Type Reset Description 1 1 OBS_FUNC_SPI_ EFC_INFORMATI ON R 0h Observation port for efc information 0 0 OBS_FUNC_SPI_ EFC_ERROR R 0h Observation port for efc_error 2 11 26 Register 170h offset 170h reset 0h Figure 2 1201 Register 170h 7 6 5 4 3 2 1 0 PLL_REG_SPI _REQ_A R W 0h LEGEND R W Read Write W Write only ...

Page 624: ...fset 190h reset 3h Figure 2 1203 Register 190h 7 6 5 4 3 2 1 0 MISC_SPI_GL OBAL_PDN_SI G MISC_SPI_GL OBAL_PDN_C TRL R W 1h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 1214 Register 190 Field Descriptions Bit Field Type Reset Description 1 1 MISC_SPI_GLOBA L_PDN_SIG R W 1h In case register override is set the value of this register is used instead of global PDN pin 0 0 MIS...

Page 625: ...23 16 107h TX_DUC_BAND0_MIXER1_NCO1_FCW 31 24 110h TX_DUC_BAND0_MIXER1_NCO0_PHASE_OFFSET 7 0 111h TX_DUC_BAND0_MIXER1_NCO0_PHASE_OFFSET 15 8 114h TX_DUC_BAND0_MIXER1_NCO1_PHASE_OFFSET 7 0 115h TX_DUC_BAND0_MIXER1_NCO1_PHASE_OFFSET 15 8 120h TX_DUC_BAND0_MIXER1_NCO0_FRAC_FCW_NUM 7 0 121h TX_DUC_BAND0_MIXER1_NCO0_FRAC_FCW_NUM 15 8 122h TX_DUC_BAND0_MIXER1_NCO0_FRAC_FCW_DEN 7 0 123h TX_DUC_BAND0_MIXE...

Page 626: ...S_ CH_COMBINE_ EN TX_DUC_OTHE R_CH_COMBIN E_EN 31Ch TX_DUC_DAC_ DITHER_CONFI G0 31Eh TX_DUC_DAC_DITHER_CONFIG2 31Fh TX_DUC_DAC_DITHER_CONFIG4 TX_DUC_DAC_DITHER_CONFIG3 320h TX_DUC_DAC_DITHER_FCW0 350h TX_DUC_MIXER2_NCO0_FCW 7 0 351h TX_DUC_MIXER2_NCO0_FCW 15 8 352h TX_DUC_MIXER2_NCO0_FCW 23 16 353h TX_DUC_MIXER2_NCO0_FCW 31 24 354h TX_DUC_MIXER2_NCO1_FCW 7 0 355h TX_DUC_MIXER2_NCO1_FCW 15 8 356h T...

Page 627: ...ROR_WINDOW_COUNTER 7 0 513h TX_DUAL_BAND_COMBINER_PAP_MOVING_AVERAGE_ERROR_WIND OW_COUNTER 11 8 514h TX_DUAL_BAND_COMBINER_PAP_MOVING_AVERAGE_ERROR_THRESHOLD 7 0 515h TX_DUAL_BAND_COMBINER_PAP_MOVING_AVERAGE_ERROR_THRE SHOLD 11 8 516h TX_DUAL_BAND_COMBINER_PAP_MOVING_AVERAGE_ACCUMULATOR_THRESHOLD 7 0 517h TX_DUAL_BAN D_COMBINER_ PAP_MOVING_ AVERAGE_ACC UMULATOR_TH RESHOLD 8 518h TX_DUAL_BAN D_COMB...

Page 628: ...M_CLR 7 0 54Dh TX_PAP_OTHER_TX_PAP_ALARM_CLR 10 8 54Eh TX_PAP_OTHER_TX_PAP_ALARM_MASK 7 0 54Fh TX_PAP_OTHER_TX_PAP_ALARM_MASK 10 8 550h TX_PAP_EN_O VER_RANGE_W IND_COUNTER 554h TX_PAP_OVER_RANGE_WINDOW_COUNTER 7 0 555h TX_PAP_OVER_RANGE_WINDOW_COUNTER 11 8 556h TX_PAP_OVER_RANGE_ERROR_THRESHOLD 7 0 557h TX_PAP_OVER_RANGE_ERROR_THRESHOLD 11 8 558h TX_PAP_ALARM_STATUS 559h TX_PAP_UNMASK_STATUS 55Ch ...

Page 629: ..._MA_UPDAT E_SAMPLES TX_PAP_DUAL_ BAND_COMBIN ER_MA_MODE_ NO_AVG 584h TX_PAP_DUAL_BAND_COMBINER_DET_ALARM_ST ATUS 585h TX_PAP_DUAL_BAND_COMBINER_DET_UNMASK_S TATUS 588h TX_IP_PAP_EN _PAP_BAND1 589h TX_IP_PAP_DET_ALARM_CLR 58Ah TX_IP_PAP_DET_ALARM_MASK 58Ch TX_IP_PAP_HP F_UPDATE_SA MPLES TX_IP_PAP_HP F_MODE_NO_A VG TX_IP_PAP_MA _UPDATE_SAM PLES TX_IP_PAP_MA _MODE_NO_AV G 590h TX_IP_PAP_DET_ALARM_STA...

Page 630: ...ion The value to the programmed is a function of the interpolation1 interpolation factor as well as in some cases the mixer1 mode configuration interpolation2 configuration etc The correct optimal value to use is automatically determined if System Configuration Macros are used Not all interpolation1 interpolation factors are valid for all DAC rates and or DAC DIG clock ratios so it is highly recom...

Page 631: ...h Figure 2 1207 Register 46h 7 6 5 4 3 2 1 0 TX_DUC_MIXER1_MODE_CONFIG1 R W 4h LEGEND R W Read Write W Write only n value after reset Table 2 1219 Register 46 Field Descriptions Bit Field Type Reset Description 3 0 TX_DUC_MIXER1 _MODE_CONFIG1 R W 4h Mixer1 Mode Configuration1 Value depends on whether mixer1 is engaged at all and if engaged at what sampling rate in relation to the TX Digital clock ...

Page 632: ...is a function of the interpolation2 interpolation factor as well as the percentage bandwidth at the interpolator2 input sampling rate that is to be preserved by the interpolation2 interpolation filters The correct optimal value to use is automatically determined if System Configuration Macros are used Not all interpolation2 interpolation factors are valid for all DAC rates and or DAC DIG clock rat...

Page 633: ...2 12 9 Register 64h offset 64h reset 0h Figure 2 1212 Register 64h 7 6 5 4 3 2 1 0 TX_DUC_FIFO_CONFIG0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1224 Register 64 Field Descriptions Bit Field Type Reset Description 4 0 TX_DUC_FIFO_C ONFIG0 R W 0h TX DUC FIFO Configuration0 Value dependent on interplation factor DAC rate etc Optimal value automatically determined if Syste...

Page 634: ...t 4h Figure 2 1215 Register 68h 7 6 5 4 3 2 1 0 TX_DUC_FIFO_CONFIG3 R W 4h LEGEND R W Read Write W Write only n value after reset Table 2 1227 Register 68 Field Descriptions Bit Field Type Reset Description 2 0 TX_DUC_FIFO_C ONFIG3 R W 4h TX DUC FIFO Configuration3 Value dependent on interplation factor DAC rate etc Optimal value automatically determined if System Configuration Macros are used 2 1...

Page 635: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1230 Register 100 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_BAND0_ MIXER1_NCO0_F CW 7 0 R W 0h Mixer 1 Frequency control word FCW for nco0 of band0 The System Configuration Macros automatically and optimally partition the overall center frequency between Mixer1 and Mixer2 and are hence strongly recommended 2 12...

Page 636: ...3 2 1 0 TX_DUC_BAND0_MIXER1_NCO0_FCW 31 24 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1233 Register 103 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_BAND0_ MIXER1_NCO0_F CW 31 24 R W 0h Mixer 1 Frequency control word FCW for nco0 of band0 The System Configuration Macros automatically and optimally partition the overall center frequency between Mixer1 an...

Page 637: ... 1 0 TX_DUC_BAND0_MIXER1_NCO1_FCW 23 16 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1236 Register 106 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_BAND0_ MIXER1_NCO1_F CW 23 16 R W 0h Mixer 1 Frequency control word FCW for nco1 of band0 The System Configuration Macros automatically and optimally partition the overall center frequency between Mixer1 and M...

Page 638: ...2 24 Register 111h offset 111h reset 0h Figure 2 1227 Register 111h 7 6 5 4 3 2 1 0 TX_DUC_BAND0_MIXER1_NCO0_PHASE_OFFSET 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1239 Register 111 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_BAND0_ MIXER1_NCO0_P HASE_OFFSET 15 8 R W 0h Offset phase for nco0 of band0 in Mixer 1 2 12 25 Register 114h offset 114h r...

Page 639: ...30 Register 120h 7 6 5 4 3 2 1 0 TX_DUC_BAND0_MIXER1_NCO0_FRAC_FCW_NUM 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1242 Register 120 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_BAND0_ MIXER1_NCO0_F RAC_FCW_NUM 7 0 R W 0h Numerator of the fractional fequency control word for nco0 of band0 in Mixer 1 Signed number 2 12 28 Register 121h offset 121h res...

Page 640: ...123h reset 8h Figure 2 1233 Register 123h 7 6 5 4 3 2 1 0 TX_DUC_BAND0_MIXER1_NCO0_FRAC_FCW_DEN 15 8 R W 8h LEGEND R W Read Write W Write only n value after reset Table 2 1245 Register 123 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_BAND0_ MIXER1_NCO0_F RAC_FCW_DEN 1 5 8 R W 8h Denominator of the fractional fequency control word for nco0 of band0 in Mixer1 Unsigned number 2 12 3...

Page 641: ...6h reset 0h Figure 2 1236 Register 126h 7 6 5 4 3 2 1 0 TX_DUC_BAND0_MIXER1_NCO1_FRAC_FCW_DEN 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1248 Register 126 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_BAND0_ MIXER1_NCO1_F RAC_FCW_DEN 7 0 R W 0h Denominator of the fractional fequency control word for nco1 of band0 in Mixer1 Unsigned number 2 12 34 Reg...

Page 642: ...gister 131h offset 131h reset 0h Figure 2 1239 Register 131h 7 6 5 4 3 2 1 0 TX_DUC_BAN D0_MIXER1_N CO1_FCW_FO RCE_RELOAD R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1251 Register 131 Field Descriptions Bit Field Type Reset Description 0 0 TX_DUC_BAND0_ MIXER1_NCO1_F CW_FORCE_REL OAD R W 0h A 0 1 0 sequence on this bit can be used to force a re load of the FCW in the band...

Page 643: ... 1 0 TX_DUC_BAND1_MIXER1_NCO0_FCW 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1254 Register 201 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_BAND1_ MIXER1_NCO0_F CW 15 8 R W 0h Mixer 1 Frequency control word FCW for nco0 of Band1 The System Configuration Macros automatically and optimally partition the overall center frequency between Mixer1 and Mix...

Page 644: ... 3 2 1 0 TX_DUC_BAND1_MIXER1_NCO1_FCW 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1257 Register 204 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_BAND1_ MIXER1_NCO1_F CW 7 0 R W 0h Mixer 1 Frequency control word FCW for nco1 of Band1 The System Configuration Macros automatically and optimally partition the overall center frequency between Mixer1 and M...

Page 645: ...12 45 Register 207h offset 207h reset 0h Figure 2 1248 Register 207h 7 6 5 4 3 2 1 0 TX_DUC_BAND1_MIXER1_NCO1_FCW 31 24 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1260 Register 207 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_BAND1_ MIXER1_NCO1_F CW 31 24 R W 0h Mixer 1 Frequency control word FCW for nco1 of Band1 The System Configuration Macros automat...

Page 646: ...12 48 Register 214h offset 214h reset 0h Figure 2 1251 Register 214h 7 6 5 4 3 2 1 0 TX_DUC_BAND1_MIXER1_NCO1_PHASE_OFFSET 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1263 Register 214 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_BAND1_ MIXER1_NCO1_P HASE_OFFSET 7 0 R W 0h Offset phase for nco1 of Band1 in Mixer 1 2 12 49 Register 215h offset 215h re...

Page 647: ...1h reset 0h Figure 2 1254 Register 221h 7 6 5 4 3 2 1 0 TX_DUC_BAND1_MIXER1_NCO0_FRAC_FCW_NUM 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1266 Register 221 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_BAND1_ MIXER1_NCO0_F RAC_FCW_NUM 1 5 8 R W 0h Numerator of the fractional fequency control word for nco0 of Band1 in Mixer 1 Signed number 2 12 52 Reg...

Page 648: ...et 224h reset 0h Figure 2 1257 Register 224h 7 6 5 4 3 2 1 0 TX_DUC_BAND1_MIXER1_NCO1_FRAC_FCW_NUM 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1269 Register 224 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_BAND1_ MIXER1_NCO1_F RAC_FCW_NUM 7 0 R W 0h Numerator of the fractional fequency control word for nco1 of Band1 in Mixer 1 Signed number 2 12 55 R...

Page 649: ...e 2 1260 Register 227h 7 6 5 4 3 2 1 0 TX_DUC_BAND1_MIXER1_NCO1_FRAC_FCW_DEN 15 8 R W 8h LEGEND R W Read Write W Write only n value after reset Table 2 1272 Register 227 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_BAND1_ MIXER1_NCO1_F RAC_FCW_DEN 1 5 8 R W 8h Denominator of the fractional fequency control word for nco1 of Band1 in Mixer1 Unsigned number 2 12 58 Register 230h off...

Page 650: ...1 nco1 in Mixer1 Will break phase coherence 2 12 60 Register 242h offset 242h reset 0h Figure 2 1263 Register 242h 7 6 5 4 3 2 1 0 TX_DUC_BAN D1_MIXER1_C ONFIG2 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1275 Register 242 Field Descriptions Bit Field Type Reset Description 0 0 TX_DUC_BAND1_ MIXER1_CONFIG2 R W 0h Enable fractional FCW mode in the Mixer 1 Band1 NCO 0 Disab...

Page 651: ...2 1278 Register 314 Field Descriptions Bit Field Type Reset Description 1 1 TX_DUC_THIS_C H_COMBINE_EN R W 1h Add data from the current TX DUC in a 2T pair after the mixer Along with other_ch_combine_en 1 see above this can be used to realize a quad band DUC configuration 0 Don t add data 1 Add data from current DUC 0 0 TX_DUC_OTHER_ CH_COMBINE_EN R W 0h Add data from the other TX DUC in a 2T pair...

Page 652: ...I G3 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1281 Register 31F Field Descriptions Bit Field Type Reset Description 4 2 TX_DUC_DAC_DI THER_CONFIG4 R W 0h Fine amplitude scale control for DAC data dither 0 1 default 1 scaling of 3 4 approx 2 5 dB 2 scaling of 5 4 approx 1 9 dB 1 0 TX_DUC_DAC_DI THER_CONFIG3 R W 0h Coase amplitude scale control for DAC data dither...

Page 653: ...7 6 5 4 3 2 1 0 TX_DUC_MIXER2_NCO0_FCW 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1284 Register 351 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_MIXER2 _NCO0_FCW 15 8 R W 0h Mixer 2 Frequency control word FCW for nco0 The System Configuration Macros automatically and optimally partition the overall center frequency between Mixer1 and Mixer2 and are...

Page 654: ...354h 7 6 5 4 3 2 1 0 TX_DUC_MIXER2_NCO1_FCW 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1287 Register 354 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_MIXER2 _NCO1_FCW 7 0 R W 0h Mixer 2 Frequency control word FCW for nco1 The System Configuration Macros automatically and optimally partition the overall center frequency between Mixer1 and Mixer2 and ...

Page 655: ...0 TX_DUC_MIXER2_NCO1_FCW 31 24 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1290 Register 357 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_MIXER2 _NCO1_FCW 31 2 4 R W 0h Mixer 2 Frequency control word FCW for nco1 The System Configuration Macros automatically and optimally partition the overall center frequency between Mixer1 and Mixer2 and are hence stro...

Page 656: ...r 393h 7 6 5 4 3 2 1 0 TX_DUC_MIXER2_NCO1_PHASE_OFFSET 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1294 Register 393 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_MIXER2 _NCO1_PHASE_O FFSET 15 8 R W 0h Offset phase for nco1 in Mixer 2 2 12 80 Register 3C0h offset 3C0h reset 0h Figure 2 1283 Register 3C0h 7 6 5 4 3 2 1 0 TX_DUC_MIXER2_NCO0_FMULT 7 0 R...

Page 657: ...te W Write only n value after reset Table 2 1297 Register 3C2 Field Descriptions Bit Field Type Reset Description 5 0 TX_DUC_MIXER2 _NCO0_FMULT 21 16 R W 0h Frequency shift corresponding to the fcw of nco0 in Mixer2 expressed in kHz modulo Fdac 16 Value programmed here should correspond to the nco0 fcw and should be a value between 0 and Fdac 16 The System Configuration Macros automatically and op...

Page 658: ...C6h offset 3C6h reset 0h Figure 2 1288 Register 3C6h 7 6 5 4 3 2 1 0 TX_DUC_MIXER2_NCO1_FMULT 21 16 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1300 Register 3C6 Field Descriptions Bit Field Type Reset Description 5 0 TX_DUC_MIXER2 _NCO1_FMULT 21 16 R W 0h Frequency shift corresponding to the fcw of nco1 in Mixer2 expressed in kHz modulo Fdac 16 Value programmed here shou...

Page 659: ...W_DEN 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1303 Register 402 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_MIXER2 _NCO0_FRAC_FC W_DEN 7 0 R W 0h Denominator of the fractional fequency control word for nco0 in Mixer2 Unsigned number 2 12 89 Register 403h offset 403h reset 8h Figure 2 1292 Register 403h 7 6 5 4 3 2 1 0 TX_DUC_MIXER2_NCO0_FRAC_FCW...

Page 660: ... Numerator of the fractional fequency control word for nco1 in Mixer 2 Signed number 2 12 92 Register 406h offset 406h reset 0h Figure 2 1295 Register 406h 7 6 5 4 3 2 1 0 TX_DUC_MIXER2_NCO1_FRAC_FCW_DEN 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1307 Register 406 Field Descriptions Bit Field Type Reset Description 7 0 TX_DUC_MIXER2 _NCO1_FRAC_FC W_DEN 7 0 R W 0h Den...

Page 661: ...3 2 1 0 TX_DUC_MIXE R2_FMIXER_F RAC_CORR_E N R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1310 Register 447 Field Descriptions Bit Field Type Reset Description 0 0 TX_DUC_MIXER2 _FMIXER_FRAC_ CORR_EN R W 0h Enable fractional FCW mode in the Mixer2 NCO 0 disable fractional correction 1 enable fractional correction 2 12 96 Register 460h offset 460h reset 0h Figure 2 1299 Reg...

Page 662: ...use is strongly recommended 2 12 98 Register 500h offset 500h reset 1h Figure 2 1301 Register 500h 7 6 5 4 3 2 1 0 TX_PAP_RAM P_MULT_TDD_ GATE R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 1313 Register 500 Field Descriptions Bit Field Type Reset Description 0 0 TX_PAP_RAMP_M ULT_TDD_GATE R W 1h Control for ungate gate of PA Protection ramp multiplication with data during T...

Page 663: ...mmed in register tx_pap_ramp_mult_data 1 Regular TX Data 2 On PA protection trigger the last good sample is held The bad sample is not propagated in the TX chain 3 Reserved 2 12 101 Register 503h offset 503h reset 1h Figure 2 1304 Register 503h 7 6 5 4 3 2 1 0 TX_PAP_RAM P_MULT_EN R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 1316 Register 503 Field Descriptions Bit Field T...

Page 664: ...BINER _PAP_MODE_ MOVING_AVE RAGE_EN R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1319 Register 510 Field Descriptions Bit Field Type Reset Description 0 0 TX_DUAL_BAND_ COMBINER_PAP_ MODE_MOVING_ AVERAGE_EN R W 0h Enable the Moving Average MA mode in dual band combiner PA Protection detector 0 Disable 1 Enable 2 12 105 Register 511h offset 511h reset 0h Figure 2 1308 Regis...

Page 665: ...in the register tx_dual_band_combiner_pap_moving_average_error_threshol d 2 12 107 Register 513h offset 513h reset 0h Figure 2 1310 Register 513h 7 6 5 4 3 2 1 0 TX_DUAL_BAND_COMBINER_PAP_MOVING_AVERAGE_ERROR _WINDOW_COUNTER 11 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1322 Register 513 Field Descriptions Bit Field Type Reset Description 3 0 TX_DUAL_BAND_ COMBINER_PAP...

Page 666: ...on 3 0 TX_DUAL_BAND_ COMBINER_PAP_ MOVING_AVERAG E_ERROR_THRES HOLD 11 8 R W 0h In the Dual band combiner PA Protection moving average module when the moving average exceeds a thershold error hit is generated The PA protection can be triggered when the number of such hits in a programmable window exceeds the count threshold The moving average count threshold can be programmed in the range 0 to 2 1...

Page 667: ...e 0 to 512 The threshold is interpreted as programmed_value 256 For example value of 256 implies the envelope threshold 1 2 12 112 Register 518h offset 518h reset 0h Figure 2 1315 Register 518h 7 6 5 4 3 2 1 0 TX_DUAL_BAN D_COMBINER _PAP_MODE_ HPF_EN R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1327 Register 518 Field Descriptions Bit Field Type Reset Description 0 0 TX_DU...

Page 668: ...h reset 0h Figure 2 1317 Register 51Ah 7 6 5 4 3 2 1 0 TX_DUAL_BAND_COMBINER_ PAP_HPF_AVERAGING_SAMP LE_COUNT R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1329 Register 51A Field Descriptions Bit Field Type Reset Description 1 0 TX_DUAL_BAND_ COMBINER_PAP_ HPF_AVERAGING _SAMPLE_COUNT R W 0h The high pass filter output can be averaged in a programmable window of 2 to 16 sam...

Page 669: ...NER _PAP_PWR_M ETER_CAPTU RE R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1331 Register 51D Field Descriptions Bit Field Type Reset Description 0 0 TX_DUAL_BAND_ COMBINER_PAP_ PWR_METER_CA PTURE R W 0h Dynamic power calculation capture signal for the power meter at dual band combiner 0 1 0 transition captures power estimation data 2 12 117 Register 51Eh offset 51Eh reset 0...

Page 670: ...set Table 2 1334 Register 521 Field Descriptions Bit Field Type Reset Description 3 0 TX_DUAL_BAND_ COMBINER_PAP_ PWR_METER_WI NDOW_COUNTER 11 8 R W 0h Dual band power meter accumulation window counter Window length of 2 n are only supported and the value to be programmed for 2 n window length 2 n 5 1 2 12 120 Register 524h offset 524h reset 0h Figure 2 1323 Register 524h 7 6 5 4 3 2 1 0 TX_DUAL_B...

Page 671: ...AND_DUAL_BAN D_DISABLE R W 0h Disable PA protection for one of the bands when PAP detectors are in run in dual band mode 0 Enable both bands 1 Disable band0 only 2 Disable band1 only 3 Disable both bands 2 12 123 Register 528h offset 528h reset 0h Figure 2 1326 Register 528h 7 6 5 4 3 2 1 0 TX_PAP_MAS TER_EN R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1338 Register 528 Fi...

Page 672: ...scription 6 0 TX_PAP_ALARM_ MASK R W 7Eh Mask PAP final alarm to GPIO Value 1 Mask Value 0 NoMask bit 0 TxA Alarm bit 1 TxB Alarm bit 2 TxC Alarm bit 3 TxD Alarm bit 4 Reserved bit 5 Reserved bit 6 Reserved 2 12 126 Register 530h offset 530h reset 0h Figure 2 1329 Register 530h 7 6 5 4 3 2 1 0 TX_PAP_ALAR M_TRIGGER_ A R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1341 Regis...

Page 673: ...allowed values is 0 to 128 In the cosine mode value of 0 will get converted to amplitude of 127 128 in the ramp down and value of 128 will map to amplitude of 0 2 12 129 Register 534h offset 534h reset 80h Figure 2 1332 Register 534h 7 6 5 4 3 2 1 0 TX_PAP_ATTENUATION_START_LIN R W 80h LEGEND R W Read Write W Write only n value after reset Table 2 1344 Register 534 Field Descriptions Bit Field Typ...

Page 674: ...Write only n value after reset Table 2 1347 Register 539 Field Descriptions Bit Field Type Reset Description 3 0 TX_PAP_CHAIN_D ELAY_RAMP_DO WN 11 8 R W 0h Tx Chain latency before ramp down starts from PAP trigger to the PAP state machine The latency is measured in terms of clock frequency of FDAC 16 2 12 133 Register 53Ah offset 53Ah reset 0h Figure 2 1336 Register 53Ah 7 6 5 4 3 2 1 0 TX_PAP_CHA...

Page 675: ...ring PAP cosine ramp up mode Ranges of allowed values is 0 to 128 In the cosine mode value of 0 will get converted to amplitude of 127 128 in the ramp up and value of 128 will map to amplitude of 0 2 12 136 Register 53Eh offset 53Eh reset 0h Figure 2 1339 Register 53Eh 7 6 5 4 3 2 1 0 TX_PAP_GAIN_START_LIN R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1351 Register 53E Fiel...

Page 676: ...t 0h Figure 2 1342 Register 544h 7 6 5 4 3 2 1 0 TX_PAP_WAIT_COUNTER 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1354 Register 544 Field Descriptions Bit Field Type Reset Description 7 0 TX_PAP_WAIT_C OUNTER 7 0 R W 0h Wait counter window length Range is from 1 to 2 16 1 The counter is operating at frequency FDAC 16 2 12 140 Register 545h offset 545h reset 0h Figure 2...

Page 677: ...6 Async FIFO Overflow Alarm bit 7 Saturation Overflow Alarm bit 8 Dual Single band Alarm bit 9 PAP dual band combiner alarm bit 10 FW SPI triggered alarm Remaining Unused 2 12 143 Register 54Dh offset 54Dh reset 0h Figure 2 1346 Register 54Dh 7 6 5 4 3 2 1 0 TX_PAP_OTHER_TX_PAP_ALARM_CLR 10 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1358 Register 54D Field Descriptions...

Page 678: ...d Write W Write only n value after reset Table 2 1360 Register 54F Field Descriptions Bit Field Type Reset Description 2 0 TX_PAP_OTHER_ TX_PAP_ALARM_ MASK 10 8 R W 6h Mask PAP TxA input detection alarms Value 1 Mask Value 0 NoMask bit 0 PLL Alarm bit 5 JESD Serdes Alarm bit 6 Async FIFO Overflow Alarm bit 7 Saturation Overflow Alarm bit 8 Dual Single band Alarm bit 9 PAP dual band combiner alarm ...

Page 679: ...GE_WINDOW_COUNTER 11 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1363 Register 555 Field Descriptions Bit Field Type Reset Description 3 0 TX_PAP_OVER_R ANGE_WINDOW_ COUNTER 11 8 R W 0h Saturation window counter value Allowed values from 0 to 2 12 1 2 12 149 Register 556h offset 556h reset 0h Figure 2 1352 Register 556h 7 6 5 4 3 2 1 0 TX_PAP_OVER_RANGE_ERROR_THRESHOLD ...

Page 680: ..._ STATUS R 0h Masked Alarm status bits of PAP final alarm to GPIO Value 1 Triggered Value 0 NoTrigger bit 0 TxA Alarm bit 1 TxB Alarm bit 2 TxC Alarm bit 3 TxD Alarm bit 4 Reserved 2 12 152 Register 559h offset 559h reset 0h Figure 2 1355 Register 559h 7 6 5 4 3 2 1 0 TX_PAP_UNMASK_STATUS R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1367 Register 559 Field Descriptions Bit F...

Page 681: ...ptions Bit Field Type Reset Description 2 0 TX_PAP_OTHER_ TX_PAP_ALARM_ STATUS 10 8 R 0h Masked Alarm status bits of PAP TxA input detection alarms Value 1 Trigger Value 0 NoTrigger bit 0 PLL Alarm bit 5 JESD Serdes Alarm bit 6 Async FIFO Overflow Alarm bit 7 Saturation Overflow Alarm bit 8 Dual Single band Alarm bit 9 PAP dual band combiner alarm bit 10 FW SPI triggered alarm Remaining Unused 2 1...

Page 682: ...t 0 PLL Alarm bit 5 JESD Serdes Alarm bit 6 Async FIFO Overflow Alarm bit 7 Saturation Overflow Alarm bit 8 Dual Single band Alarm bit 9 PAP dual band combiner alarm bit 10 FW SPI triggered alarm Remaining Unused 2 12 157 Register 560h offset 560h reset 0h Figure 2 1360 Register 560h 7 6 5 4 3 2 1 0 TX_IP_PAP_M ODE_MOVING _AVERAGE_E N R W 0h LEGEND R W Read Write W Write only n value after reset T...

Page 683: ...fter reset Table 2 1374 Register 562 Field Descriptions Bit Field Type Reset Description 7 0 TX_IP_PAP_MOVI NG_AVERAGE_WI NDOW_COUNTER 7 0 R W 0h Interface rate PAP Moving average window counter value 0 to 2 12 1 2 12 160 Register 563h offset 563h reset 0h Figure 2 1363 Register 563h 7 6 5 4 3 2 1 0 TX_IP_PAP_MOVING_AVERAGE_WINDOW_COUNTER 11 8 R W 0h LEGEND R W Read Write W Write only n value afte...

Page 684: ...r reset Table 2 1377 Register 565 Field Descriptions Bit Field Type Reset Description 3 0 TX_IP_PAP_MOVI NG_AVERAGE_E RROR_THRESHO LD 11 8 R W 0h Interface rate PAP moving average error counter value 0 to 2 12 1 2 12 163 Register 568h offset 568h reset 0h Figure 2 1366 Register 568h 7 6 5 4 3 2 1 0 TX_IP_PAP_M ODE_HPF_EN R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1378 Re...

Page 685: ...er 56A Field Descriptions Bit Field Type Reset Description 1 0 TX_IP_PAP_HPF_ SAMPLES R W 0h The high pass filter output can be averaged in a programmable window of 2 to 16 samples The averaged output is compared against a threshold to determine the error hit 0 2 1 4 2 8 3 16 However the averaging can be bypassed and the instantaneous filter output is compared against the threshold If the register...

Page 686: ...AP_POWER_BIAS R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1383 Register 56E Field Descriptions Bit Field Type Reset Description 7 0 TX_IP_PAP_POW ER_BIAS R W 0h Unused 2 12 169 Register 570h offset 570h reset 0h Figure 2 1372 Register 570h 7 6 5 4 3 2 1 0 TX_IP_PAP_MOVING_AVERAGE_PWR_COUNTER 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1384 Re...

Page 687: ...e moving average count threshold can be programmed in the range 0 to 2 12 1 The error accumulation counter is programmable with value in the range 1 to 2 12 1 The error threshold is programmed in the register tx_pap_hpf_error_threshold 2 12 172 Register 575h offset 575h reset 0h Figure 2 1375 Register 575h 7 6 5 4 3 2 1 0 TX_PAP_DUAL_BAND_COMBINER_HPF_WINDOW_COUNTER 11 8 R W 0h LEGEND R W Read Wri...

Page 688: ...it Field Type Reset Description 3 0 TX_PAP_HPF_ER ROR_THRESHOL D 11 8 R W 0h In the Dual band combiner PA Protection high pass filter module when the high pass filter output average exceeds a thershold error hit is generated The PA protection can be triggered when the number of such hits in a programmable window exceeds the count threshold The moving average count threshold can be programmed in th...

Page 689: ...gister 57Ch offset 57Ch reset 0h Figure 2 1380 Register 57Ch 7 6 5 4 3 2 1 0 TX_IP_PAP_HPF_WINDOW_COUNTER 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1392 Register 57C Field Descriptions Bit Field Type Reset Description 7 0 TX_IP_PAP_HPF_ WINDOW_COUNT ER 7 0 R W 0h In the interface rate or Tx input IP PA Protection high pass filter module when the high pass filter out...

Page 690: ... rate or Tx input IP PA Protection high pass filter module when the high pass filter output average exceeds a thershold error hit is generated The PA protection can be triggered when the number of such hits in a programmable window exceeds the count threshold The moving average count threshold can be programmed in the range 0 to 2 12 1 The error accumulation counter is programmable with value in t...

Page 691: ...R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1397 Register 581 Field Descriptions Bit Field Type Reset Description 2 0 TX_PAP_DUAL_B AND_COMBINER_ DET_ALARM_MAS K R W 0h Dual band combiner PAP detection alarm Mask Value 1 mask 0 nomask bit 0 Moving average mode bit 1 High Pass Filter mode bit 2 Reserved 2 12 183 Register 582h offset 582h reset 0h Figure 2 1386 Register 582...

Page 692: ...Enable averaging 1 Disable moving average 2 12 184 Register 584h offset 584h reset 0h Figure 2 1387 Register 584h 7 6 5 4 3 2 1 0 TX_PAP_DUAL_BAND_COMBINER_DET_ALAR M_STATUS R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1399 Register 584 Field Descriptions Bit Field Type Reset Description 2 0 TX_PAP_DUAL_B AND_COMBINER_ DET_ALARM_STA TUS R 0h Dual band combiner PAP detection ...

Page 693: ...gure 2 1390 Register 589h 7 6 5 4 3 2 1 0 TX_IP_PAP_DET_ALARM_CLR R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1402 Register 589 Field Descriptions Bit Field Type Reset Description 2 0 TX_IP_PAP_DET_ ALARM_CLR R W 0h TX JESD interface PAP detection alarm clear Value 1 clear 0 noclear bit 0 Moving average mode bit 1 High pass filter mode bit 2 Reserved 2 12 188 Register 58A...

Page 694: ...f averaging mode 0 Don t use FIFOs 1 Use FIFO storage 1 1 TX_IP_PAP_MA_U PDATE_SAMPLES R W 0h Input PAP moving average mode averaging samples update pulse A 0 1 0 transition will update the sample config 0 0 TX_IP_PAP_MA_M ODE_NO_AVG R W 0h In TX JESD interface or input IP PAP moving average detection mode control for enable and disable of averaging mode 0 Enable averaging 1 Disable averaging 2 12...

Page 695: ...ype Reset Description 0 0 TX_PAP_DYN_GPI O_ALARM R W 0h PAP alarm type for output to GPIO Dynamic or Static versions are available 0 static alarm output 1 dynamic alarm output 2 12 193 Register 596h offset 596h reset 1h Figure 2 1396 Register 596h 7 6 5 4 3 2 1 0 TX_PAP_DYN_OUT_PULSE_EXTENSION 7 0 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 1408 Register 596 Field Descrip...

Page 696: ... 7 0 R 0h Input PAP band0 power detection module average power output The linear scale value is interpreted as read_value 2 16 2 12 196 Register 5A1h offset 5A1h reset 0h Figure 2 1399 Register 5A1h 7 6 5 4 3 2 1 0 TX_IP_PAP_MA_PWR_AVG_BAND0 15 8 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1411 Register 5A1 Field Descriptions Bit Field Type Reset Description 7 0 TX_IP_PAP_M...

Page 697: ...W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1414 Register 5A5 Field Descriptions Bit Field Type Reset Description 0 0 TX_IP_PAP_MA_A CCU_TH_BAND0 8 R W 0h Input PAP band0 moving average accumulator threshold for the envelope of the signal sqrt I 2 Q 2 The linear value is interpreted as programmed_value 2 8 2 12 200 Register 5A8h offset 5A8h reset 0h Figure 2 1403 Register 5...

Page 698: ...iner PAP moving average detection output The linear value is interpreted as read_value 2 16 2 12 203 Register 5B0h offset 5B0h reset 0h Figure 2 1406 Register 5B0h 7 6 5 4 3 2 1 0 TX_IP_PAP_MA_PWR_AVG_BAND1 7 0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1418 Register 5B0 Field Descriptions Bit Field Type Reset Description 7 0 TX_IP_PAP_MA_P WR_AVG_BAND1 7 0 R 0h Input PAP ...

Page 699: ... 5B4h 7 6 5 4 3 2 1 0 TX_IP_PAP_MA_ACCU_TH_BAND1 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1421 Register 5B4 Field Descriptions Bit Field Type Reset Description 7 0 TX_IP_PAP_MA_A CCU_TH_BAND1 7 0 R W 0h Input PAP band1 moving average accumulator threshold for the envelope of the signal sqrt I 2 Q 2 The linear value is interpreted as programmed_value 2 8 2 12 207 Re...

Page 700: ...eld Type Reset Description 7 0 TX_IP_PAP_HPF_ ACCU_TH_BAND1 7 0 R W 0h Input PAP band1 high pass filter accumulator threshold The linear value is interpreted as programmed_value 2 8 2 12 209 Register 5B7h offset 5B7h reset 0h Figure 2 1412 Register 5B7h 7 6 5 4 3 2 1 0 TX_IP_PAP_H PF_ACCU_TH_ BAND1 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1424 Register 5B7 Field Desc...

Page 701: ...h RX_DDC_BAND0_NCO0_PHASE_OFFSET 15 8 E2h RX_DDC_BAND0_NCO1_PHASE_OFFSET 7 0 E3h RX_DDC_BAND0_NCO1_PHASE_OFFSET 15 8 100h RX_DDC_BAND0_NCO0_FMULT 7 0 101h RX_DDC_BAND0_NCO0_FMULT 15 8 102h RX_DDC_BAND0_NCO0_FMULT 21 16 104h RX_DDC_BAND0_NCO1_FMULT 7 0 105h RX_DDC_BAND0_NCO1_FMULT 15 8 106h RX_DDC_BAND0_NCO1_FMULT 21 16 140h RX_DDC_BAND0_NCO0_FRAC_FCW_NUM 7 0 141h RX_DDC_BAND0_NCO0_FRAC_FCW_NUM 15 ...

Page 702: ...BAND _PK_DET_EN RX_AGC_PWR_ DECAY_DET_E N RX_AGC_PWR_ ATTACK_DET_E N RX_AGC_SMAL L_STEP_DECAY _DET_EN RX_AGC_BIG_S TEP_DECAY_D ET_EN RX_AGC_SMAL L_STEP_ATTAC K_DET_EN RX_AGC_BIG_S TEP_ATTACK_D ET_EN 405h RX_AGC_LNA_ RF_ATTACK_D ET_EN 408h RX_AGC_BIG_STEP_ATTACK_STEP_SIZE 409h RX_AGC_SMALL_STEP_ATTACK_STEP_SIZE 40Ah RX_AGC_BIG_STEP_DECAY_STEP_SIZE 40Bh RX_AGC_SMALL_STEP_DECAY_STEP_SIZE 40Ch RX_AGC_...

Page 703: ... RX_AGC_SMALL_STEP_DECAY_NUM_HITS 23 16 460h RX_AGC_LNA_RF_DET_ATTACK_NUM_HITS 7 0 461h RX_AGC_LNA_RF_DET_ATTACK_NUM_HITS 15 8 462h RX_AGC_LNA_RF_DET_ATTACK_NUM_HITS 23 16 463h RX_AGC_LNA_RF_DET_ATTACK_NUM_HITS 27 24 470h RX_AGC_BAND0_DECAY_NUM_HITS 7 0 471h RX_AGC_BAND0_DECAY_NUM_HITS 15 8 472h RX_AGC_BAND0_DECAY_NUM_HITS 23 16 478h RX_AGC_BAND1_DECAY_NUM_HITS 7 0 479h RX_AGC_BAND1_DECAY_NUM_HITS...

Page 704: ...10 8 4BEh RX_AGC_BAND0_LNA_GAIN1 7 0 4BFh RX_AGC_BAND0_LNA_GAIN1 10 8 4C0h RX_AGC_BAND0_LNA_GAIN2 7 0 4C1h RX_AGC_BAND0_LNA_GAIN2 10 8 4C2h RX_AGC_BAND0_LNA_GAIN3 7 0 4C3h RX_AGC_BAND0_LNA_GAIN3 10 8 4C4h RX_AGC_BAND0_LNA_GAIN4 7 0 4C5h RX_AGC_BAND0_LNA_GAIN4 10 8 4C6h RX_AGC_BAND0_LNA_GAIN5 7 0 4C7h RX_AGC_BAND0_LNA_GAIN5 10 8 4C8h RX_AGC_BAND0_LNA_GAIN6 7 0 4C9h RX_AGC_BAND0_LNA_GAIN6 10 8 4CAh ...

Page 705: ...6h RX_AGC_BAND0_LNA_GAIN29 7 0 4F7h RX_AGC_BAND0_LNA_GAIN29 10 8 4F8h RX_AGC_BAND0_LNA_GAIN30 7 0 4F9h RX_AGC_BAND0_LNA_GAIN30 10 8 4FAh RX_AGC_BAND0_LNA_GAIN31 7 0 4FBh RX_AGC_BAND0_LNA_GAIN31 10 8 4FCh RX_AGC_BAND1_LNA_GAIN0 7 0 4FDh RX_AGC_BAND1_LNA_GAIN0 10 8 4FEh RX_AGC_BAND1_LNA_GAIN1 7 0 4FFh RX_AGC_BAND1_LNA_GAIN1 10 8 500h RX_AGC_BAND1_LNA_GAIN2 7 0 501h RX_AGC_BAND1_LNA_GAIN2 10 8 502h R...

Page 706: ...23 10 8 52Ch RX_AGC_BAND1_LNA_GAIN24 7 0 52Dh RX_AGC_BAND1_LNA_GAIN24 10 8 52Eh RX_AGC_BAND1_LNA_GAIN25 7 0 52Fh RX_AGC_BAND1_LNA_GAIN25 10 8 530h RX_AGC_BAND1_LNA_GAIN26 7 0 531h RX_AGC_BAND1_LNA_GAIN26 10 8 532h RX_AGC_BAND1_LNA_GAIN27 7 0 533h RX_AGC_BAND1_LNA_GAIN27 10 8 534h RX_AGC_BAND1_LNA_GAIN28 7 0 535h RX_AGC_BAND1_LNA_GAIN28 10 8 536h RX_AGC_BAND1_LNA_GAIN29 7 0 537h RX_AGC_BAND1_LNA_GA...

Page 707: ...5Bh RX_AGC_BAND0_LNA_PHASE15 9 8 55Ch RX_AGC_BAND0_LNA_PHASE16 7 0 55Dh RX_AGC_BAND0_LNA_PHASE16 9 8 55Eh RX_AGC_BAND0_LNA_PHASE17 7 0 55Fh RX_AGC_BAND0_LNA_PHASE17 9 8 560h RX_AGC_BAND0_LNA_PHASE18 7 0 561h RX_AGC_BAND0_LNA_PHASE18 9 8 562h RX_AGC_BAND0_LNA_PHASE19 7 0 563h RX_AGC_BAND0_LNA_PHASE19 9 8 564h RX_AGC_BAND0_LNA_PHASE20 7 0 565h RX_AGC_BAND0_LNA_PHASE20 9 8 566h RX_AGC_BAND0_LNA_PHASE...

Page 708: ...D1_LNA_PHASE4 9 8 586h RX_AGC_BAND1_LNA_PHASE5 7 0 587h RX_AGC_BAND1_LNA_PHASE5 9 8 588h RX_AGC_BAND1_LNA_PHASE6 7 0 589h RX_AGC_BAND1_LNA_PHASE6 9 8 58Ah RX_AGC_BAND1_LNA_PHASE7 7 0 58Bh RX_AGC_BAND1_LNA_PHASE7 9 8 58Ch RX_AGC_BAND1_LNA_PHASE8 7 0 58Dh RX_AGC_BAND1_LNA_PHASE8 9 8 58Eh RX_AGC_BAND1_LNA_PHASE9 7 0 58Fh RX_AGC_BAND1_LNA_PHASE9 9 8 590h RX_AGC_BAND1_LNA_PHASE10 7 0 591h RX_AGC_BAND1_...

Page 709: ...C_BAND1_LNA_PHASE25 9 8 5B0h RX_AGC_BAND1_LNA_PHASE26 7 0 5B1h RX_AGC_BAND1_LNA_PHASE26 9 8 5B2h RX_AGC_BAND1_LNA_PHASE27 7 0 5B3h RX_AGC_BAND1_LNA_PHASE27 9 8 5B4h RX_AGC_BAND1_LNA_PHASE28 7 0 5B5h RX_AGC_BAND1_LNA_PHASE28 9 8 5B6h RX_AGC_BAND1_LNA_PHASE29 7 0 5B7h RX_AGC_BAND1_LNA_PHASE29 9 8 5B8h RX_AGC_BAND1_LNA_PHASE30 7 0 5B9h RX_AGC_BAND1_LNA_PHASE30 9 8 5BAh RX_AGC_BAND1_LNA_PHASE31 7 0 5B...

Page 710: ...ONTROL 637h RX_ALC_USE_1 2BIT_SEL 638h RX_ALC_TOTAL_GAIN_RANGE 639h RX_ALC_SIG_BACKOFF_DB 63Ch RX_ALC_COARSE_STEP RX_ALC_NUM_BITS_COARSE_INDEX 63Dh RX_ALC_COAR SE_INDEX_SW AP_IQ RX_ALC_COAR SE_INDEX_INV ERT 63Eh RX_ALC_FINE_EXP_OFFSET RX_ALC_FINE_OFFSET 640h RX_ALC_OUTPUT_PIN_DELAY 7 0 641h RX_ALC_OUTPUT_PIN_DELAY 13 8 648h RX_ALC_MIN_ATTN_DSA 649h RX_ALC_USE_ MIN_ATTN_FRO M_AGC 64Ch RX_ALC_USE_L ...

Page 711: ...factor 10 06 decimation factor 20 07 decimation factor 40 08 decimation factor 12 10 decimation factor 24 11 decimation factor 48 16 decimation factor 4 32 decimation factor 2 5 48 decimation factor 5 64 decimation factor 3 80 decimation factor 6 2 13 2 Register 41h offset 41h reset 1h Figure 2 1414 Register 41h 7 6 5 4 3 2 1 0 RX_DDC_2X_S CALE_CONFG R W 1h LEGEND R W Read Write W Write only n val...

Page 712: ... factor is 8 in addition to rx_ddc_mode_config above 2 13 5 Register 44h offset 44h reset 0h Figure 2 1417 Register 44h 7 6 5 4 3 2 1 0 RX_DDC_REA L_MODE_CON FIG R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1430 Register 44 Field Descriptions Bit Field Type Reset Description 0 0 RX_DDC_REAL_M ODE_CONFIG R W 0h FB DDC real output mode enable 0 Complex I Q output mode defaul...

Page 713: ... R W Read Write W Write only n value after reset Table 2 1433 Register 4A Field Descriptions Bit Field Type Reset Description 2 0 RX_DDC_FIFO_C ONFIG2 R W 1h RX DDC FIFO Configuration2 Value dependent on decimation factor Optimal value automatically determined if System Configuration Macros are used 2 13 9 Register 4Eh offset 4Eh reset 6h Figure 2 1421 Register 4Eh 7 6 5 4 3 2 1 0 RX_DDC_MISC_DLY_...

Page 714: ...egister 70h offset 70h reset 1h Figure 2 1424 Register 70h 7 6 5 4 3 2 1 0 RX_DDC_NYQ_CONFIG R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 1437 Register 70 Field Descriptions Bit Field Type Reset Description 2 0 RX_DDC_NYQ_C ONFIG R W 1h ADC Nyquist zone select Valid range 1 through 6 1 Select Nyquist Zone 1 2 Select Nyquist Zone 2 3 Select Nyquist Zone 3 4 Select Nyquist Z...

Page 715: ... 23 16 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1440 Register A2 Field Descriptions Bit Field Type Reset Description 7 0 RX_DDC_BAND0_ NCO0_FCW 23 16 R W 0h Frequency control word FCW for nco0 of band0 The System Configuration Macros automatically configure this 2 13 16 Register A3h offset A3h reset 0h Figure 2 1428 Register A3h 7 6 5 4 3 2 1 0 RX_DDC_BAND0_NCO0_FCW 31...

Page 716: ...rol word FCW for nco1 of band0 The System Configuration Macros automatically configure this 2 13 19 Register A6h offset A6h reset 0h Figure 2 1431 Register A6h 7 6 5 4 3 2 1 0 RX_DDC_BAND0_NCO1_FCW 23 16 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1444 Register A6 Field Descriptions Bit Field Type Reset Description 7 0 RX_DDC_BAND0_ NCO1_FCW 23 16 R W 0h Frequency control...

Page 717: ...1 0 RX_DDC_BAND0_NCO0_PHASE_OFFSET 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1447 Register E1 Field Descriptions Bit Field Type Reset Description 7 0 RX_DDC_BAND0_ NCO0_PHASE_OF FSET 15 8 R W 0h Offset phase for nco0 of band0 2 13 23 Register E2h offset E2h reset 0h Figure 2 1435 Register E2h 7 6 5 4 3 2 1 0 RX_DDC_BAND0_NCO1_PHASE_OFFSET 7 0 R W 0h LEGEND R W Read...

Page 718: ...w of band0 and should be a value between Fadc 32 and Fadc 32 The System Configuration Macros automatically compute and configure this and are hence strongly recommended 2 13 26 Register 101h offset 101h reset 0h Figure 2 1438 Register 101h 7 6 5 4 3 2 1 0 RX_DDC_BAND0_NCO0_FMULT 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1451 Register 101 Field Descriptions Bit Fiel...

Page 719: ...orresponding to the fcw of nco1 of band0 expressed in kHz less the closest multiple of Fadc 16 Value programmed here should correspond to the nco1 fcw of band0 and should be a value between Fadc 32 and Fadc 32 The System Configuration Macros automatically compute and configure this and are hence strongly recommended 2 13 29 Register 105h offset 105h reset 0h Figure 2 1441 Register 105h 7 6 5 4 3 2...

Page 720: ...et Table 2 1456 Register 140 Field Descriptions Bit Field Type Reset Description 7 0 RX_DDC_BAND0_ NCO0_FRAC_FC W_NUM 7 0 R W 0h Numerator of the fractional fequency control word for nco0 of Band0 Signed number System Configuration macros compute and configure this automatically and hence are strongly recommended 2 13 32 Register 141h offset 141h reset 0h Figure 2 1444 Register 141h 7 6 5 4 3 2 1 ...

Page 721: ...nfiguration macros compute and configure this automatically and hence are strongly recommended 2 13 35 Register 144h offset 144h reset 0h Figure 2 1447 Register 144h 7 6 5 4 3 2 1 0 RX_DDC_BAND0_NCO1_FRAC_FCW_NUM 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1460 Register 144 Field Descriptions Bit Field Type Reset Description 7 0 RX_DDC_BAND0_ NCO1_FRAC_FC W_NUM 7 0 R ...

Page 722: ...D0_NCO1_FRAC_FCW_DEN 15 8 R W 2Dh LEGEND R W Read Write W Write only n value after reset Table 2 1463 Register 147 Field Descriptions Bit Field Type Reset Description 7 0 RX_DDC_BAND0_ NCO1_FRAC_FC W_DEN 15 8 R W 2Dh Denominator of the fractional fequency control word for nco1 of band0 Unsigned number System Configuration macros compute and configure this automatically and hence are strongly recom...

Page 723: ...15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1466 Register 1A1 Field Descriptions Bit Field Type Reset Description 7 0 RX_DDC_BAND1_ NCO0_FCW 15 8 R W 0h Frequency control word FCW for nco0 of band1 The System Configuration Macros automatically configure this 2 13 42 Register 1A2h offset 1A2h reset 0h Figure 2 1454 Register 1A2h 7 6 5 4 3 2 1 0 RX_DDC_BAND1_NCO0_FCW 2...

Page 724: ...ol word FCW for nco1 of band1 The System Configuration Macros automatically configure this 2 13 45 Register 1A5h offset 1A5h reset 0h Figure 2 1457 Register 1A5h 7 6 5 4 3 2 1 0 RX_DDC_BAND1_NCO1_FCW 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1470 Register 1A5 Field Descriptions Bit Field Type Reset Description 7 0 RX_DDC_BAND1_ NCO1_FCW 15 8 R W 0h Frequency contro...

Page 725: ...460 Register 1E0h 7 6 5 4 3 2 1 0 RX_DDC_BAND1_NCO0_PHASE_OFFSET 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1473 Register 1E0 Field Descriptions Bit Field Type Reset Description 7 0 RX_DDC_BAND1_ NCO0_PHASE_OF FSET 7 0 R W 0h Offset phase for nco0 of band1 2 13 49 Register 1E1h offset 1E1h reset 0h Figure 2 1461 Register 1E1h 7 6 5 4 3 2 1 0 RX_DDC_BAND1_NCO0_PHASE_O...

Page 726: ...et phase for nco1 of band1 2 13 52 Register 200h offset 200h reset 0h Figure 2 1464 Register 200h 7 6 5 4 3 2 1 0 RX_DDC_BAND1_NCO0_FMULT 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1477 Register 200 Field Descriptions Bit Field Type Reset Description 7 0 RX_DDC_BAND1_ NCO0_FMULT 7 0 R W 0h Frequency shift corresponding to the fcw of nco0 of band1 expressed in kHz les...

Page 727: ...t corresponding to the fcw of nco0 of band1 expressed in kHz less the closest multiple of Fadc 16 Value programmed here should correspond to the nco0 fcw of band1 and should be a value between Fadc 32 and Fadc 32 The System Configuration Macros automatically compute and configure this and are hence strongly recommended 2 13 55 Register 204h offset 204h reset 0h Figure 2 1467 Register 204h 7 6 5 4 ...

Page 728: ...er 206 Field Descriptions Bit Field Type Reset Description 5 0 RX_DDC_BAND1_ NCO1_FMULT 21 16 R W 0h Frequency shift corresponding to the fcw of nco1 of band1 expressed in kHz less the closest multiple of Fadc 16 Value programmed here should correspond to the nco1 fcw of band1 and should be a value between Fadc 32 and Fadc 32 The System Configuration Macros automatically compute and configure this...

Page 729: ...ion macros compute and configure this automatically and hence are strongly recommended 2 13 61 Register 243h offset 243h reset 2Dh Figure 2 1473 Register 243h 7 6 5 4 3 2 1 0 RX_DDC_BAND1_NCO0_FRAC_FCW_DEN 15 8 R W 2Dh LEGEND R W Read Write W Write only n value after reset Table 2 1486 Register 243 Field Descriptions Bit Field Type Reset Description 7 0 RX_DDC_BAND1_ NCO0_FRAC_FC W_DEN 15 8 R W 2D...

Page 730: ...6 5 4 3 2 1 0 RX_DDC_BAND1_NCO1_FRAC_FCW_DEN 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1489 Register 246 Field Descriptions Bit Field Type Reset Description 7 0 RX_DDC_BAND1_ NCO1_FRAC_FC W_DEN 7 0 R W 0h Denominator of the fractional fequency control word for nco1 of band1 Unsigned number System Configuration macros compute and configure this automatically and henc...

Page 731: ...K _EN R W 0h R W 0h R W 0h R W 0h R W 1h R W 0h R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1492 Register 400 Field Descriptions Bit Field Type Reset Description 7 7 RX_AGC_DIG_BA ND1_DET_EN R W 0h Use Digital Band detector 1 for AGC control loop Will be effective only in case Dual Band AGC feature is enabled 0 Disable 1 Enable 6 6 RX_AGC_DIG_BA ND0_DET_EN R W 0h U...

Page 732: ...4 3 2 1 0 RX_AGC_EXT _DVGA_CNTR L_EN RX_AGC_EXT _LNA_CNTL_E N R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1494 Register 402 Field Descriptions Bit Field Type Reset Description 1 1 RX_AGC_EXT_DV GA_CNTRL_EN R W 0h Indicates whether AGC can control External DVGA or not At any point of time only either LNA or External DVGA can be enabled see rx_agc_ext_lna_cntrl_en ab...

Page 733: ...LL_ STEP_ATTACK_D ET_EN R W 1h Small step attack detector enable 0 Disable 1 Enable 0 0 RX_AGC_BIG_ST EP_ATTACK_DET _EN R W 0h Big step attack detector enable 0 Disable 1 Enable 2 13 71 Register 405h offset 405h reset 0h Figure 2 1483 Register 405h 7 6 5 4 3 2 1 0 RX_AGC_LNA _RF_ATTACK_ DET_EN R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1496 Register 405 Field Description...

Page 734: ...C_BIG_STEP_DECAY_STEP_SIZE R W 6h LEGEND R W Read Write W Write only n value after reset Table 2 1499 Register 40A Field Descriptions Bit Field Type Reset Description 5 0 RX_AGC_BIG_ST EP_DECAY_STEP _SIZE R W 6h Gain step when Digital big step decay is triggered 0 5 dB step size 2 13 75 Register 40Bh offset 40Bh reset 2h Figure 2 1487 Register 40Bh 7 6 5 4 3 2 1 0 RX_AGC_SMALL_STEP_DECAY_STEP_SIZE...

Page 735: ..._STEP_SIZE R W 2h Gain step when Digital power detector decay is triggered 0 5 dB step size 2 13 78 Register 410h offset 410h reset Ch Figure 2 1490 Register 410h 7 6 5 4 3 2 1 0 RX_AGC_LNARF_ATTACK_STEP_SIZE R W Ch LEGEND R W Read Write W Write only n value after reset Table 2 1503 Register 410 Field Descriptions Bit Field Type Reset Description 5 0 RX_AGC_LNARF_ ATTACK_STEP_SI ZE R W Ch Gain ste...

Page 736: ..._WIN_LEN 23 16 R W 40h LEGEND R W Read Write W Write only n value after reset Table 2 1506 Register 416 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BIG_ST EP_ATTACK_WIN _LEN 23 16 R W 40h Digital big step attack det window length Max supported length is 2 24 2 2 13 82 Register 418h offset 418h reset 0h Figure 2 1494 Register 418h 7 6 5 4 3 2 1 0 RX_AGC_SMALL_STEP_ATTACK_WIN_LEN ...

Page 737: ...W IN_LEN 23 16 R W 40h Digital small step attack det window length Max supported length is 2 24 2 2 13 85 Register 41Ch offset 41Ch reset 0h Figure 2 1497 Register 41Ch 7 6 5 4 3 2 1 0 RX_AGC_BIG_STEP_DECAY_WIN_LEN 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1510 Register 41C Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BIG_ST EP_DECAY_WIN_ LEN 7 0 R...

Page 738: ...Y_WIN_LEN 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1513 Register 420 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_SMALL_ STEP_DECAY_WI N_LEN 7 0 R W 0h Digital small step decay det window length Max supported length is 2 24 2 2 13 89 Register 421h offset 421h reset 80h Figure 2 1501 Register 421h 7 6 5 4 3 2 1 0 RX_AGC_SMALL_STEP_DECAY_WIN_LEN 15 ...

Page 739: ...window length used is 2 power programmed value Max supported length is 2 23 programmed value 23 2 13 92 Register 425h offset 425h reset Fh Figure 2 1504 Register 425h 7 6 5 4 3 2 1 0 RX_AGC_PWRDET_DECAY_WIN_LEN R W Fh LEGEND R W Read Write W Write only n value after reset Table 2 1517 Register 425 Field Descriptions Bit Field Type Reset Description 4 0 RX_AGC_PWRDE T_DECAY_WIN_L EN R W Fh Power de...

Page 740: ...TACK_WIN_LEN 23 16 R W 40h LEGEND R W Read Write W Write only n value after reset Table 2 1520 Register 42A Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_LNA_RF _DET_ATTACK_W IN_LEN 23 16 R W 40h LNA RF attack det window length Max supported length is 2 24 2 2 13 96 Register 42Ch offset 42Ch reset FAh Figure 2 1508 Register 42Ch 7 6 5 4 3 2 1 0 RX_AGC_BIG_STEP_ATTACK_SIG_TH 7 0 R ...

Page 741: ...0 R W CBh Signal threshold for digital small step attack detector in 0 12 unsigned format 2 13 99 Register 431h offset 431h reset 6h Figure 2 1511 Register 431h 7 6 5 4 3 2 1 0 RX_AGC_SMALL_STEP_ATTACK_SIG_TH 11 8 R W 6h LEGEND R W Read Write W Write only n value after reset Table 2 1524 Register 431 Field Descriptions Bit Field Type Reset Description 3 0 RX_AGC_SMALL_ STEP_ATTACK_SI G_TH 11 8 R W...

Page 742: ...CAY_SIG_TH 7 0 R W 65h LEGEND R W Read Write W Write only n value after reset Table 2 1527 Register 438 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_SMALL_ STEP_DECAY_SI G_TH 7 0 R W 65h Signal threshold for digital small step decay detector in 0 12 unsigned format 2 13 103 Register 439h offset 439h reset Fh Figure 2 1515 Register 439h 7 6 5 4 3 2 1 0 RX_AGC_SMALL_STEP_DECAY_SIG_...

Page 743: ...at Power threshold in dB will be 10 log Th 2 16 A full scale sine wave corresponds to 3 dB power 2 13 106 Register 43Eh offset 43Eh reset 4h Figure 2 1518 Register 43Eh 7 6 5 4 3 2 1 0 RX_AGC_PWR_DET_DECAY_TH 7 0 R W 4h LEGEND R W Read Write W Write only n value after reset Table 2 1531 Register 43E Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_PWR_D ET_DECAY_TH 7 0 R W 4h Thresho...

Page 744: ...ATTACK_NUM_HITS 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1534 Register 451 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BIG_ST EP_ATTACK_NUM _HITS 15 8 R W 0h Number of Hits threshold for digital big step attack detector 2 13 110 Register 452h offset 452h reset 8h Figure 2 1522 Register 452h 7 6 5 4 3 2 1 0 RX_AGC_BIG_STEP_ATTACK_NUM_HITS 23 16 R...

Page 745: ...ACK_N UM_HITS 15 8 R W 0h Number of Hits threshold for digital small step attack detector 2 13 113 Register 456h offset 456h reset 8h Figure 2 1525 Register 456h 7 6 5 4 3 2 1 0 RX_AGC_SMALL_STEP_ATTACK_NUM_HITS 23 16 R W 8h LEGEND R W Read Write W Write only n value after reset Table 2 1538 Register 456 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_SMALL_ STEP_ATTACK_N UM_HITS 23...

Page 746: ..._DECAY_NUM_HITS 23 16 R W 8h LEGEND R W Read Write W Write only n value after reset Table 2 1541 Register 45A Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BIG_ST EP_DECAY_NUM_ HITS 23 16 R W 8h Number of Hits threshold for digital big step decay detector 2 13 117 Register 45Ch offset 45Ch reset 0h Figure 2 1529 Register 45Ch 7 6 5 4 3 2 1 0 RX_AGC_SMALL_STEP_DECAY_NUM_HITS 7 0 R ...

Page 747: ...p decay detector 2 13 120 Register 460h offset 460h reset 0h Figure 2 1532 Register 460h 7 6 5 4 3 2 1 0 RX_AGC_LNA_RF_DET_ATTACK_NUM_HITS 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1545 Register 460 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_LNA_RF _DET_ATTACK_N UM_HITS 7 0 R W 0h LNA RF attack det threshold If Number of hits is greater than this...

Page 748: ..._LNA_RF_DET_ATTACK_NUM_HITS 27 24 R W 8h LEGEND R W Read Write W Write only n value after reset Table 2 1548 Register 463 Field Descriptions Bit Field Type Reset Description 3 0 RX_AGC_LNA_RF _DET_ATTACK_N UM_HITS 27 24 R W 8h LNA RF attack det threshold If Number of hits is greater than this detector is triggered Note that per clock we may get up to 8 hits 2 13 124 Register 470h offset 470h reset...

Page 749: ...DECAY_NUM_HIT S 23 16 R W 8h Number of Hits threshold digital band0 detector in decay mode 2 13 127 Register 478h offset 478h reset 0h Figure 2 1539 Register 478h 7 6 5 4 3 2 1 0 RX_AGC_BAND1_DECAY_NUM_HITS 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1552 Register 478 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ DECAY_NUM_HIT S 7 0 R W 0h Numb...

Page 750: ...55 Register 484 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND0_ PEAK_DET_DECA Y_WIN_LEN 7 0 R W 0h Band0 peak detector window length in decay mode When decay detectors are in sync mode this window length is used by all decay detectors Max supported length is 2 24 2 Window length is defined in terms of band detector tap off point clock rate 2 13 131 Register 485h offset 485h r...

Page 751: ... 5 4 3 2 1 0 RX_AGC_BAND0_PWR_DET_DECAY_WIN_LEN R W Fh LEGEND R W Read Write W Write only n value after reset Table 2 1558 Register 489 Field Descriptions Bit Field Type Reset Description 4 0 RX_AGC_BAND0_ PWR_DET_DECA Y_WIN_LEN R W Fh Power detector decay window length for Band 0 Actual window length used is 2 power programmed value Supported length is only upto 2 23 Window length is defined in t...

Page 752: ... this to reflect 2 13 136 Register 491h offset 491h reset Bh Figure 2 1548 Register 491h 7 6 5 4 3 2 1 0 RX_AGC_BAND1_PKDET_DB_DECAY_THR R W Bh LEGEND R W Read Write W Write only n value after reset Table 2 1561 Register 491 Field Descriptions Bit Field Type Reset Description 5 0 RX_AGC_BAND1_ PKDET_DB_DECA Y_THR R W Bh LNA re enable threshold in dB for Band1 Negative value will be used Please not...

Page 753: ... external DSA Gain has changed 0 Internal AGC Mode 1 External AGC Mode 0 0 RX_AGC_INTERN AL_EN R W 0h Internal AGC control loop enable 0 Use Default attn 1 Internal AGC enabled 2 13 139 Register 499h offset 499h reset 0h Figure 2 1551 Register 499h 7 6 5 4 3 2 1 0 RX_AGC_FRE EZE_PIN_EN R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1564 Register 499 Field Descriptions Bit Fi...

Page 754: ...gister 49Dh offset 49Dh reset 0h Figure 2 1554 Register 49Dh 7 6 5 4 3 2 1 0 RX_AGC_DEF _LNA_BYP_VA L_B0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1567 Register 49D Field Descriptions Bit Field Type Reset Description 0 0 RX_AGC_DEF_LN A_BYP_VAL_B0 R W 0h Default LNA bypass value for Band 0 0 LNA enabled 1 LNA bypassed 2 13 143 Register 49Eh offset 49Eh reset 0h Figure 2...

Page 755: ...h reset 32h Figure 2 1557 Register 4A0h 7 6 5 4 3 2 1 0 RX_AGC_MAX_ATTN R W 32h LEGEND R W Read Write W Write only n value after reset Table 2 1570 Register 4A0 Field Descriptions Bit Field Type Reset Description 5 0 RX_AGC_MAX_AT TN R W 32h Max attenuation DSA can go to Resolution is 0 5 dB 2 13 146 Register 4A1h offset 4A1h reset 0h Figure 2 1558 Register 4A1h 7 6 5 4 3 2 1 0 RX_AGC_MIN_ATTN R W...

Page 756: ...GC_RES ET_LOOP_AT_ SIG_INVALID RX_AGC_DEC AY_DETS_RE SET_AT_RX_O N RX_AGC_ATT ACK_DETS_R ESET_AT_RX_ ON R W 0h R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1574 Register 4A4 Field Descriptions Bit Field Type Reset Description 2 2 RX_AGC_RESET_ LOOP_AT_SIG_IN VALID R W 0h Bit to control if during RX OFF and Gain Swap whether to reset the loop start the DSA with defau...

Page 757: ...ent Gain Changes this blanking time is used for all the detectors 2 13 152 Register 4A9h offset 4A9h reset 58h Figure 2 1564 Register 4A9h 7 6 5 4 3 2 1 0 RX_AGC_BLANK_TIME_FOR_EXT_COMP_CHANGE 15 8 R W 58h LEGEND R W Read Write W Write only n value after reset Table 2 1577 Register 4A9 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BLANK_ TIME_FOR_EXT_ COMP_CHANGE 1 5 8 R W 58h Whe...

Page 758: ...Dig pwr attack Bit 2 Dig pwr decay Bit 1 Absolute reliability Bit 0 Relative reliability 2 13 155 Register 4ADh offset 4ADh reset 40h Figure 2 1567 Register 4ADh 7 6 5 4 3 2 1 0 RX_AGC_PIN_1_SELECT_BITS 15 8 R W 40h LEGEND R W Read Write W Write only n value after reset Table 2 1580 Register 4AD Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_PIN_1_S ELECT_BITS 15 8 R W 40h Each bit...

Page 759: ...ion 7 0 RX_AGC_PIN_2_S ELECT_BITS 15 8 R W 30h Each bit corresponds to one particular detector which should be used for peak detector 2 Bit 14 Dig OVR Bit 13 Reserved Bit 12 Reserved Bit 11 LNARF det Bit 10 Reserved Bit 9 Reserved Bit 8 reserved Bit 7 Dig bigstep attack Bit 6 Dig small step attack Bit 5 Bigstep decay Bit 4 Small step decay Bit 3 Dig pwr attack Bit 2 Dig pwr decay Bit 1 Absolute re...

Page 760: ...3 Dig pwr attack Bit 2 Dig pwr decay Bit 1 Absolute reliability Bit 0 Relative reliability 2 13 160 Register 4B2h offset 4B2h reset 40h Figure 2 1572 Register 4B2h 7 6 5 4 3 2 1 0 RX_AGC_PIN_4_SELECT_BITS 7 0 R W 40h LEGEND R W Read Write W Write only n value after reset Table 2 1585 Register 4B2 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_PIN_4_S ELECT_BITS 7 0 R W 40h Each bit...

Page 761: ...ons Bit Field Type Reset Description 7 0 RX_AGC_GAIN_C HG_PULSE_EXPN _COUNT 7 0 R W 2h Number of clock cycles in terms of Fs 8 by which a high one should be extended before being sent on the pins for gain change indication pin 2 13 163 Register 4B5h offset 4B5h reset 0h Figure 2 1575 Register 4B5h 7 6 5 4 3 2 1 0 RX_AGC_GAIN_CHG_PULSE_EXPN_COUNT 11 8 R W 0h LEGEND R W Read Write W Write only n val...

Page 762: ...r 4B8h offset 4B8h reset 0h Figure 2 1578 Register 4B8h 7 6 5 4 3 2 1 0 RX_AGC_BAND0_TEMP_IDX R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1591 Register 4B8 Field Descriptions Bit Field Type Reset Description 4 0 RX_AGC_BAND0_ TEMP_IDX R W 0h Temperature index for Band 0 LNA 2 13 167 Register 4B9h offset 4B9h reset 0h Figure 2 1579 Register 4B9h 7 6 5 4 3 2 1 0 RX_AGC_BAND...

Page 763: ...ex 0 in case of External LNA Control Gain for DVGA Index 0 in case of External DVGA control It is in 6 5 resolution in dB which means 1dB corresponds to 32 Max value in dB should be lower than internal DSA Range 2 13 170 Register 4BEh offset 4BEh reset 0h Figure 2 1582 Register 4BEh 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_GAIN1 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 159...

Page 764: ...W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1598 Register 4C1 Field Descriptions Bit Field Type Reset Description 2 0 RX_AGC_BAND0_ LNA_GAIN2 10 8 R W 0h LNA Gain for Band0 for temp index 2 in case of External LNA Control Gain for DVGA Index 2 in case of External DVGA control 2 13 174 Register 4C2h offset 4C2h reset 0h Figure 2 1586 Register 4C2h 7 6 5 4 3 2 1 0 RX_AGC_BAND...

Page 765: ...ex 4 in case of External LNA Control Gain for DVGA Index 4 in case of External DVGA control 2 13 177 Register 4C5h offset 4C5h reset 0h Figure 2 1589 Register 4C5h 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_GAIN4 10 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1602 Register 4C5 Field Descriptions Bit Field Type Reset Description 2 0 RX_AGC_BAND0_ LNA_GAIN4 10 8 R W 0h LNA Gain for...

Page 766: ... W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1605 Register 4C8 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND0_ LNA_GAIN6 7 0 R W 0h LNA Gain for Band0 for temp index 6 in case of External LNA Control Gain for DVGA Index 6 in case of External DVGA control 2 13 181 Register 4C9h offset 4C9h reset 0h Figure 2 1593 Register 4C9h 7 6 5 4 3 2 1 0 RX_AGC_BAND...

Page 767: ...ex 7 in case of External LNA Control Gain for DVGA Index 7 in case of External DVGA control 2 13 184 Register 4CCh offset 4CCh reset 0h Figure 2 1596 Register 4CCh 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_GAIN8 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1609 Register 4CC Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND0_ LNA_GAIN8 7 0 R W 0h LNA Gain for B...

Page 768: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 1612 Register 4CF Field Descriptions Bit Field Type Reset Description 2 0 RX_AGC_BAND0_ LNA_GAIN9 10 8 R W 0h LNA Gain for Band0 for temp index 9 in case of External LNA Control Gain for DVGA Index 9 in case of External DVGA control 2 13 188 Register 4D0h offset 4D0h reset 0h Figure 2 1600 Register 4D0h 7 6 5 4 3 2 1 0 RX_AGC_BAND0_...

Page 769: ...11 in case of External LNA Control Gain for DVGA Index 11 in case of External DVGA control 2 13 191 Register 4D3h offset 4D3h reset 0h Figure 2 1603 Register 4D3h 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_GAIN11 10 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1616 Register 4D3 Field Descriptions Bit Field Type Reset Description 2 0 RX_AGC_BAND0_ LNA_GAIN11 10 8 R W 0h LNA Gain fo...

Page 770: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1619 Register 4D6 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND0_ LNA_GAIN13 7 0 R W 0h LNA Gain for Band0 for temp index 13 in case of External LNA Control Gain for DVGA Index 13 in case of External DVGA control 2 13 195 Register 4D7h offset 4D7h reset 0h Figure 2 1607 Register 4D7h 7 6 5 4 3 2 1 0 RX_AGC_BAN...

Page 771: ... 14 in case of External LNA Control Gain for DVGA Index 14 in case of External DVGA control 2 13 198 Register 4DAh offset 4DAh reset 0h Figure 2 1610 Register 4DAh 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_GAIN15 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1623 Register 4DA Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND0_ LNA_GAIN15 7 0 R W 0h LNA Gain for...

Page 772: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1626 Register 4DD Field Descriptions Bit Field Type Reset Description 2 0 RX_AGC_BAND0_ LNA_GAIN16 10 8 R W 0h LNA Gain for Band0 for temp index 16 in case of External LNA Control Gain for DVGA Index 16 in case of External DVGA control 2 13 202 Register 4DEh offset 4DEh reset 0h Figure 2 1614 Register 4DEh 7 6 5 4 3 2 1 0 RX_AGC_BA...

Page 773: ...18 in case of External LNA Control Gain for DVGA Index 18 in case of External DVGA control 2 13 205 Register 4E1h offset 4E1h reset 0h Figure 2 1617 Register 4E1h 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_GAIN18 10 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1630 Register 4E1 Field Descriptions Bit Field Type Reset Description 2 0 RX_AGC_BAND0_ LNA_GAIN18 10 8 R W 0h LNA Gain fo...

Page 774: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1633 Register 4E4 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND0_ LNA_GAIN20 7 0 R W 0h LNA Gain for Band0 for temp index 20 in case of External LNA Control Gain for DVGA Index 20 in case of External DVGA control 2 13 209 Register 4E5h offset 4E5h reset 0h Figure 2 1621 Register 4E5h 7 6 5 4 3 2 1 0 RX_AGC_BAN...

Page 775: ... 21 in case of External LNA Control Gain for DVGA Index 21 in case of External DVGA control 2 13 212 Register 4E8h offset 4E8h reset 0h Figure 2 1624 Register 4E8h 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_GAIN22 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1637 Register 4E8 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND0_ LNA_GAIN22 7 0 R W 0h LNA Gain for...

Page 776: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1640 Register 4EB Field Descriptions Bit Field Type Reset Description 2 0 RX_AGC_BAND0_ LNA_GAIN23 10 8 R W 0h LNA Gain for Band0 for temp index 23 in case of External LNA Control Gain for DVGA Index 23 in case of External DVGA control 2 13 216 Register 4ECh offset 4ECh reset 0h Figure 2 1628 Register 4ECh 7 6 5 4 3 2 1 0 RX_AGC_BA...

Page 777: ...25 in case of External LNA Control Gain for DVGA Index 25 in case of External DVGA control 2 13 219 Register 4EFh offset 4EFh reset 0h Figure 2 1631 Register 4EFh 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_GAIN25 10 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1644 Register 4EF Field Descriptions Bit Field Type Reset Description 2 0 RX_AGC_BAND0_ LNA_GAIN25 10 8 R W 0h LNA Gain fo...

Page 778: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1647 Register 4F2 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND0_ LNA_GAIN27 7 0 R W 0h LNA Gain for Band0 for temp index 27 in case of External LNA Control Gain for DVGA Index 27 in case of External DVGA control 2 13 223 Register 4F3h offset 4F3h reset 0h Figure 2 1635 Register 4F3h 7 6 5 4 3 2 1 0 RX_AGC_BAN...

Page 779: ... 28 in case of External LNA Control Gain for DVGA Index 28 in case of External DVGA control 2 13 226 Register 4F6h offset 4F6h reset 0h Figure 2 1638 Register 4F6h 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_GAIN29 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1651 Register 4F6 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND0_ LNA_GAIN29 7 0 R W 0h LNA Gain for...

Page 780: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1654 Register 4F9 Field Descriptions Bit Field Type Reset Description 2 0 RX_AGC_BAND0_ LNA_GAIN30 10 8 R W 0h LNA Gain for Band0 for temp index 30 in case of External LNA Control Gain for DVGA Index 30 in case of External DVGA control 2 13 230 Register 4FAh offset 4FAh reset 0h Figure 2 1642 Register 4FAh 7 6 5 4 3 2 1 0 RX_AGC_BA...

Page 781: ...ex 0 in case of External LNA Control Gain for DVGA Index 32 in case of External DVGA control 2 13 233 Register 4FDh offset 4FDh reset 0h Figure 2 1645 Register 4FDh 7 6 5 4 3 2 1 0 RX_AGC_BAND1_LNA_GAIN0 10 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1658 Register 4FD Field Descriptions Bit Field Type Reset Description 2 0 RX_AGC_BAND1_ LNA_GAIN0 10 8 R W 0h LNA Gain fo...

Page 782: ...W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1661 Register 500 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_GAIN2 7 0 R W 0h LNA Gain for Band1 for temp index 2 in case of External LNA Control Gain for DVGA Index 34 in case of External DVGA control 2 13 237 Register 501h offset 501h reset 0h Figure 2 1649 Register 501h 7 6 5 4 3 2 1 0 RX_AGC_BAND...

Page 783: ...x 3 in case of External LNA Control Gain for DVGA Index 35 in case of External DVGA control 2 13 240 Register 504h offset 504h reset 0h Figure 2 1652 Register 504h 7 6 5 4 3 2 1 0 RX_AGC_BAND1_LNA_GAIN4 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1665 Register 504 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_GAIN4 7 0 R W 0h LNA Gain for B...

Page 784: ...W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1668 Register 507 Field Descriptions Bit Field Type Reset Description 2 0 RX_AGC_BAND1_ LNA_GAIN5 10 8 R W 0h LNA Gain for Band1 for temp index 5 in case of External LNA Control Gain for DVGA Index 37 in case of External DVGA control 2 13 244 Register 508h offset 508h reset 0h Figure 2 1656 Register 508h 7 6 5 4 3 2 1 0 RX_AGC_BAN...

Page 785: ...x 7 in case of External LNA Control Gain for DVGA Index 39 in case of External DVGA control 2 13 247 Register 50Bh offset 50Bh reset 0h Figure 2 1659 Register 50Bh 7 6 5 4 3 2 1 0 RX_AGC_BAND1_LNA_GAIN7 10 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1672 Register 50B Field Descriptions Bit Field Type Reset Description 2 0 RX_AGC_BAND1_ LNA_GAIN7 10 8 R W 0h LNA Gain for...

Page 786: ...W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1675 Register 50E Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_GAIN9 7 0 R W 0h LNA Gain for Band1 for temp index 9 in case of External LNA Control Gain for DVGA Index 41 in case of External DVGA control 2 13 251 Register 50Fh offset 50Fh reset 0h Figure 2 1663 Register 50Fh 7 6 5 4 3 2 1 0 RX_AGC_BAND...

Page 787: ... 10 in case of External LNA Control Gain for DVGA Index 42 in case of External DVGA control 2 13 254 Register 512h offset 512h reset 0h Figure 2 1666 Register 512h 7 6 5 4 3 2 1 0 RX_AGC_BAND1_LNA_GAIN11 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1679 Register 512 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_GAIN11 7 0 R W 0h LNA Gain for...

Page 788: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1682 Register 515 Field Descriptions Bit Field Type Reset Description 2 0 RX_AGC_BAND1_ LNA_GAIN12 10 8 R W 0h LNA Gain for Band1 for temp index 12 in case of External LNA Control Gain for DVGA Index 44 in case of External DVGA control 2 13 258 Register 516h offset 516h reset 0h Figure 2 1670 Register 516h 7 6 5 4 3 2 1 0 RX_AGC_BA...

Page 789: ...14 in case of External LNA Control Gain for DVGA Index 46 in case of External DVGA control 2 13 261 Register 519h offset 519h reset 0h Figure 2 1673 Register 519h 7 6 5 4 3 2 1 0 RX_AGC_BAND1_LNA_GAIN14 10 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1686 Register 519 Field Descriptions Bit Field Type Reset Description 2 0 RX_AGC_BAND1_ LNA_GAIN14 10 8 R W 0h LNA Gain fo...

Page 790: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1689 Register 51C Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_GAIN16 7 0 R W 0h LNA Gain for Band1 for temp index 16 in case of External LNA Control Gain for DVGA Index 48 in case of External DVGA control 2 13 265 Register 51Dh offset 51Dh reset 0h Figure 2 1677 Register 51Dh 7 6 5 4 3 2 1 0 RX_AGC_BAN...

Page 791: ... 17 in case of External LNA Control Gain for DVGA Index 49 in case of External DVGA control 2 13 268 Register 520h offset 520h reset 0h Figure 2 1680 Register 520h 7 6 5 4 3 2 1 0 RX_AGC_BAND1_LNA_GAIN18 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1693 Register 520 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_GAIN18 7 0 R W 0h LNA Gain for...

Page 792: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1696 Register 523 Field Descriptions Bit Field Type Reset Description 2 0 RX_AGC_BAND1_ LNA_GAIN19 10 8 R W 0h LNA Gain for Band1 for temp index 19 in case of External LNA Control Gain for DVGA Index 51 in case of External DVGA control 2 13 272 Register 524h offset 524h reset 0h Figure 2 1684 Register 524h 7 6 5 4 3 2 1 0 RX_AGC_BA...

Page 793: ...21 in case of External LNA Control Gain for DVGA Index 53 in case of External DVGA control 2 13 275 Register 527h offset 527h reset 0h Figure 2 1687 Register 527h 7 6 5 4 3 2 1 0 RX_AGC_BAND1_LNA_GAIN21 10 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1700 Register 527 Field Descriptions Bit Field Type Reset Description 2 0 RX_AGC_BAND1_ LNA_GAIN21 10 8 R W 0h LNA Gain fo...

Page 794: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1703 Register 52A Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_GAIN23 7 0 R W 0h LNA Gain for Band1 for temp index 23 in case of External LNA Control Gain for DVGA Index 55 in case of External DVGA control 2 13 279 Register 52Bh offset 52Bh reset 0h Figure 2 1691 Register 52Bh 7 6 5 4 3 2 1 0 RX_AGC_BAN...

Page 795: ... 24 in case of External LNA Control Gain for DVGA Index 56 in case of External DVGA control 2 13 282 Register 52Eh offset 52Eh reset 0h Figure 2 1694 Register 52Eh 7 6 5 4 3 2 1 0 RX_AGC_BAND1_LNA_GAIN25 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1707 Register 52E Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_GAIN25 7 0 R W 0h LNA Gain for...

Page 796: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1710 Register 531 Field Descriptions Bit Field Type Reset Description 2 0 RX_AGC_BAND1_ LNA_GAIN26 10 8 R W 0h LNA Gain for Band1 for temp index 26 in case of External LNA Control Gain for DVGA Index 58 in case of External DVGA control 2 13 286 Register 532h offset 532h reset 0h Figure 2 1698 Register 532h 7 6 5 4 3 2 1 0 RX_AGC_BA...

Page 797: ...28 in case of External LNA Control Gain for DVGA Index 60 in case of External DVGA control 2 13 289 Register 535h offset 535h reset 0h Figure 2 1701 Register 535h 7 6 5 4 3 2 1 0 RX_AGC_BAND1_LNA_GAIN28 10 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1714 Register 535 Field Descriptions Bit Field Type Reset Description 2 0 RX_AGC_BAND1_ LNA_GAIN28 10 8 R W 0h LNA Gain fo...

Page 798: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1717 Register 538 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_GAIN30 7 0 R W 0h LNA Gain for Band1 for temp index 30 in case of External LNA Control Gain for DVGA Index 62 in case of External DVGA control 2 13 293 Register 539h offset 539h reset 0h Figure 2 1705 Register 539h 7 6 5 4 3 2 1 0 RX_AGC_BAN...

Page 799: ...r DVGA Index 63 in case of External DVGA control 2 13 296 Register 53Ch offset 53Ch reset 0h Figure 2 1708 Register 53Ch 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_PHASE0 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1721 Register 53C Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND0_ LNA_PHASE0 7 0 R W 0h LNA Phase for Band0 for temp index 0 in case of Externa...

Page 800: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1724 Register 53F Field Descriptions Bit Field Type Reset Description 1 0 RX_AGC_BAND0_ LNA_PHASE1 9 8 R W 0h LNA Phase for Band0 for temp index 1 in case of External LNA Control Phase for DVGA Index 1 in case of External DVGA control 2 13 300 Register 540h offset 540h reset 0h Figure 2 1712 Register 540h 7 6 5 4 3 2 1 0 RX_AGC_BAN...

Page 801: ... 3 in case of External LNA Control Phase for DVGA Index 3 in case of External DVGA control 2 13 303 Register 543h offset 543h reset 0h Figure 2 1715 Register 543h 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_PHASE 3 9 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1728 Register 543 Field Descriptions Bit Field Type Reset Description 1 0 RX_AGC_BAND0_ LNA_PHASE3 9 8 R W 0h LNA Phase fo...

Page 802: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1731 Register 546 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND0_ LNA_PHASE5 7 0 R W 0h LNA Phase for Band0 for temp index 5 in case of External LNA Control Phase for DVGA Index 5 in case of External DVGA control 2 13 307 Register 547h offset 547h reset 0h Figure 2 1719 Register 547h 7 6 5 4 3 2 1 0 RX_AGC_BAN...

Page 803: ...x 6 in case of External LNA Control Phase for DVGA Index 6 in case of External DVGA control 2 13 310 Register 54Ah offset 54Ah reset 0h Figure 2 1722 Register 54Ah 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_PHASE7 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1735 Register 54A Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND0_ LNA_PHASE7 7 0 R W 0h LNA Phase fo...

Page 804: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1738 Register 54D Field Descriptions Bit Field Type Reset Description 1 0 RX_AGC_BAND0_ LNA_PHASE8 9 8 R W 0h LNA Phase for Band0 for temp index 8 in case of External LNA Control Phase for DVGA Index 8 in case of External DVGA control 2 13 314 Register 54Eh offset 54Eh reset 0h Figure 2 1726 Register 54Eh 7 6 5 4 3 2 1 0 RX_AGC_BAN...

Page 805: ...in case of External LNA Control Phase for DVGA Index 10 in case of External DVGA control 2 13 317 Register 551h offset 551h reset 0h Figure 2 1729 Register 551h 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_PHASE 10 9 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1742 Register 551 Field Descriptions Bit Field Type Reset Description 1 0 RX_AGC_BAND0_ LNA_PHASE10 9 8 R W 0h LNA Phase fo...

Page 806: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 1745 Register 554 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND0_ LNA_PHASE12 7 0 R W 0h LNA Phase for Band0 for temp index 12 in case of External LNA Control Phase for DVGA Index 12 in case of External DVGA control 2 13 321 Register 555h offset 555h reset 0h Figure 2 1733 Register 555h 7 6 5 4 3 2 1 0 RX_AGC_B...

Page 807: ...3 in case of External LNA Control Phase for DVGA Index 13 in case of External DVGA control 2 13 324 Register 558h offset 558h reset 0h Figure 2 1736 Register 558h 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_PHASE14 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1749 Register 558 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND0_ LNA_PHASE14 7 0 R W 0h LNA Phase f...

Page 808: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 1752 Register 55B Field Descriptions Bit Field Type Reset Description 1 0 RX_AGC_BAND0_ LNA_PHASE15 9 8 R W 0h LNA Phase for Band0 for temp index 15 in case of External LNA Control Phase for DVGA Index 15 in case of External DVGA control 2 13 328 Register 55Ch offset 55Ch reset 0h Figure 2 1740 Register 55Ch 7 6 5 4 3 2 1 0 RX_AGC_B...

Page 809: ...7 in case of External LNA Control Phase for DVGA Index 17 in case of External DVGA control 2 13 331 Register 55Fh offset 55Fh reset 0h Figure 2 1743 Register 55Fh 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_PHASE 17 9 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1756 Register 55F Field Descriptions Bit Field Type Reset Description 1 0 RX_AGC_BAND0_ LNA_PHASE17 9 8 R W 0h LNA Phase ...

Page 810: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 1759 Register 562 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND0_ LNA_PHASE19 7 0 R W 0h LNA Phase for Band0 for temp index 19 in case of External LNA Control Phase for DVGA Index 19 in case of External DVGA control 2 13 335 Register 563h offset 563h reset 0h Figure 2 1747 Register 563h 7 6 5 4 3 2 1 0 RX_AGC_B...

Page 811: ...0 in case of External LNA Control Phase for DVGA Index 20 in case of External DVGA control 2 13 338 Register 566h offset 566h reset 0h Figure 2 1750 Register 566h 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_PHASE21 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1763 Register 566 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND0_ LNA_PHASE21 7 0 R W 0h LNA Phase f...

Page 812: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 1766 Register 569 Field Descriptions Bit Field Type Reset Description 1 0 RX_AGC_BAND0_ LNA_PHASE22 9 8 R W 0h LNA Phase for Band0 for temp index 22 in case of External LNA Control Phase for DVGA Index 22 in case of External DVGA control 2 13 342 Register 56Ah offset 56Ah reset 0h Figure 2 1754 Register 56Ah 7 6 5 4 3 2 1 0 RX_AGC_B...

Page 813: ...4 in case of External LNA Control Phase for DVGA Index 24 in case of External DVGA control 2 13 345 Register 56Dh offset 56Dh reset 0h Figure 2 1757 Register 56Dh 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_PHASE 24 9 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1770 Register 56D Field Descriptions Bit Field Type Reset Description 1 0 RX_AGC_BAND0_ LNA_PHASE24 9 8 R W 0h LNA Phase ...

Page 814: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 1773 Register 570 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND0_ LNA_PHASE26 7 0 R W 0h LNA Phase for Band0 for temp index 26 in case of External LNA Control Phase for DVGA Index 26 in case of External DVGA control 2 13 349 Register 571h offset 571h reset 0h Figure 2 1761 Register 571h 7 6 5 4 3 2 1 0 RX_AGC_B...

Page 815: ...7 in case of External LNA Control Phase for DVGA Index 27 in case of External DVGA control 2 13 352 Register 574h offset 574h reset 0h Figure 2 1764 Register 574h 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_PHASE28 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1777 Register 574 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND0_ LNA_PHASE28 7 0 R W 0h LNA Phase f...

Page 816: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 1780 Register 577 Field Descriptions Bit Field Type Reset Description 1 0 RX_AGC_BAND0_ LNA_PHASE29 9 8 R W 0h LNA Phase for Band0 for temp index 29 in case of External LNA Control Phase for DVGA Index 29 in case of External DVGA control 2 13 356 Register 578h offset 578h reset 0h Figure 2 1768 Register 578h 7 6 5 4 3 2 1 0 RX_AGC_B...

Page 817: ...31 in case of External LNA Control Phase for DVGA Index 31 in case of External DVGA control 2 13 359 Register 57Bh offset 57Bh reset 0h Figure 2 1771 Register 57Bh 7 6 5 4 3 2 1 0 RX_AGC_BAND0_LNA_PHASE 31 9 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1784 Register 57B Field Descriptions Bit Field Type Reset Description 1 0 RX_AGC_BAND0_ LNA_PHASE31 9 8 R W 0h LNA Phase...

Page 818: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1787 Register 57E Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_PHASE1 7 0 R W 0h LNA Phase for Band1 for temp index 1 in case of External LNA Control Phase for DVGA Index 33 in case of External DVGA control 2 13 363 Register 57Fh offset 57Fh reset 0h Figure 2 1775 Register 57Fh 7 6 5 4 3 2 1 0 RX_AGC_BA...

Page 819: ... 2 in case of External LNA Control Phase for DVGA Index 34 in case of External DVGA control 2 13 366 Register 582h offset 582h reset 0h Figure 2 1778 Register 582h 7 6 5 4 3 2 1 0 RX_AGC_BAND1_LNA_PHASE3 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1791 Register 582 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_PHASE3 7 0 R W 0h LNA Phase fo...

Page 820: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1794 Register 585 Field Descriptions Bit Field Type Reset Description 1 0 RX_AGC_BAND1_ LNA_PHASE4 9 8 R W 0h LNA Phase for Band1 for temp index 4 in case of External LNA Control Phase for DVGA Index 36 in case of External DVGA control 2 13 370 Register 586h offset 586h reset 0h Figure 2 1782 Register 586h 7 6 5 4 3 2 1 0 RX_AGC_BA...

Page 821: ...6 in case of External LNA Control Phase for DVGA Index 38 in case of External DVGA control 2 13 373 Register 589h offset 589h reset 0h Figure 2 1785 Register 589h 7 6 5 4 3 2 1 0 RX_AGC_BAND1_LNA_PHASE 6 9 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1798 Register 589 Field Descriptions Bit Field Type Reset Description 1 0 RX_AGC_BAND1_ LNA_PHASE6 9 8 R W 0h LNA Phase fo...

Page 822: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 1801 Register 58C Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_PHASE8 7 0 R W 0h LNA Phase for Band1 for temp index 8 in case of External LNA Control Phase for DVGA Index 40 in case of External DVGA control 2 13 377 Register 58Dh offset 58Dh reset 0h Figure 2 1789 Register 58Dh 7 6 5 4 3 2 1 0 RX_AGC_BA...

Page 823: ...in case of External LNA Control Phase for DVGA Index 41 in case of External DVGA control 2 13 380 Register 590h offset 590h reset 0h Figure 2 1792 Register 590h 7 6 5 4 3 2 1 0 RX_AGC_BAND1_LNA_PHASE10 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1805 Register 590 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_PHASE10 7 0 R W 0h LNA Phase for...

Page 824: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 1808 Register 593 Field Descriptions Bit Field Type Reset Description 1 0 RX_AGC_BAND1_ LNA_PHASE11 9 8 R W 0h LNA Phase for Band1 for temp index 11 in case of External LNA Control Phase for DVGA Index 43 in case of External DVGA control 2 13 384 Register 594h offset 594h reset 0h Figure 2 1796 Register 594h 7 6 5 4 3 2 1 0 RX_AGC_B...

Page 825: ...3 in case of External LNA Control Phase for DVGA Index 45 in case of External DVGA control 2 13 387 Register 597h offset 597h reset 0h Figure 2 1799 Register 597h 7 6 5 4 3 2 1 0 RX_AGC_BAND1_LNA_PHASE 13 9 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1812 Register 597 Field Descriptions Bit Field Type Reset Description 1 0 RX_AGC_BAND1_ LNA_PHASE13 9 8 R W 0h LNA Phase ...

Page 826: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 1815 Register 59A Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_PHASE15 7 0 R W 0h LNA Phase for Band1 for temp index 15 in case of External LNA Control Phase for DVGA Index 47 in case of External DVGA control 2 13 391 Register 59Bh offset 59Bh reset 0h Figure 2 1803 Register 59Bh 7 6 5 4 3 2 1 0 RX_AGC_B...

Page 827: ...6 in case of External LNA Control Phase for DVGA Index 48 in case of External DVGA control 2 13 394 Register 59Eh offset 59Eh reset 0h Figure 2 1806 Register 59Eh 7 6 5 4 3 2 1 0 RX_AGC_BAND1_LNA_PHASE17 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1819 Register 59E Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_PHASE17 7 0 R W 0h LNA Phase f...

Page 828: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 1822 Register 5A1 Field Descriptions Bit Field Type Reset Description 1 0 RX_AGC_BAND1_ LNA_PHASE18 9 8 R W 0h LNA Phase for Band1 for temp index 18 in case of External LNA Control Phase for DVGA Index 50 in case of External DVGA control 2 13 398 Register 5A2h offset 5A2h reset 0h Figure 2 1810 Register 5A2h 7 6 5 4 3 2 1 0 RX_AGC_B...

Page 829: ...0 in case of External LNA Control Phase for DVGA Index 52 in case of External DVGA control 2 13 401 Register 5A5h offset 5A5h reset 0h Figure 2 1813 Register 5A5h 7 6 5 4 3 2 1 0 RX_AGC_BAND1_LNA_PHASE 20 9 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1826 Register 5A5 Field Descriptions Bit Field Type Reset Description 1 0 RX_AGC_BAND1_ LNA_PHASE20 9 8 R W 0h LNA Phase ...

Page 830: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 1829 Register 5A8 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_PHASE22 7 0 R W 0h LNA Phase for Band1 for temp index 22 in case of External LNA Control Phase for DVGA Index 54 in case of External DVGA control 2 13 405 Register 5A9h offset 5A9h reset 0h Figure 2 1817 Register 5A9h 7 6 5 4 3 2 1 0 RX_AGC_B...

Page 831: ...3 in case of External LNA Control Phase for DVGA Index 55 in case of External DVGA control 2 13 408 Register 5ACh offset 5ACh reset 0h Figure 2 1820 Register 5ACh 7 6 5 4 3 2 1 0 RX_AGC_BAND1_LNA_PHASE24 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1833 Register 5AC Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_PHASE24 7 0 R W 0h LNA Phase f...

Page 832: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 1836 Register 5AF Field Descriptions Bit Field Type Reset Description 1 0 RX_AGC_BAND1_ LNA_PHASE25 9 8 R W 0h LNA Phase for Band1 for temp index 25 in case of External LNA Control Phase for DVGA Index 57 in case of External DVGA control 2 13 412 Register 5B0h offset 5B0h reset 0h Figure 2 1824 Register 5B0h 7 6 5 4 3 2 1 0 RX_AGC_B...

Page 833: ...7 in case of External LNA Control Phase for DVGA Index 59 in case of External DVGA control 2 13 415 Register 5B3h offset 5B3h reset 0h Figure 2 1827 Register 5B3h 7 6 5 4 3 2 1 0 RX_AGC_BAND1_LNA_PHASE 27 9 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1840 Register 5B3 Field Descriptions Bit Field Type Reset Description 1 0 RX_AGC_BAND1_ LNA_PHASE27 9 8 R W 0h LNA Phase ...

Page 834: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 1843 Register 5B6 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_PHASE29 7 0 R W 0h LNA Phase for Band1 for temp index 29 in case of External LNA Control Phase for DVGA Index 61 in case of External DVGA control 2 13 419 Register 5B7h offset 5B7h reset 0h Figure 2 1831 Register 5B7h 7 6 5 4 3 2 1 0 RX_AGC_B...

Page 835: ...0 in case of External LNA Control Phase for DVGA Index 62 in case of External DVGA control 2 13 422 Register 5BAh offset 5BAh reset 0h Figure 2 1834 Register 5BAh 7 6 5 4 3 2 1 0 RX_AGC_BAND1_LNA_PHASE31 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1847 Register 5BA Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_BAND1_ LNA_PHASE31 7 0 R W 0h LNA Phase f...

Page 836: ...ister 5C0 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_CLK_DI V_FACTOR_DVGA _CTRL 7 0 R W 5h Clock divide factor for external DVGA control module This factor is used to derive the SPI clock when the device is acting as a master to control external dvga settings Should be programmed such that the output clock is 25 MHz dvga_spi_clock Fs 8 clk_div_factor_dvga_ctrl 1 2 13 426 Regist...

Page 837: ...5C4h reset 0h Figure 2 1840 Register 5C4h 7 6 5 4 3 2 1 0 RX_AGC_UPD ATE_DET_STA TUS R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1853 Register 5C4 Field Descriptions Bit Field Type Reset Description 0 0 RX_AGC_UPDATE _DET_STATUS R W 0h Update pulse for all detector read out status including Digital peak power analog and band detectors 2 13 429 Register 5D0h offset 5D0h re...

Page 838: ...DIG_DET_NUM_HITS_SEEN 7 0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1856 Register 5D4 Field Descriptions Bit Field Type Reset Description 7 0 RX_AGC_DIG_DE T_NUM_HITS_SE EN 7 0 R 0h Indicates Number of Hits observed Based on dig_det_read_sel the corresponding digital peak detector status is read This will get updated only when update pulse is given Running accum mode shou...

Page 839: ...ATT ACK R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1859 Register 5DC Field Descriptions Bit Field Type Reset Description 0 0 RX_AGC_USE_AL L_DETECTORS_A S_ATTACK R W 0h Used only in external agc mode When high this will make all the decay detectors also behave like attack detectors 2 13 435 Register 5E0h offset 5E0h reset 0h Figure 2 1847 Register 5E0h 7 6 5 4 3 2 1 0 RX...

Page 840: ...2 1 0 RX_AGC_MIN_ATTN_USED R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1862 Register 5E5 Field Descriptions Bit Field Type Reset Description 5 0 RX_AGC_MIN_AT TN_USED R 0h Min attenuation seen by stat module This is in 0 5 dB resolution 2 13 438 Register 5E6h offset 5E6h reset 0h Figure 2 1850 Register 5E6h 7 6 5 4 3 2 1 0 RX_AGC_MAX_DVGA_ATTN_USED R 0h LEGEND R W Read Writ...

Page 841: ...A_ BYPASS R 0h Current external LNA control for Band1 0 Ext LNA is Enabled 1 Ext LNA is Bypassed 6 6 RX_AGC_BAND0_ CURR_EXT_LNA_ BYPASS R 0h Current external LNA control for Band0 0 Ext LNA is Enabled 1 Ext LNA is Bypassed 5 0 RX_AGC_CURR_ DVGA_ATTN R 0h Current value of External DVGA attn This is in 0 5 dB resolution 2 13 441 Register 5E9h offset 5E9h reset 0h Figure 2 1853 Register 5E9h 7 6 5 4 ...

Page 842: ...gure 2 1855 Register 5ECh 7 6 5 4 3 2 1 0 RX_AGC_CUR R_EXT_LNA_E N R 0h LEGEND R W Read Write W Write only n value after reset Table 2 1868 Register 5EC Field Descriptions Bit Field Type Reset Description 0 0 RX_AGC_CURR_E XT_LNA_EN R 0h Current external LNA enable 0 Ext LNA is bypassed 1 Ext LNA is enabled 2 13 444 Register 634h offset 634h reset 0h Figure 2 1856 Register 634h 7 6 5 4 3 2 1 0 RX_...

Page 843: ...3 2 1 0 RX_ALC_USE_ LSB_PLUS_ON E_BIT_FOR_C ONTROL RX_ALC_USE_ LSB_BIT_FOR _CONTROL R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1871 Register 636 Field Descriptions Bit Field Type Reset Description 1 1 RX_ALC_USE_LS B_PLUS_ONE_BIT _FOR_CONTROL R W 0h Enables the penultimate LSB bit to be used for control information so that Peak detector output can be sent on it th...

Page 844: ...638h reset 20h Figure 2 1860 Register 638h 7 6 5 4 3 2 1 0 RX_ALC_TOTAL_GAIN_RANGE R W 20h LEGEND R W Read Write W Write only n value after reset Table 2 1873 Register 638 Field Descriptions Bit Field Type Reset Description 6 0 RX_ALC_TOTAL_ GAIN_RANGE R W 20h Total Gain Range to be supported by DGC Total Gain Compensation is saturated to this value Allowable range is 0 to 66 dB in steps of 1 dB 2...

Page 845: ...1 reserved 2 2 bits Used for DGC mode 2 3 4 3 3 bits Used for DGC modes 2 4 4 4 bits Used only in DGC mode 3 5 reserved 6 reserved 7 reserved 2 13 451 Register 63Dh offset 63Dh reset 0h Figure 2 1863 Register 63Dh 7 6 5 4 3 2 1 0 RX_ALC_COA RSE_INDEX_S WAP_IQ RX_ALC_COA RSE_INDEX_I NVERT R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1876 Register 63D Field Descriptio...

Page 846: ...h Figure 2 1865 Register 640h 7 6 5 4 3 2 1 0 RX_ALC_OUTPUT_PIN_DELAY 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1878 Register 640 Field Descriptions Bit Field Type Reset Description 7 0 RX_ALC_OUTPUT _PIN_DELAY 7 0 R W 0h Delay in fs 8 clocks imparted on the ALC output pins This can be used by the customer to match the ALC pin information with latency of the data th...

Page 847: ... attenuation from AGC instead of rx_alc_min_attn_dsa 2 13 457 Register 64Ch offset 64Ch reset 0h Figure 2 1869 Register 64Ch 7 6 5 4 3 2 1 0 RX_ALC_USE_ LSB_BIT_FOR _CONTROL_F B RX_ALC_USE_ 12BIT_SEL_FB R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1882 Register 64C Field Descriptions Bit Field Type Reset Description 1 1 RX_ALC_USE_LS B_BIT_FOR_CON TROL_FB R W 0h Ena...

Page 848: ...t Field Type Reset Description 5 0 RX_ALC_BAND1_ EXT_COMP_MIN_ ATTN R W 0h Min value of external DVGA LNA gain for Band1 DGC will compensate for gain changes only above this value 2 13 460 Register 6A4h offset 6A4h reset 3h Figure 2 1872 Register 6A4h 7 6 5 4 3 2 1 0 reserved RX_ALC_GAIN _CHANGE_IND _EN R W 1h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 1885 Register 6A4 ...

Page 849: ... the MSB bit of mantissa if Exponent is 0 v 1 Power S X T for E 0 i e v 2powert v 1 power S 0xb7 2 power t T 0xb72 power E 1 for E 0 i e v 0x2265 2 power t 1 send the MSB bit of mantissa always v 1 power S 0xb7T 0xb72 power E for all values of E S is Sign bit T is Mantissa E is exponent 2 13 463 Register 6D5h offset 6D5h reset 0h Figure 2 1875 Register 6D5h 7 6 5 4 3 2 1 0 RX_ALC_FLOATING_POINT_F ...

Page 850: ...eVal 2 13 465 Register 710h offset 710h reset 0h Figure 2 1877 Register 710h 7 6 5 4 3 2 1 0 RX_DDC_PROG_DELAY R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1890 Register 710 Field Descriptions Bit Field Type Reset Description 4 0 RX_DDC_PROG_ DELAY R W 0h Programmable delay in ADC clock cycles Valid range 0 through 31 2 13 466 Register 711h offset 711h reset 0h Figure 2 18...

Page 851: ...tire RX channel 0 Normal mode of operation 2 13 469 Register 771h offset 771h reset 0h Figure 2 1881 Register 771h 7 6 5 4 3 2 1 0 RX_DDC_PRE _DECIM_PDN R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1894 Register 771 Field Descriptions Bit Field Type Reset Description 0 0 RX_DDC_PRE_DE CIM_PDN R W 0h Power down the pre decimation section of RX channel 1 Power down the Pre D...

Page 852: ...er Maps 2 13 471 Register 773h offset 773h reset 0h Figure 2 1883 Register 773h 7 6 5 4 3 2 1 0 RX_AGC_PDN R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1896 Register 773 Field Descriptions Bit Field Type Reset Description 0 0 RX_AGC_PDN R W 0h Power down the AGC 1 Power down the AGC of the RX channel 0 Normal mode of operation ...

Page 853: ...Bh FB_DDC_NCO2_FCW 31 24 ACh FB_DDC_NCO3_FCW 7 0 ADh FB_DDC_NCO3_FCW 15 8 AEh FB_DDC_NCO3_FCW 23 16 AFh FB_DDC_NCO3_FCW 31 24 E0h FB_DDC_NCO0_PHASE_OFFSET 7 0 E1h FB_DDC_NCO0_PHASE_OFFSET 15 8 E2h FB_DDC_NCO1_PHASE_OFFSET 7 0 E3h FB_DDC_NCO1_PHASE_OFFSET 15 8 E4h FB_DDC_NCO2_PHASE_OFFSET 7 0 E5h FB_DDC_NCO2_PHASE_OFFSET 15 8 E6h FB_DDC_NCO3_PHASE_OFFSET 7 0 E7h FB_DDC_NCO3_PHASE_OFFSET 15 8 100h F...

Page 854: ...SIZE 409h FB_AGC_SMALL_STEP_ATTACK_STEP_SIZE 40Ah FB_AGC_BIG_STEP_DECAY_STEP_SIZE 40Bh FB_AGC_SMALL_STEP_DECAY_STEP_SIZE 40Ch FB_AGC_PWR_ATTACK_STEP_SIZE 40Dh FB_AGC_PWR_DECAY_STEP_SIZE 410h FB_AGC_LNARF_ATTACK_STEP_SIZE 414h FB_AGC_BIG_STEP_ATTACK_WIN_LEN 7 0 415h FB_AGC_BIG_STEP_ATTACK_WIN_LEN 15 8 416h FB_AGC_BIG_STEP_ATTACK_WIN_LEN 23 16 418h FB_AGC_SMALL_STEP_ATTACK_WIN_LEN 7 0 419h FB_AGC_SM...

Page 855: ...UM_HITS 27 24 498h FB_AGC_EXT_ MODE FB_AGC_INTER NAL_EN 499h FB_AGC_FREE ZE_PIN_EN 49Ah FB_AGC_FREE ZE 49Ch FB_AGC_DEF_ATTN 49Dh FB_AGC_DEF_L NA_BYP_VAL_B 0 49Eh FB_AGC_DEF_L NA_BYP_VAL_B 1 49Fh FB_AGC_DEF_DVGA_ATTN 4A0h FB_AGC_MAX_ATTN 4A1h FB_AGC_MIN_ATTN 4A2h FB_AGC_MAX_DVGA_ATTN 4A3h FB_AGC_MIN_DVGA_ATTN 4A4h FB_AGC_RESE T_LOOP_AT_SI G_INVALID FB_AGC_DECA Y_DETS_RESE T_AT_RX_ON FB_AGC_ATTA CK_...

Page 856: ...GAIN12 7 0 4D5h FB_AGC_BAND0_LNA_GAIN12 10 8 4D6h FB_AGC_BAND0_LNA_GAIN13 7 0 4D7h FB_AGC_BAND0_LNA_GAIN13 10 8 4D8h FB_AGC_BAND0_LNA_GAIN14 7 0 4D9h FB_AGC_BAND0_LNA_GAIN14 10 8 4DAh FB_AGC_BAND0_LNA_GAIN15 7 0 4DBh FB_AGC_BAND0_LNA_GAIN15 10 8 4DCh FB_AGC_BAND0_LNA_GAIN16 7 0 4DDh FB_AGC_BAND0_LNA_GAIN16 10 8 4DEh FB_AGC_BAND0_LNA_GAIN17 7 0 4DFh FB_AGC_BAND0_LNA_GAIN17 10 8 4E0h FB_AGC_BAND0_LN...

Page 857: ...NA_PHASE5 7 0 547h FB_AGC_BAND0_LNA_PHASE5 9 8 548h FB_AGC_BAND0_LNA_PHASE6 7 0 549h FB_AGC_BAND0_LNA_PHASE6 9 8 54Ah FB_AGC_BAND0_LNA_PHASE7 7 0 54Bh FB_AGC_BAND0_LNA_PHASE7 9 8 54Ch FB_AGC_BAND0_LNA_PHASE8 7 0 54Dh FB_AGC_BAND0_LNA_PHASE8 9 8 54Eh FB_AGC_BAND0_LNA_PHASE9 7 0 54Fh FB_AGC_BAND0_LNA_PHASE9 9 8 550h FB_AGC_BAND0_LNA_PHASE10 7 0 551h FB_AGC_BAND0_LNA_PHASE10 9 8 552h FB_AGC_BAND0_LNA...

Page 858: ...AGC_BAND0_LNA_PHASE26 9 8 572h FB_AGC_BAND0_LNA_PHASE27 7 0 573h FB_AGC_BAND0_LNA_PHASE27 9 8 574h FB_AGC_BAND0_LNA_PHASE28 7 0 575h FB_AGC_BAND0_LNA_PHASE28 9 8 576h FB_AGC_BAND0_LNA_PHASE29 7 0 577h FB_AGC_BAND0_LNA_PHASE29 9 8 578h FB_AGC_BAND0_LNA_PHASE30 7 0 579h FB_AGC_BAND0_LNA_PHASE30 9 8 57Ah FB_AGC_BAND0_LNA_PHASE31 7 0 57Bh FB_AGC_BAND0_LNA_PHASE31 9 8 5BCh FB_AGC_ENAB LE_GPIO_RESE T_FE...

Page 859: ...L_GAIN_RANGE 639h FB_ALC_SIG_BACKOFF_DB 63Ah FB_ALC_GAIN_OFFSET_INPUT_ALC 63Ch FB_ALC_COARSE_STEP FB_ALC_NUM_BITS_COARSE_INDEX 63Dh FB_ALC_COAR SE_INDEX_SW AP_IQ FB_ALC_COAR SE_INDEX_INV ERT 63Eh FB_ALC_FINE_EXP_OFFSET FB_ALC_FINE_OFFSET 640h FB_ALC_OUTPUT_PIN_DELAY 7 0 641h FB_ALC_OUTPUT_PIN_DELAY 13 8 642h FB_ALC_INPUT_DELAY_CODE 644h FB_ALC_EXP_O FFSET_INPUT_ ALC_FORCE 645h FB_ALC_EXP_OFFSET_IN...

Page 860: ...10 06 decimation factor 20 07 decimation factor 40 08 decimation factor 12 10 decimation factor 24 11 decimation factor 48 16 decimation factor 4 32 decimation factor 2 5 48 decimation factor 5 64 decimation factor 3 80 decimation factor 6 2 14 2 Register 41h offset 41h reset 1h Figure 2 1885 Register 41h 7 6 5 4 3 2 1 0 FB_DDC_2X_S CALE_CONFIG R W 1h LEGEND R W Read Write W Write only n value aft...

Page 861: ...l value automatically determined if System Configuration Macros are used 2 14 5 Register 49h offset 49h reset 4h Figure 2 1888 Register 49h 7 6 5 4 3 2 1 0 FB_DDC_FIFO_CONFIG1 R W 4h LEGEND R W Read Write W Write only n value after reset Table 2 1902 Register 49 Field Descriptions Bit Field Type Reset Description 4 0 FB_DDC_FIFO_C ONFIG1 R W 4h FB DDC FIFO Configuration1 Value dependent on decimat...

Page 862: ...er 61h 7 6 5 4 3 2 1 0 FB_DDC_ASYNC_FIFO_CONFIG1 R W 44h LEGEND R W Read Write W Write only n value after reset Table 2 1905 Register 61 Field Descriptions Bit Field Type Reset Description 7 0 FB_DDC_ASYNC_ FIFO_CONFIG1 R W 44h Pointer offset value Valid range 0 to 15 2 14 9 Register 70h offset 70h reset 1h Figure 2 1892 Register 70h 7 6 5 4 3 2 1 0 FB_DDC_NYQ_CONFIG R W 1h LEGEND R W Read Write W...

Page 863: ...equency control word FCW for nco0 The System Configuration Macros automatically configure this 2 14 12 Register A2h offset A2h reset 0h Figure 2 1895 Register A2h 7 6 5 4 3 2 1 0 FB_DDC_NCO0_FCW 23 16 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1909 Register A2 Field Descriptions Bit Field Type Reset Description 7 0 FB_DDC_NCO0_F CW 23 16 R W 0h Frequency control word FCW...

Page 864: ...CO1_FCW 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1912 Register A5 Field Descriptions Bit Field Type Reset Description 7 0 FB_DDC_NCO1_F CW 15 8 R W 0h Frequency control word FCW for nco1 The System Configuration Macros automatically configure this 2 14 16 Register A6h offset A6h reset 0h Figure 2 1899 Register A6h 7 6 5 4 3 2 1 0 FB_DDC_NCO1_FCW 23 16 R W 0h LEGEN...

Page 865: ...requency control word FCW for nco2 The System Configuration Macros automatically configure this 2 14 19 Register A9h offset A9h reset 0h Figure 2 1902 Register A9h 7 6 5 4 3 2 1 0 FB_DDC_NCO2_FCW 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1916 Register A9 Field Descriptions Bit Field Type Reset Description 7 0 FB_DDC_NCO2_F CW 15 8 R W 0h Frequency control word FCW ...

Page 866: ...DC_NCO3_FCW 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1919 Register AC Field Descriptions Bit Field Type Reset Description 7 0 FB_DDC_NCO3_F CW 7 0 R W 0h Frequency control word FCW for nco3 The System Configuration Macros automatically configure this 2 14 23 Register ADh offset ADh reset 0h Figure 2 1906 Register ADh 7 6 5 4 3 2 1 0 FB_DDC_NCO3_FCW 15 8 R W 0h LEGE...

Page 867: ...ld Type Reset Description 7 0 FB_DDC_NCO3_F CW 31 24 R W 0h Frequency control word FCW for nco3 The System Configuration Macros automatically configure this 2 14 26 Register E0h offset E0h reset 0h Figure 2 1909 Register E0h 7 6 5 4 3 2 1 0 FB_DDC_NCO0_PHASE_OFFSET 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1923 Register E0 Field Descriptions Bit Field Type Reset Des...

Page 868: ...h 7 6 5 4 3 2 1 0 FB_DDC_NCO1_PHASE_OFFSET 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1926 Register E3 Field Descriptions Bit Field Type Reset Description 7 0 FB_DDC_NCO1_P HASE_OFFSET 15 8 R W 0h Offset phase for nco1 2 14 30 Register E4h offset E4h reset 0h Figure 2 1913 Register E4h 7 6 5 4 3 2 1 0 FB_DDC_NCO2_PHASE_OFFSET 7 0 R W 0h LEGEND R W Read Write W Write...

Page 869: ...t 0h Figure 2 1916 Register E7h 7 6 5 4 3 2 1 0 FB_DDC_NCO3_PHASE_OFFSET 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1930 Register E7 Field Descriptions Bit Field Type Reset Description 7 0 FB_DDC_NCO3_P HASE_OFFSET 15 8 R W 0h Offset phase for nco3 2 14 34 Register 100h offset 100h reset 0h Figure 2 1917 Register 100h 7 6 5 4 3 2 1 0 FB_DDC_NCO0_FMULT 7 0 R W 0h LEG...

Page 870: ...1 16 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1933 Register 102 Field Descriptions Bit Field Type Reset Description 5 0 FB_DDC_NCO0_F MULT 21 16 R W 0h Frequency shift corresponding to the fcw of nco0 expressed in kHz modulo Fadc 16 Value programmed here should correspond to the nco0 fcw and should be a value between 0 and Fadc 16 The System Configuration Macros automa...

Page 871: ...1 16 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1936 Register 106 Field Descriptions Bit Field Type Reset Description 5 0 FB_DDC_NCO1_F MULT 21 16 R W 0h Frequency shift corresponding to the fcw of nco1 expressed in kHz modulo Fadc 16 Value programmed here should correspond to the nco0 fcw and should be a value between 0 and Fadc 16 The System Configuration Macros automa...

Page 872: ...1 16 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1939 Register 10A Field Descriptions Bit Field Type Reset Description 5 0 FB_DDC_NCO2_F MULT 21 16 R W 0h Frequency shift corresponding to the fcw of nco2 expressed in kHz modulo Fadc 16 Value programmed here should correspond to the nco0 fcw and should be a value between 0 and Fadc 16 The System Configuration Macros automa...

Page 873: ...Register 10Eh 7 6 5 4 3 2 1 0 FB_DDC_NCO3_FMULT 21 16 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1942 Register 10E Field Descriptions Bit Field Type Reset Description 5 0 FB_DDC_NCO3_F MULT 21 16 R W 0h Frequency shift corresponding to the fcw of nco3 expressed in kHz modulo Fadc 16 Value programmed here should correspond to the nco0 fcw and should be a value between 0 a...

Page 874: ...ter 142h 7 6 5 4 3 2 1 0 FB_DDC_NCO0_FRAC_FCW_DEN 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1945 Register 142 Field Descriptions Bit Field Type Reset Description 7 0 FB_DDC_NCO0_F RAC_FCW_DEN 7 0 R W 0h Denominator of the fractional fequency control word for nco0 Unsigned number System Configuration macros compute and configure this automatically and hence are stron...

Page 875: ...ister 145h 7 6 5 4 3 2 1 0 FB_DDC_NCO1_FRAC_FCW_NUM 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1948 Register 145 Field Descriptions Bit Field Type Reset Description 7 0 FB_DDC_NCO1_F RAC_FCW_NUM 1 5 8 R W 0h Numerator of the fractional fequency control word for nco1 Signed number System Configuration macros compute and configure this automatically and hence are stro...

Page 876: ...937 Register 148h 7 6 5 4 3 2 1 0 FB_DDC_NCO2_FRAC_FCW_NUM 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1951 Register 148 Field Descriptions Bit Field Type Reset Description 7 0 FB_DDC_NCO2_F RAC_FCW_NUM 7 0 R W 0h Numerator of the fractional fequency control word for nco2 Signed number System Configuration macros compute and configure this automatically and hence are ...

Page 877: ...egister 14Bh 7 6 5 4 3 2 1 0 FB_DDC_NCO2_FRAC_FCW_DEN 15 8 R W 2Dh LEGEND R W Read Write W Write only n value after reset Table 2 1954 Register 14B Field Descriptions Bit Field Type Reset Description 7 0 FB_DDC_NCO2_F RAC_FCW_DEN 1 5 8 R W 2Dh Denominator of the fractional fequency control word for nco2 Unsigned number System Configuration macros compute and configure this automatically and hence ...

Page 878: ...ter 14Eh 7 6 5 4 3 2 1 0 FB_DDC_NCO3_FRAC_FCW_DEN 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1957 Register 14E Field Descriptions Bit Field Type Reset Description 7 0 FB_DDC_NCO3_F RAC_FCW_DEN 7 0 R W 0h Denominator of the fractional fequency control word for nco3 Unsigned number System Configuration macros compute and configure this automatically and hence are stron...

Page 879: ...N FB_AGC_PWR _ATTACK_EN FB_AGC_SMA LL_STEP_DEC AY_EN FB_AGC_BIG_ STEP_DECAY _EN FB_AGC_SMA LL_STEP_ATT ACK_EN FB_AGC_BIG_ STEP_ATTACK _EN R W 0h R W 0h R W 0h R W 0h R W 1h R W 0h R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1960 Register 400 Field Descriptions Bit Field Type Reset Description 7 7 reserved R W 0h 6 6 reserved R W 0h 5 5 FB_AGC_PWR_D ECAY_EN R W 0h U...

Page 880: ...h 7 6 5 4 3 2 1 0 FB_AGC_EXT_ DVGA_CNTRL _EN FB_AGC_EXT_ LNA_CNTL_EN R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1962 Register 402 Field Descriptions Bit Field Type Reset Description 1 1 FB_AGC_EXT_DV GA_CNTRL_EN R W 0h Indicates whether AGC can control External DVGA or not At any point of time only either LNA or External DVGA can be enabled see rx_agc_ext_lna_cntr...

Page 881: ...l step attack detector enable 0 Disable 1 Enable 0 0 FB_AGC_BIG_STE P_ATTACK_DET_ EN R W 0h Big step attack detector enable 0 Disable 1 Enable 2 14 67 Register 405h offset 405h reset 0h Figure 2 1950 Register 405h 7 6 5 4 3 2 1 0 FB_AGC_LNA_ RF_ATTACK_D ET_EN R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1964 Register 405 Field Descriptions Bit Field Type Reset Description ...

Page 882: ...C_BIG_STEP_DECAY_STEP_SIZE R W 6h LEGEND R W Read Write W Write only n value after reset Table 2 1967 Register 40A Field Descriptions Bit Field Type Reset Description 5 0 FB_AGC_BIG_STE P_DECAY_STEP_ SIZE R W 6h Gain step when Digital big step decay is triggered 0 5 dB step size 2 14 71 Register 40Bh offset 40Bh reset 2h Figure 2 1954 Register 40Bh 7 6 5 4 3 2 1 0 FB_AGC_SMALL_STEP_DECAY_STEP_SIZE...

Page 883: ..._STEP_SIZE R W 2h Gain step when Digital power detector decay is triggered 0 5 dB step size 2 14 74 Register 410h offset 410h reset Ch Figure 2 1957 Register 410h 7 6 5 4 3 2 1 0 FB_AGC_LNARF_ATTACK_STEP_SIZE R W Ch LEGEND R W Read Write W Write only n value after reset Table 2 1971 Register 410 Field Descriptions Bit Field Type Reset Description 5 0 FB_AGC_LNARF_ ATTACK_STEP_SI ZE R W Ch Gain ste...

Page 884: ..._WIN_LEN 23 16 R W 40h LEGEND R W Read Write W Write only n value after reset Table 2 1974 Register 416 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BIG_STE P_ATTACK_WIN_L EN 23 16 R W 40h Digital big step attack det window length Max supported length is 2 24 2 2 14 78 Register 418h offset 418h reset 0h Figure 2 1961 Register 418h 7 6 5 4 3 2 1 0 FB_AGC_SMALL_STEP_ATTACK_WIN_LEN ...

Page 885: ...W IN_LEN 23 16 R W 40h Digital small step attack det window length Max supported length is 2 24 2 2 14 81 Register 41Ch offset 41Ch reset 0h Figure 2 1964 Register 41Ch 7 6 5 4 3 2 1 0 FB_AGC_BIG_STEP_DECAY_WIN_LEN 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1978 Register 41C Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BIG_STE P_DECAY_WIN_L EN 7 0 R...

Page 886: ...Y_WIN_LEN 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 1981 Register 420 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_SMALL_ STEP_DECAY_WI N_LEN 7 0 R W 0h Digital small step decay det window length Max supported length is 2 24 2 2 14 85 Register 421h offset 421h reset 80h Figure 2 1968 Register 421h 7 6 5 4 3 2 1 0 FB_AGC_SMALL_STEP_DECAY_WIN_LEN 15 ...

Page 887: ...window length used is 2 power programmed value Max supported length is 2 23 programmed value 23 2 14 88 Register 425h offset 425h reset Fh Figure 2 1971 Register 425h 7 6 5 4 3 2 1 0 FB_AGC_PWRDET_DECAY_WIN_LEN R W Fh LEGEND R W Read Write W Write only n value after reset Table 2 1985 Register 425 Field Descriptions Bit Field Type Reset Description 4 0 FB_AGC_PWRDE T_DECAY_WIN_L EN R W Fh Power de...

Page 888: ...TACK_WIN_LEN 23 16 R W 40h LEGEND R W Read Write W Write only n value after reset Table 2 1988 Register 42A Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_LNA_RF _DET_ATTACK_W IN_LEN 23 16 R W 40h LNA RF attack det window length Max supported length is 2 24 2 2 14 92 Register 42Ch offset 42Ch reset FAh Figure 2 1975 Register 42Ch 7 6 5 4 3 2 1 0 FB_AGC_BIG_STEP_ATTACK_SIG_TH 7 0 R ...

Page 889: ...0 R W CBh Signal threshold for digital small step attack detector in 0 12 unsigned format 2 14 95 Register 431h offset 431h reset 6h Figure 2 1978 Register 431h 7 6 5 4 3 2 1 0 FB_AGC_SMALL_STEP_ATTACK_SIG_TH 11 8 R W 6h LEGEND R W Read Write W Write only n value after reset Table 2 1992 Register 431 Field Descriptions Bit Field Type Reset Description 3 0 FB_AGC_SMALL_ STEP_ATTACK_SI G_TH 11 8 R W...

Page 890: ...AY_SIG_TH 7 0 R W 65h LEGEND R W Read Write W Write only n value after reset Table 2 1995 Register 438 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_SMALL_ STEP_DECAY_SI G_TH 7 0 R W 65h Signal threshold for digital small step decay detector in 0 12 unsigned format 2 14 99 Register 439h offset 439h reset Fh Figure 2 1982 Register 439h 7 6 5 4 3 2 1 0 FB_AGC_SMALL_STEP_DECAY_SIG_TH...

Page 891: ...at Power threshold in dB will be 10 log Th 2 16 A full scale sine wave corresponds to 3 dB power 2 14 102 Register 43Eh offset 43Eh reset 4h Figure 2 1985 Register 43Eh 7 6 5 4 3 2 1 0 FB_AGC_PWR_DET_DECAY_TH 7 0 R W 4h LEGEND R W Read Write W Write only n value after reset Table 2 1999 Register 43E Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_PWR_D ET_DECAY_TH 7 0 R W 4h Thresho...

Page 892: ...ATTACK_NUM_HITS 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2002 Register 451 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BIG_STE P_ATTACK_NUM_ HITS 15 8 R W 0h Number of Hits threshold for digital big step attack detector 2 14 106 Register 452h offset 452h reset 8h Figure 2 1989 Register 452h 7 6 5 4 3 2 1 0 FB_AGC_BIG_STEP_ATTACK_NUM_HITS 23 16 R...

Page 893: ...ACK_N UM_HITS 15 8 R W 0h Number of Hits threshold for digital small step attack detector 2 14 109 Register 456h offset 456h reset 8h Figure 2 1992 Register 456h 7 6 5 4 3 2 1 0 FB_AGC_SMALL_STEP_ATTACK_NUM_HITS 23 16 R W 8h LEGEND R W Read Write W Write only n value after reset Table 2 2006 Register 456 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_SMALL_ STEP_ATTACK_N UM_HITS 23...

Page 894: ..._DECAY_NUM_HITS 23 16 R W 8h LEGEND R W Read Write W Write only n value after reset Table 2 2009 Register 45A Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BIG_STE P_DECAY_NUM_H ITS 23 16 R W 8h Number of Hits threshold for digital big step decay detector 2 14 113 Register 45Ch offset 45Ch reset 0h Figure 2 1996 Register 45Ch 7 6 5 4 3 2 1 0 FB_AGC_SMALL_STEP_DECAY_NUM_HITS 7 0 R ...

Page 895: ...p decay detector 2 14 116 Register 460h offset 460h reset 0h Figure 2 1999 Register 460h 7 6 5 4 3 2 1 0 FB_AGC_LNA_RF_DET_ATTACK_NUM_HITS 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2013 Register 460 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_LNA_RF _DET_ATTACK_N UM_HITS 7 0 R W 0h LNA RF attack det threshold If Number of hits is greater than this...

Page 896: ... W 8h LEGEND R W Read Write W Write only n value after reset Table 2 2016 Register 463 Field Descriptions Bit Field Type Reset Description 3 0 FB_AGC_LNA_RF _DET_ATTACK_N UM_HITS 27 24 R W 8h LNA RF attack det threshold If Number of hits is greater than this detector is triggered Note that per clock we may get up to 8 hits 2 14 120 Register 498h offset 498h reset 2h Figure 2 2003 Register 498h 7 6...

Page 897: ...able 2 14 122 Register 49Ah offset 49Ah reset 0h Figure 2 2005 Register 49Ah 7 6 5 4 3 2 1 0 FB_AGC_FRE EZE R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2019 Register 49A Field Descriptions Bit Field Type Reset Description 0 0 FB_AGC_FREEZE R W 0h Freeze AGC 0 Disable 1 Enable 2 14 123 Register 49Ch offset 49Ch reset 0h Figure 2 2006 Register 49Ch 7 6 5 4 3 2 1 0 FB_AGC_DE...

Page 898: ...END R W Read Write W Write only n value after reset Table 2 2022 Register 49E Field Descriptions Bit Field Type Reset Description 0 0 FB_AGC_DEF_LN A_BYP_VAL_B1 R W 0h Default LNA bypass value for Band1 Applicable only if rx_agc_dualband_en is made high 2 14 126 Register 49Fh offset 49Fh reset 0h Figure 2 2009 Register 49Fh 7 6 5 4 3 2 1 0 FB_AGC_DEF_DVGA_ATTN R W 0h LEGEND R W Read Write W Write ...

Page 899: ...scription 5 0 FB_AGC_MIN_AT TN R W 0h Min attenuation DSA can go to Resolution is 0 5 dB 2 14 129 Register 4A2h offset 4A2h reset 3Eh Figure 2 2012 Register 4A2h 7 6 5 4 3 2 1 0 FB_AGC_MAX_DVGA_ATTN R W 3Eh LEGEND R W Read Write W Write only n value after reset Table 2 2026 Register 4A2 Field Descriptions Bit Field Type Reset Description 5 0 FB_AGC_MAX_DV GA_ATTN R W 3Eh Max attn Ext DVGA can go t...

Page 900: ...they carry over the previous state 0 0 FB_AGC_ATTACK _DETS_RESET_A T_RX_ON R W 0h If enabled Attack detectors get reset during RX OFF and Gain Swap with default state else they carry over the previous state 2 14 132 Register 4A6h offset 4A6h reset 1h Figure 2 2015 Register 4A6h 7 6 5 4 3 2 1 0 FB_AGC_RES ET_DETS_GAI N_CHANGE R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 202...

Page 901: ...able 2 2032 Register 4AA Field Descriptions Bit Field Type Reset Description 5 0 FB_AGC_EXT_LN A_GAIN_MARGIN R W Ch LNA gain margin to be used for reenabling the LNA Provides additional hysterisis on top of the attack and decay hysterisis Resolution in 0 5 dB 2 14 136 Register 4ACh offset 4ACh reset 40h Figure 2 2019 Register 4ACh 7 6 5 4 3 2 1 0 FB_AGC_PIN_1_SELECT_BITS 7 0 R W 40h LEGEND R W Rea...

Page 902: ... Dig pwr attack Bit 2 Dig pwr decay Bit 1 Absolute reliability Bit 0 Relative reliability 2 14 138 Register 4AEh offset 4AEh reset 40h Figure 2 2021 Register 4AEh 7 6 5 4 3 2 1 0 FB_AGC_PIN_2_SELECT_BITS 7 0 R W 40h LEGEND R W Read Write W Write only n value after reset Table 2 2035 Register 4AE Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_PIN_2_S ELECT_BITS 7 0 R W 40h Each bit ...

Page 903: ...on 7 0 FB_AGC_PIN_3_S ELECT_BITS 7 0 R W 40h Each bit corresponds to one particular detector which should be used for peak detector 3 Bit 14 Dig OVR Bit 13 Reserved Bit 12 Reserved Bit 11 LNARF det Bit 10 Reserved Bit 9 Reserved Bit 8 reserved Bit 7 Dig bigstep attack Bit 6 Dig small step attack Bit 5 Bigstep decay Bit 4 Small step decay Bit 3 Dig pwr attack Bit 2 Dig pwr decay Bit 1 Absolute reli...

Page 904: ...ure 2 2026 Register 4B3h 7 6 5 4 3 2 1 0 FB_AGC_PIN_4_SELECT_BITS 15 8 R W 10h LEGEND R W Read Write W Write only n value after reset Table 2 2040 Register 4B3 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_PIN_4_S ELECT_BITS 15 8 R W 10h Each bit corresponds to one particular detector which should be used for peak detector 4 Bit 14 Dig OVR Bit 13 Reserved Bit 12 Reserved Bit 11 LN...

Page 905: ..._PULSE_EXPANSION_COUNT 7 0 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2043 Register 4B6 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_PULSE_ EXPANSION_COU NT 7 0 R W 1h Number of clock cycles in terms of Fs 8 by which a high one should be extended before being sent on the pins 2 14 147 Register 4B7h offset 4B7h reset 0h Figure 2 2030 Register 4B7h 7 6 5 ...

Page 906: ... dB should be lower than internal DSA Range 2 14 150 Register 4BDh offset 4BDh reset 0h Figure 2 2033 Register 4BDh 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_GAIN0 10 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2047 Register 4BD Field Descriptions Bit Field Type Reset Description 2 0 FB_AGC_BAND0_ LNA_GAIN0 10 8 R W 0h LNA Gain for Band0 for temp index 0 in case of External LNA ...

Page 907: ... W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2050 Register 4C0 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BAND0_ LNA_GAIN2 7 0 R W 0h LNA Gain for Band0 for temp index 2 in case of External LNA Control Gain for DVGA Index 2 in case of External DVGA control 2 14 154 Register 4C1h offset 4C1h reset 0h Figure 2 2037 Register 4C1h 7 6 5 4 3 2 1 0 FB_AGC_BAND...

Page 908: ...ex 3 in case of External LNA Control Gain for DVGA Index 3 in case of External DVGA control 2 14 157 Register 4C4h offset 4C4h reset 0h Figure 2 2040 Register 4C4h 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_GAIN4 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2054 Register 4C4 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BAND0_ LNA_GAIN4 7 0 R W 0h LNA Gain for B...

Page 909: ...W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2057 Register 4C7 Field Descriptions Bit Field Type Reset Description 2 0 FB_AGC_BAND0_ LNA_GAIN5 10 8 R W 0h LNA Gain for Band0 for temp index 5 in case of External LNA Control Gain for DVGA Index 5 in case of External DVGA control 2 14 161 Register 4C8h offset 4C8h reset 0h Figure 2 2044 Register 4C8h 7 6 5 4 3 2 1 0 FB_AGC_BAND...

Page 910: ...ex 7 in case of External LNA Control Gain for DVGA Index 7 in case of External DVGA control 2 14 164 Register 4CBh offset 4CBh reset 0h Figure 2 2047 Register 4CBh 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_GAIN7 10 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2061 Register 4CB Field Descriptions Bit Field Type Reset Description 2 0 FB_AGC_BAND0_ LNA_GAIN7 10 8 R W 0h LNA Gain for...

Page 911: ...W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2064 Register 4CE Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BAND0_ LNA_GAIN9 7 0 R W 0h LNA Gain for Band0 for temp index 9 in case of External LNA Control Gain for DVGA Index 9 in case of External DVGA control 2 14 168 Register 4CFh offset 4CFh reset 0h Figure 2 2051 Register 4CFh 7 6 5 4 3 2 1 0 FB_AGC_BAND0...

Page 912: ... 10 in case of External LNA Control Gain for DVGA Index 10 in case of External DVGA control 2 14 171 Register 4D2h offset 4D2h reset 0h Figure 2 2054 Register 4D2h 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_GAIN11 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2068 Register 4D2 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BAND0_ LNA_GAIN11 7 0 R W 0h LNA Gain for...

Page 913: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 2071 Register 4D5 Field Descriptions Bit Field Type Reset Description 2 0 FB_AGC_BAND0_ LNA_GAIN12 10 8 R W 0h LNA Gain for Band0 for temp index 12 in case of External LNA Control Gain for DVGA Index 12 in case of External DVGA control 2 14 175 Register 4D6h offset 4D6h reset 0h Figure 2 2058 Register 4D6h 7 6 5 4 3 2 1 0 FB_AGC_BA...

Page 914: ...14 in case of External LNA Control Gain for DVGA Index 14 in case of External DVGA control 2 14 178 Register 4D9h offset 4D9h reset 0h Figure 2 2061 Register 4D9h 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_GAIN14 10 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2075 Register 4D9 Field Descriptions Bit Field Type Reset Description 2 0 FB_AGC_BAND0_ LNA_GAIN14 10 8 R W 0h LNA Gain fo...

Page 915: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 2078 Register 4DC Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BAND0_ LNA_GAIN16 7 0 R W 0h LNA Gain for Band0 for temp index 16 in case of External LNA Control Gain for DVGA Index 16 in case of External DVGA control 2 14 182 Register 4DDh offset 4DDh reset 0h Figure 2 2065 Register 4DDh 7 6 5 4 3 2 1 0 FB_AGC_BAN...

Page 916: ... 17 in case of External LNA Control Gain for DVGA Index 17 in case of External DVGA control 2 14 185 Register 4E0h offset 4E0h reset 0h Figure 2 2068 Register 4E0h 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_GAIN18 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2082 Register 4E0 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BAND0_ LNA_GAIN18 7 0 R W 0h LNA Gain for...

Page 917: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 2085 Register 4E3 Field Descriptions Bit Field Type Reset Description 2 0 FB_AGC_BAND0_ LNA_GAIN19 10 8 R W 0h LNA Gain for Band0 for temp index 19 in case of External LNA Control Gain for DVGA Index 19 in case of External DVGA control 2 14 189 Register 4E4h offset 4E4h reset 0h Figure 2 2072 Register 4E4h 7 6 5 4 3 2 1 0 FB_AGC_BA...

Page 918: ...21 in case of External LNA Control Gain for DVGA Index 21 in case of External DVGA control 2 14 192 Register 4E7h offset 4E7h reset 0h Figure 2 2075 Register 4E7h 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_GAIN21 10 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2089 Register 4E7 Field Descriptions Bit Field Type Reset Description 2 0 FB_AGC_BAND0_ LNA_GAIN21 10 8 R W 0h LNA Gain fo...

Page 919: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 2092 Register 4EA Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BAND0_ LNA_GAIN23 7 0 R W 0h LNA Gain for Band0 for temp index 23 in case of External LNA Control Gain for DVGA Index 23 in case of External DVGA control 2 14 196 Register 4EBh offset 4EBh reset 0h Figure 2 2079 Register 4EBh 7 6 5 4 3 2 1 0 FB_AGC_BAN...

Page 920: ... 24 in case of External LNA Control Gain for DVGA Index 24 in case of External DVGA control 2 14 199 Register 4EEh offset 4EEh reset 0h Figure 2 2082 Register 4EEh 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_GAIN25 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2096 Register 4EE Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BAND0_ LNA_GAIN25 7 0 R W 0h LNA Gain for...

Page 921: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 2099 Register 4F1 Field Descriptions Bit Field Type Reset Description 2 0 FB_AGC_BAND0_ LNA_GAIN26 10 8 R W 0h LNA Gain for Band0 for temp index 26 in case of External LNA Control Gain for DVGA Index 26 in case of External DVGA control 2 14 203 Register 4F2h offset 4F2h reset 0h Figure 2 2086 Register 4F2h 7 6 5 4 3 2 1 0 FB_AGC_BA...

Page 922: ...28 in case of External LNA Control Gain for DVGA Index 28 in case of External DVGA control 2 14 206 Register 4F5h offset 4F5h reset 0h Figure 2 2089 Register 4F5h 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_GAIN28 10 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2103 Register 4F5 Field Descriptions Bit Field Type Reset Description 2 0 FB_AGC_BAND0_ LNA_GAIN28 10 8 R W 0h LNA Gain fo...

Page 923: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 2106 Register 4F8 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BAND0_ LNA_GAIN30 7 0 R W 0h LNA Gain for Band0 for temp index 30 in case of External LNA Control Gain for DVGA Index 30 in case of External DVGA control 2 14 210 Register 4F9h offset 4F9h reset 0h Figure 2 2093 Register 4F9h 7 6 5 4 3 2 1 0 FB_AGC_BAN...

Page 924: ...or DVGA Index 31 in case of External DVGA control 2 14 213 Register 53Ch offset 53Ch reset 0h Figure 2 2096 Register 53Ch 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_PHASE0 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2110 Register 53C Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BAND0_ LNA_PHASE0 7 0 R W 0h LNA Phase for Band0 for temp index 0 in case of Extern...

Page 925: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 2113 Register 53F Field Descriptions Bit Field Type Reset Description 1 0 FB_AGC_BAND0_ LNA_PHASE1 9 8 R W 0h LNA Phase for Band0 for temp index 1 in case of External LNA Control Phase for DVGA Index 1 in case of External DVGA control 2 14 217 Register 540h offset 540h reset 0h Figure 2 2100 Register 540h 7 6 5 4 3 2 1 0 FB_AGC_BAN...

Page 926: ...x 3 in case of External LNA Control Phase for DVGA Index 3 in case of External DVGA control 2 14 220 Register 543h offset 543h reset 0h Figure 2 2103 Register 543h 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_PHASE3 9 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2117 Register 543 Field Descriptions Bit Field Type Reset Description 1 0 FB_AGC_BAND0_ LNA_PHASE3 9 8 R W 0h LNA Phase fo...

Page 927: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 2120 Register 546 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BAND0_ LNA_PHASE5 7 0 R W 0h LNA Phase for Band0 for temp index 5 in case of External LNA Control Phase for DVGA Index 5 in case of External DVGA control 2 14 224 Register 547h offset 547h reset 0h Figure 2 2107 Register 547h 7 6 5 4 3 2 1 0 FB_AGC_BAN...

Page 928: ...x 6 in case of External LNA Control Phase for DVGA Index 6 in case of External DVGA control 2 14 227 Register 54Ah offset 54Ah reset 0h Figure 2 2110 Register 54Ah 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_PHASE7 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2124 Register 54A Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BAND0_ LNA_PHASE7 7 0 R W 0h LNA Phase fo...

Page 929: ... 0h LEGEND R W Read Write W Write only n value after reset Table 2 2127 Register 54D Field Descriptions Bit Field Type Reset Description 1 0 FB_AGC_BAND0_ LNA_PHASE8 9 8 R W 0h LNA Phase for Band0 for temp index 8 in case of External LNA Control Phase for DVGA Index 8 in case of External DVGA control 2 14 231 Register 54Eh offset 54Eh reset 0h Figure 2 2114 Register 54Eh 7 6 5 4 3 2 1 0 FB_AGC_BAN...

Page 930: ...in case of External LNA Control Phase for DVGA Index 10 in case of External DVGA control 2 14 234 Register 551h offset 551h reset 0h Figure 2 2117 Register 551h 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_PHASE1 0 9 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2131 Register 551 Field Descriptions Bit Field Type Reset Description 1 0 FB_AGC_BAND0_ LNA_PHASE10 9 8 R W 0h LNA Phase fo...

Page 931: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 2134 Register 554 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BAND0_ LNA_PHASE12 7 0 R W 0h LNA Phase for Band0 for temp index 12 in case of External LNA Control Phase for DVGA Index 12 in case of External DVGA control 2 14 238 Register 555h offset 555h reset 0h Figure 2 2121 Register 555h 7 6 5 4 3 2 1 0 FB_AGC_B...

Page 932: ...3 in case of External LNA Control Phase for DVGA Index 13 in case of External DVGA control 2 14 241 Register 558h offset 558h reset 0h Figure 2 2124 Register 558h 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_PHASE14 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2138 Register 558 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BAND0_ LNA_PHASE14 7 0 R W 0h LNA Phase f...

Page 933: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 2141 Register 55B Field Descriptions Bit Field Type Reset Description 1 0 FB_AGC_BAND0_ LNA_PHASE15 9 8 R W 0h LNA Phase for Band0 for temp index 15 in case of External LNA Control Phase for DVGA Index 15 in case of External DVGA control 2 14 245 Register 55Ch offset 55Ch reset 0h Figure 2 2128 Register 55Ch 7 6 5 4 3 2 1 0 FB_AGC_B...

Page 934: ...7 in case of External LNA Control Phase for DVGA Index 17 in case of External DVGA control 2 14 248 Register 55Fh offset 55Fh reset 0h Figure 2 2131 Register 55Fh 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_PHASE1 7 9 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2145 Register 55F Field Descriptions Bit Field Type Reset Description 1 0 FB_AGC_BAND0_ LNA_PHASE17 9 8 R W 0h LNA Phase ...

Page 935: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 2148 Register 562 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BAND0_ LNA_PHASE19 7 0 R W 0h LNA Phase for Band0 for temp index 19 in case of External LNA Control Phase for DVGA Index 19 in case of External DVGA control 2 14 252 Register 563h offset 563h reset 0h Figure 2 2135 Register 563h 7 6 5 4 3 2 1 0 FB_AGC_B...

Page 936: ...0 in case of External LNA Control Phase for DVGA Index 20 in case of External DVGA control 2 14 255 Register 566h offset 566h reset 0h Figure 2 2138 Register 566h 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_PHASE21 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2152 Register 566 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BAND0_ LNA_PHASE21 7 0 R W 0h LNA Phase f...

Page 937: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 2155 Register 569 Field Descriptions Bit Field Type Reset Description 1 0 FB_AGC_BAND0_ LNA_PHASE22 9 8 R W 0h LNA Phase for Band0 for temp index 22 in case of External LNA Control Phase for DVGA Index 22 in case of External DVGA control 2 14 259 Register 56Ah offset 56Ah reset 0h Figure 2 2142 Register 56Ah 7 6 5 4 3 2 1 0 FB_AGC_B...

Page 938: ...4 in case of External LNA Control Phase for DVGA Index 24 in case of External DVGA control 2 14 262 Register 56Dh offset 56Dh reset 0h Figure 2 2145 Register 56Dh 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_PHASE2 4 9 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2159 Register 56D Field Descriptions Bit Field Type Reset Description 1 0 FB_AGC_BAND0_ LNA_PHASE24 9 8 R W 0h LNA Phase ...

Page 939: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 2162 Register 570 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BAND0_ LNA_PHASE26 7 0 R W 0h LNA Phase for Band0 for temp index 26 in case of External LNA Control Phase for DVGA Index 26 in case of External DVGA control 2 14 266 Register 571h offset 571h reset 0h Figure 2 2149 Register 571h 7 6 5 4 3 2 1 0 FB_AGC_B...

Page 940: ...7 in case of External LNA Control Phase for DVGA Index 27 in case of External DVGA control 2 14 269 Register 574h offset 574h reset 0h Figure 2 2152 Register 574h 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_PHASE28 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2166 Register 574 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_BAND0_ LNA_PHASE28 7 0 R W 0h LNA Phase f...

Page 941: ...0h LEGEND R W Read Write W Write only n value after reset Table 2 2169 Register 577 Field Descriptions Bit Field Type Reset Description 1 0 FB_AGC_BAND0_ LNA_PHASE29 9 8 R W 0h LNA Phase for Band0 for temp index 29 in case of External LNA Control Phase for DVGA Index 29 in case of External DVGA control 2 14 273 Register 578h offset 578h reset 0h Figure 2 2156 Register 578h 7 6 5 4 3 2 1 0 FB_AGC_B...

Page 942: ...index 31 in case of External LNA Control Phase for DVGA Index 31 in case of External DVGA control 2 14 276 Register 57Bh offset 57Bh reset 0h Figure 2 2159 Register 57Bh 7 6 5 4 3 2 1 0 FB_AGC_BAND0_LNA_PHASE3 1 9 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2173 Register 57B Field Descriptions Bit Field Type Reset Description 1 0 FB_AGC_BAND0_ LNA_PHASE31 9 8 R W 0h LNA...

Page 943: ...ster 5C1h 7 6 5 4 3 2 1 0 FB_AGC_CLK_DIV_FACTOR_DVGA_CTRL 10 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2176 Register 5C1 Field Descriptions Bit Field Type Reset Description 2 0 FB_AGC_CLK_DIV _FACTOR_DVGA_ CTRL 10 8 R W 0h Clock divide factor for external DVGA control module This factor is used to derive the SPI clock when the device is acting as a master to control e...

Page 944: ...Write W Write only n value after reset Table 2 2179 Register 5D0 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_AVG_P WR_DET_SEEN 7 0 R 0h Indicates average power seen by the power detector Based on pwr_det_read_sel corresponding power detector is selected Update pulse needs to be provided for reading this Power read will be equal to 10 log value read 65535 2 14 283 Register 5D1h o...

Page 945: ...B_AGC_DIG_DET_NUM_HITS_SEEN 15 8 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2182 Register 5D5 Field Descriptions Bit Field Type Reset Description 7 0 FB_AGC_DIG_DE T_NUM_HITS_SE EN 15 8 R 0h Indicates Number of Hits observed Based on dig_det_read_sel the corresponding digital peak detector status is read This will get updated only when update pulse is given Running accum m...

Page 946: ... Read Write W Write only n value after reset Table 2 2185 Register 5E0 Field Descriptions Bit Field Type Reset Description 0 0 FB_AGC_RESTAR T_MAX_MIN R W 0h Resetting statistics module When Set to zero and set to one reset all the statistics and start again That is reset rx_agc_max_attn_used rx_agc_min_attn_used to rx_agc_curr_attn Reset rx_agc_max_dvga_attn_used rx_agc_min_dvga_attn_used to rx_a...

Page 947: ...ED R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2188 Register 5E6 Field Descriptions Bit Field Type Reset Description 5 0 FB_AGC_MAX_DV GA_ATTN_USED R 0h Max dvga attn seen by stat module This is in 0 5 dB resolution 2 14 292 Register 5E7h offset 5E7h reset 0h Figure 2 2175 Register 5E7h 7 6 5 4 3 2 1 0 FB_AGC_MIN_DVGA_ATTN_USED R 0h LEGEND R W Read Write W Write only n valu...

Page 948: ... 2191 Register 5E9 Field Descriptions Bit Field Type Reset Description 5 0 FB_AGC_CURR_A TTN R 0h DSA attn read out This is in 0 5 dB resolution 2 14 295 Register 5EAh offset 5EAh reset 0h Figure 2 2178 Register 5EAh 7 6 5 4 3 2 1 0 FB_AGC_STAT _SIGNAL_OOB FB_AGC_ATT N_CHANGED reserved FB_AGC_BAN D0_LNA_BYPA SS_CHANGED R 0h R 0h R 0h R 0h LEGEND R W Read Write W Write only n value after reset Tabl...

Page 949: ...LNA is enabled 2 14 297 Register 634h offset 634h reset 0h Figure 2 2180 Register 634h 7 6 5 4 3 2 1 0 FB_ALC_CLK_ EN FB_ALC_ENAB LE R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2194 Register 634 Field Descriptions Bit Field Type Reset Description 1 1 FB_ALC_CLK_EN R W 0h clock enable for ALC module Need to be set along with enable_alc 0 Disable 1 Enable 0 0 FB_ALC_...

Page 950: ...egister 636 Field Descriptions Bit Field Type Reset Description 1 1 FB_ALC_USE_LS B_PLUS_ONE_BIT _FOR_CONTROL R W 0h Enables the penultimate LSB bit to be used for control information so that Peak detector output can be sent on it the LSB position is dependent on 12bit or 16bit mode of operation accordingly Penultimate LSB of I contains detector selected by rx_agc_pin_3_select_bits Penultimate LSB...

Page 951: ...be supported by DGC Total Gain Compensation is saturated to this value Allowable range is 0 to 66 dB in steps of 1 dB 2 14 302 Register 639h offset 639h reset 0h Figure 2 2185 Register 639h 7 6 5 4 3 2 1 0 FB_ALC_SIG_BACKOFF_DB R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2199 Register 639 Field Descriptions Bit Field Type Reset Description 4 0 FB_ALC_SIG_BAC KOFF_DB R W 0...

Page 952: ...1 reserved 2 2 bits Used for DGC mode 2 3 4 3 3 bits Used for DGC modes 2 4 4 4 bits Used only in DGC mode 3 5 reserved 6 reserved 7 reserved 2 14 305 Register 63Dh offset 63Dh reset 0h Figure 2 2188 Register 63Dh 7 6 5 4 3 2 1 0 FB_ALC_COA RSE_INDEX_S WAP_IQ FB_ALC_COA RSE_INDEX_I NVERT R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2202 Register 63D Field Descriptio...

Page 953: ...Figure 2 2190 Register 640h 7 6 5 4 3 2 1 0 FB_ALC_OUTPUT_PIN_DELAY 7 0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2204 Register 640 Field Descriptions Bit Field Type Reset Description 7 0 FB_ALC_OUTPUT _PIN_DELAY 7 0 R W 0h Delay in fs 8 clocks imparted on the ALC output pins This can be used by the customer to match the ALC pin information with latency of the data thro...

Page 954: ...0 FB_ALC_EXP_OF FSET_INPUT_ALC _FORCE R W 0h Used in Input ALC mode 0 Automatic computation 1 Use the force value for exponent 2 14 311 Register 645h offset 645h reset 0h Figure 2 2194 Register 645h 7 6 5 4 3 2 1 0 FB_ALC_EXP_OFFSET_INPUT_ALC_FORCE_VAL R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2208 Register 645 Field Descriptions Bit Field Type Reset Description 4 0 FB_...

Page 955: ...h LEGEND R W Read Write W Write only n value after reset Table 2 2211 Register 64A Field Descriptions Bit Field Type Reset Description 0 0 FB_ALC_DISABLE _CF_GAININDEN_ TOT_GAIN_CHAN GE R W 0h 0 Disable 1 Enable 2 14 315 Register 64Ch offset 64Ch reset 0h Figure 2 2198 Register 64Ch 7 6 5 4 3 2 1 0 FB_ALC_USE_ LSB_BIT_FOR _CONTROL_F B FB_ALC_USE_ 12BIT_SEL_FB R W 0h R W 0h LEGEND R W Read Write W ...

Page 956: ... only above this value 2 14 317 Register 712h offset 712h reset 0h Figure 2 2200 Register 712h 7 6 5 4 3 2 1 0 FB_DDC_PROG_DELAY R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2214 Register 712 Field Descriptions Bit Field Type Reset Description 4 0 FB_DDC_PROG_D ELAY R W 0h Programmable delay in ADC clock cycles Valid range 0 through 31 2 14 318 Register 713h offset 713h re...

Page 957: ...6 5 4 3 2 1 0 FB_DDC_USE _RX_ROOT_C LOCK R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2217 Register 741 Field Descriptions Bit Field Type Reset Description 0 0 FB_DDC_USE_RX _ROOT_CLOCK R W 0h Use RX digital root clock for FB Useful when RX and FB ADC rates are the same The System Configuration Macros automatically engage such power savings hooks and are hence strongly rec...

Page 958: ...lock 0 Enable FB PDDC clock 2 14 323 Register 772h offset 772h reset 0h Figure 2 2206 Register 772h 7 6 5 4 3 2 1 0 FB_DDC_DECI M_PDN R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2220 Register 772 Field Descriptions Bit Field Type Reset Description 0 0 FB_DDC_DECIM_ PDN R W 0h Power down the DDC section of FB channel 1 Turn off FB DDC clock 0 Enable FB DDC clock 2 14 324 R...

Page 959: ...X_GAIN_SWAP_B 92h ENABLE_TX_GAIN_SWAP_C 93h ENABLE_TX_GAIN_SWAP_D 94h BROADCAST_S WAP_TX 95h ENABLE_TXDSALATCH 98h BROADCAST_T XNCOSEL 99h TXNCOSEL_MODE_AB 9Ah TXNCOSEL_MODE_CD 9Ch ENABLE_TXNCOSEL_A 9Dh ENABLE_TXNCOSEL_B 9Eh ENABLE_TXNCOSEL_C 9Fh ENABLE_TXNCOSEL_D A0h USE_PER_CH_ RXAB_TDD A1h USE_PER_CH_ RXCD_TDD A2h RXGSWAP_MO DE_AB A3h RXGSWAP_MO DE_CD A4h ENABLE_RX_GAIN_SWAP_A A5h ENABLE_RX_GAI...

Page 960: ...2 2223 Register 80 Field Descriptions Bit Field Type Reset Description 0 0 MODE_2T2R R W 0h mode_2t2r 1 Controls for AB side and CD side are independent mode_2t2r 0 Controls for channel A are broadcast to all 4 channels This control takes effect for both Tx and Rx Enables System normally comes up with this bit 1 2 15 2 Register 81h offset 81h reset 1h Figure 2 2209 Register 81h 7 6 5 4 3 2 1 0 FDD...

Page 961: ...ngs of Rx FbEn to valid settings in conjunction with fields rxa_fb_shr rxb_fb_shr etc Example a RxA and Fb chains are shared When RxEn 1 FbEn 1 we want shared chain to be in Fb mode and non shared chain chB to be in Rx mode This can be achieved by setting rxa_fb_shr 1 rxb_fb_shr 0 and map_invalid_settings to 01 Since rxa_fb_shr 1 map_invalid_settings will take effect of chA and set it in Fb mode a...

Page 962: ... in map_invalid_settings 2 15 7 Register 8Ah offset 8Ah reset 1h Figure 2 2214 Register 8Ah 7 6 5 4 3 2 1 0 RXC_FB_SHR R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2229 Register 8A Field Descriptions Bit Field Type Reset Description 0 0 RXC_FB_SHR R W 1h see description in map_invalid_settings 2 15 8 Register 8Bh offset 8Bh reset 0h Figure 2 2215 Register 8Bh 7 6 5 4 3 2 1...

Page 963: ...l control is not enabled This means that TxEn for chC is also used for chD 2 15 11 Register 8Eh offset 8Eh reset 0h Figure 2 2218 Register 8Eh 7 6 5 4 3 2 1 0 TXGSWAP_M ODE_AB R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2233 Register 8E Field Descriptions Bit Field Type Reset Description 0 0 TXGSWAP_MODE _AB R W 0h If txgswap_mode_ab 0 both chA chB get the same 2 bits for...

Page 964: ...AP_B R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2236 Register 91 Field Descriptions Bit Field Type Reset Description 1 0 ENABLE_TX_GAIN _SWAP_B R W 0h Acts as an EN for txgswap for each bit of chB If a bit of the enable is 0 then the corresponding gain_swap bit will be always 0 2 15 15 Register 92h offset 92h reset 0h Figure 2 2222 Register 92h 7 6 5 4 3 2 1 0 ENABLE_TX_...

Page 965: ... 0h Whether to broadcast tx_gain_swap from AB to CD or not 0 means no broadcast 1 means broadcast 2 15 18 Register 95h offset 95h reset 0h Figure 2 2225 Register 95h 7 6 5 4 3 2 1 0 ENABLE_TXDSALATCH R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2240 Register 95 Field Descriptions Bit Field Type Reset Description 3 0 ENABLE_TXDSAL ATCH R W 0h These bits when set enable txds...

Page 966: ...Ah 7 6 5 4 3 2 1 0 TXNCOSEL_MODE_CD R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2243 Register 9A Field Descriptions Bit Field Type Reset Description 1 0 TXNCOSEL_MOD E_CD R W 0h The 4 bits of NCOSel get routed to both C and D channels according to mode as follow NCOsel for band1 band0 If broadcast_txncosel 1 00 b0 b0 b0 b0 b0 b0 01 b1 b0 b1 b0 b1 b0 02 0 0 b3 b2 b1 b0 03 ...

Page 967: ...ABLE_TXNCOSEL_C R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2246 Register 9E Field Descriptions Bit Field Type Reset Description 5 0 ENABLE_TXNCOS EL_C R W 0h If enable 0 then the corresponding bit in txncosel for that channel is made 0 else ncosel is sent as it is 2 15 25 Register 9Fh offset 9Fh reset 0h Figure 2 2232 Register 9Fh 7 6 5 4 3 2 1 0 ENABLE_TXNCOSEL_D R W 0h...

Page 968: ...t By default per channel control is not enabled 2 15 28 Register A2h offset A2h reset 0h Figure 2 2235 Register A2h 7 6 5 4 3 2 1 0 RXGSWAP_M ODE_AB R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2250 Register A2 Field Descriptions Bit Field Type Reset Description 0 0 RXGSWAP_MODE _AB R W 0h In mode 0 both chA chB get the same 2 bits for the gain swap and in mode1 chA gets b...

Page 969: ...AP_B R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2253 Register A5 Field Descriptions Bit Field Type Reset Description 1 0 ENABLE_RX_GAI N_SWAP_B R W 0h Acts as an EN for rxgswap for each bit of chB If a bit of the enable is 0 then the corresponding gain_swap bit will be always 0 2 15 32 Register A6h offset A6h reset 0h Figure 2 2239 Register A6h 7 6 5 4 3 2 1 0 ENABLE_RX_...

Page 970: ...W 0h Whether to broadcast swap_rx from AB to CD or not 0 means no broadcast 1 means broadcast 2 15 35 Register ACh offset ACh reset 0h Figure 2 2242 Register ACh 7 6 5 4 3 2 1 0 BROADCAST_ RXNCOSEL R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2257 Register AC Field Descriptions Bit Field Type Reset Description 0 0 BROADCAST_RX NCOSEL R W 0h Setting this to 1 broadcasts to ...

Page 971: ...broadcast_rxncosel 0 00 b2 b2 b2 b2 b2 01 b3 b3 b2 b3 b2 02 0 b3 b2 b1 b0 03 0 0 0 0 0 2 15 38 Register B0h offset B0h reset 0h Figure 2 2245 Register B0h 7 6 5 4 3 2 1 0 ENABLE_RXNCOSEL_A R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2260 Register B0 Field Descriptions Bit Field Type Reset Description 4 0 ENABLE_RXNCOS EL_A R W 0h If enable 0 then the corresponding bit in ...

Page 972: ...lue after reset Table 2 2263 Register B3 Field Descriptions Bit Field Type Reset Description 4 0 ENABLE_RXNCOS EL_D R W 0h If enable 0 then the corresponding bit in rxncosel for that channel is made 0 else ncosel is sent as it is 2 15 42 Register B5h offset B5h reset 0h Figure 2 2249 Register B5h 7 6 5 4 3 2 1 0 ENABLE_FB_GAIN_SWAP_AB R W 0h LEGEND R W Read Write W Write only n value after reset T...

Page 973: ...st to both fbs the same 2 bit input ncosel So the modes supported are if broadcast_fbncosel 0 fbAB 0 0 ns1 ns0 fbCD 0 0 ns2 ns1 if broadcast_fbncosel 1 fbAB ns3 ns2 ns1 ns0 fbCD ns3 ns2 ns1 ns0 Other modes may be achieved by using enable_fbncosel and force_fbncosel bits below For example if we want independent single bit control for both fbs then make broadcast_fbncosel 0 and enable_fbncosel_ab cd...

Page 974: ...escription 3 0 ENABLE_FBNCOS EL_AB R W 0h bit mask for the 4 bit fbncosel_ab If a particular bit is not enabled then 0 is sent else the input fbncosel bit is sent 2 15 48 Register BDh offset BDh reset 0h Figure 2 2255 Register BDh 7 6 5 4 3 2 1 0 ENABLE_FBNCOSEL_CD R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2270 Register BD Field Descriptions Bit Field Type Reset Descrip...

Page 975: ...set 0h Figure 2 2258 Register C2h 7 6 5 4 3 2 1 0 CH0_LSB_FBMUXSEL R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2273 Register C2 Field Descriptions Bit Field Type Reset Description 1 0 CH0_LSB_FBMUX SEL R W 0h ch0 used for the fbab in case of dual fbmode 2 15 52 Register C3h offset C3h reset 1h Figure 2 2259 Register C3h 7 6 5 4 3 2 1 0 CH1_LSB_FBMUXSEL R W 1h LEGEND R W R...

Page 976: ...n case of dual fbmode 2 15 55 Register C6h offset C6h reset 0h Figure 2 2262 Register C6h 7 6 5 4 3 2 1 0 OVERRIDE_FBMUXSEL R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2277 Register C6 Field Descriptions Bit Field Type Reset Description 1 0 OVERRIDE_FBMU XSEL R W 0h Control bits which indicate which bits of the FbMuxSel are forced The value for the forced bits are picked ...

Page 977: ...5h IBUF_ST_GPIO_5 216h ODRIV_DS_GPIO_5 218h PULL_CTRL_GPIO_6 219h IBUF_ST_GPIO_6 21Ah ODRIV_DS_GPIO_6 21Ch PULL_CTRL_GPIO_7 21Dh IBUF_ST_GPIO_7 21Eh ODRIV_DS_GPIO_7 220h PULL_CTRL_GPIO_8 221h IBUF_ST_GPIO_8 222h ODRIV_DS_GPIO_8 224h PULL_CTRL_GPIO_9 225h IBUF_ST_GPIO_9 226h ODRIV_DS_GPIO_9 228h PULL_CTRL_GPIO_10 229h IBUF_ST_GPIO_10 22Ah ODRIV_DS_GPIO_10 22Ch PULL_CTRL_GPIO_11 22Dh IBUF_ST_GPIO_11...

Page 978: ... 25Eh ODRIV_DS_GPIO_23 260h PULL_CTRL_GPIO_24 261h IBUF_ST_GPIO_24 262h ODRIV_DS_GPIO_24 264h PULL_CTRL_GPIO_25 265h IBUF_ST_GPIO_25 266h ODRIV_DS_GPIO_25 268h PULL_CTRL_GPIO_26 269h IBUF_ST_GPIO_26 26Ah ODRIV_DS_GPIO_26 26Ch PULL_CTRL_GPIO_27 26Dh IBUF_ST_GPIO_27 26Eh ODRIV_DS_GPIO_27 270h PULL_CTRL_GPIO_28 271h IBUF_ST_GPIO_28 272h ODRIV_DS_GPIO_28 274h PULL_CTRL_GPIO_29 275h IBUF_ST_GPIO_29 276...

Page 979: ...2 2A9h IBUF_ST_GPIO_42 2AAh ODRIV_DS_GPIO_42 2ACh PULL_CTRL_GPIO_43 2ADh IBUF_ST_GPIO_43 2AEh ODRIV_DS_GPIO_43 2B0h PULL_CTRL_GPIO_44 2B1h IBUF_ST_GPIO_44 2B2h ODRIV_DS_GPIO_44 2B4h PULL_CTRL_GPIO_45 2B5h IBUF_ST_GPIO_45 2B6h ODRIV_DS_GPIO_45 2B8h PULL_CTRL_GPIO_46 2B9h IBUF_ST_GPIO_46 2BAh ODRIV_DS_GPIO_46 2BCh PULL_CTRL_GPIO_47 2BDh IBUF_ST_GPIO_47 2BEh ODRIV_DS_GPIO_47 2C0h PULL_CTRL_GPIO_48 2C...

Page 980: ... 2F4h PULL_CTRL_GPIO_61 2F5h IBUF_ST_GPIO_61 2F6h ODRIV_DS_GPIO_61 2F8h PULL_CTRL_GPIO_62 2F9h IBUF_ST_GPIO_62 2FAh ODRIV_DS_GPIO_62 2FCh PULL_CTRL_GPIO_63 2FDh IBUF_ST_GPIO_63 2FEh ODRIV_DS_GPIO_63 300h PULL_CTRL_GPIO_64 301h IBUF_ST_GPIO_64 302h ODRIV_DS_GPIO_64 304h PULL_CTRL_GPIO_65 305h IBUF_ST_GPIO_65 306h ODRIV_DS_GPIO_65 308h PULL_CTRL_GPIO_66 309h IBUF_ST_GPIO_66 30Ah ODRIV_DS_GPIO_66 30C...

Page 981: ...eserved BUF_DIR_CTRL_GPIO_4 413h ACTIV_BIR_DIR_CTRL_GPIO_4 reserved 414h reserved reserved BUF_DIR_CTRL_GPIO_5 417h ACTIV_BIR_DIR_CTRL_GPIO_5 reserved 418h reserved reserved BUF_DIR_CTRL_GPIO_6 41Bh ACTIV_BIR_DIR_CTRL_GPIO_6 reserved 41Ch reserved reserved BUF_DIR_CTRL_GPIO_7 41Fh ACTIV_BIR_DIR_CTRL_GPIO_7 reserved 420h reserved reserved BUF_DIR_CTRL_GPIO_8 423h ACTIV_BIR_DIR_CTRL_GPIO_8 reserved ...

Page 982: ...served 478h reserved reserved BUF_DIR_CTRL_GPIO_30 47Bh ACTIV_BIR_DIR_CTRL_GPIO_30 reserved 47Ch reserved reserved BUF_DIR_CTRL_GPIO_31 47Fh ACTIV_BIR_DIR_CTRL_GPIO_31 reserved 480h reserved reserved BUF_DIR_CTRL_GPIO_32 483h ACTIV_BIR_DIR_CTRL_GPIO_32 reserved 484h reserved reserved BUF_DIR_CTRL_GPIO_33 487h ACTIV_BIR_DIR_CTRL_GPIO_33 reserved 488h reserved reserved BUF_DIR_CTRL_GPIO_34 48Bh ACTI...

Page 983: ...served 4E8h reserved reserved BUF_DIR_CTRL_GPIO_58 4EBh ACTIV_BIR_DIR_CTRL_GPIO_58 reserved 4ECh reserved reserved BUF_DIR_CTRL_GPIO_59 4EFh ACTIV_BIR_DIR_CTRL_GPIO_59 reserved 4F0h reserved reserved BUF_DIR_CTRL_GPIO_60 4F3h ACTIV_BIR_DIR_CTRL_GPIO_60 reserved 4F4h reserved reserved BUF_DIR_CTRL_GPIO_61 4F7h ACTIV_BIR_DIR_CTRL_GPIO_61 reserved 4F8h reserved reserved BUF_DIR_CTRL_GPIO_62 4FBh ACTI...

Page 984: ...BI PO_SPIB1_SDO OVR_INTBIPO_ SPIB1_SDO 70Ch POL_INTBIPO_ SPIB2_SDO 70Dh OVR_SEL_INTBI PO_SPIB2_SDO OVR_INTBIPO_ SPIB2_SDO 800h SEL_INTPI_SPIB2_CS_N POL_INTPI_SPI B2_CS_N 801h OVR_SEL_INTPI _SPIB2_CS_N OVR_INTPI_SPI B2_CS_N 804h SEL_INTPI_SPIB2_CLK POL_INTPI_SPI B2_CLK 805h OVR_SEL_INTPI _SPIB2_CLK OVR_INTPI_SPI B2_CLK 818h SEL_INTPI_RXAB_DSA_GAIN_0 POL_INTPI_RXA B_DSA_GAIN_0 819h OVR_SEL_INTPI _RX...

Page 985: ..._RXCD_DSA_GAIN_3 POL_INTPI_RX CD_DSA_GAIN_ 3 845h OVR_SEL_INTPI _RXCD_DSA_G AIN_3 OVR_INTPI_RX CD_DSA_GAIN_ 3 848h SEL_INTPI_RXCD_DSA_GAIN_4 POL_INTPI_RX CD_DSA_GAIN_ 4 849h OVR_SEL_INTPI _RXCD_DSA_G AIN_4 OVR_INTPI_RX CD_DSA_GAIN_ 4 84Ch SEL_INTPI_RXCD_DSA_GAIN_5 POL_INTPI_RX CD_DSA_GAIN_ 5 84Dh OVR_SEL_INTPI _RXCD_DSA_G AIN_5 OVR_INTPI_RX CD_DSA_GAIN_ 5 850h SEL_INTPI_RXCD_DSA_GAINSEL POL_INTPI_...

Page 986: ...VR_SEL_INTPI _RXC_DSA_GAI N_2 OVR_INTPI_RX C_DSA_GAIN_2 87Ch SEL_INTPI_RXD_DSA_GAIN_0 POL_INTPI_RX D_DSA_GAIN_0 87Dh OVR_SEL_INTPI _RXD_DSA_GAI N_0 OVR_INTPI_RX D_DSA_GAIN_0 880h SEL_INTPI_RXD_DSA_GAIN_1 POL_INTPI_RX D_DSA_GAIN_1 881h OVR_SEL_INTPI _RXD_DSA_GAI N_1 OVR_INTPI_RX D_DSA_GAIN_1 884h SEL_INTPI_RXD_DSA_GAIN_2 POL_INTPI_RX D_DSA_GAIN_2 885h OVR_SEL_INTPI _RXD_DSA_GAI N_2 OVR_INTPI_RX D_D...

Page 987: ..._TDD_EN_TXC OVR_INTPI_TD D_EN_TXC 8C4h SEL_INTPI_TDD_EN_TXD POL_INTPI_TDD _EN_TXD 8C5h OVR_SEL_INTPI _TDD_EN_TXD OVR_INTPI_TD D_EN_TXD 8C8h SEL_INTPI_TDD_EN_FBAB POL_INTPI_TDD _EN_FBAB 8C9h OVR_SEL_INTPI _TDD_EN_FBAB OVR_INTPI_TD D_EN_FBAB 8CCh SEL_INTPI_TDD_EN_FBCD POL_INTPI_TDD _EN_FBCD 8CDh OVR_SEL_INTPI _TDD_EN_FBC D OVR_INTPI_TD D_EN_FBCD 904h SEL_INTPI_GLOBAL_PDN POL_INTPI_GL OBAL_PDN 905h O...

Page 988: ...D_AGC_PIN_FR EEZE 9D1h OVR_SEL_INTPI _FBCD_AGC_PI N_FREEZE OVR_INTPI_FB CD_AGC_PIN_F REEZE 9D4h SEL_INTPI_TDD_EN_RXA POL_INTPI_TDD _EN_RXA 9D5h OVR_SEL_INTPI _TDD_EN_RXA OVR_INTPI_TD D_EN_RXA 9D8h SEL_INTPI_TDD_EN_RXB POL_INTPI_TDD _EN_RXB 9D9h OVR_SEL_INTPI _TDD_EN_RXB OVR_INTPI_TD D_EN_RXB 9DCh SEL_INTPI_TDD_EN_RXC POL_INTPI_TDD _EN_RXC 9DDh OVR_SEL_INTPI _TDD_EN_RXC OVR_INTPI_TD D_EN_RXC 9E0h S...

Page 989: ..._2 A28h SEL_INTPI_FB_NCOSEL_3 POL_INTPI_FB_ NCOSEL_3 A29h OVR_SEL_INTPI _FB_NCOSEL_3 OVR_INTPI_FB_ NCOSEL_3 A2Ch SEL_INTPI_RX_NCOSEL_0 POL_INTPI_RX_ NCOSEL_0 A2Dh OVR_SEL_INTPI _RX_NCOSEL_0 OVR_INTPI_RX _NCOSEL_0 A30h SEL_INTPI_RX_NCOSEL_1 POL_INTPI_RX_ NCOSEL_1 A31h OVR_SEL_INTPI _RX_NCOSEL_1 OVR_INTPI_RX _NCOSEL_1 A34h SEL_INTPI_RX_NCOSEL_2 POL_INTPI_RX_ NCOSEL_2 A35h OVR_SEL_INTPI _RX_NCOSEL_2 ...

Page 990: ...KDET _3 OVR_INTPO_RX A_PKDET_3 107Ch POL_INTPO_RX B_PKDET_0 107Dh OVR_SEL_INTP O_RXB_PKDET _0 OVR_INTPO_RX B_PKDET_0 1080h POL_INTPO_RX B_PKDET_1 1081h OVR_SEL_INTP O_RXB_PKDET _1 OVR_INTPO_RX B_PKDET_1 1084h POL_INTPO_RX B_PKDET_2 1085h OVR_SEL_INTP O_RXB_PKDET _2 OVR_INTPO_RX B_PKDET_2 1088h POL_INTPO_RX B_PKDET_3 1089h OVR_SEL_INTP O_RXB_PKDET _3 OVR_INTPO_RX B_PKDET_3 108Ch POL_INTPO_RX C_PKDE...

Page 991: ...B _0 10C5h OVR_SEL_INTP O_DAC_SYNC_ N_AB_0 OVR_INTPO_DA C_SYNC_N_AB _0 10C8h POL_INTPO_DA C_SYNC_N_AB _1 10C9h OVR_SEL_INTP O_DAC_SYNC_ N_AB_1 OVR_INTPO_DA C_SYNC_N_AB _1 10F0h POL_INTPO_DA C_SYNC_N_CD _0 10F1h OVR_SEL_INTP O_DAC_SYNC_ N_CD_0 OVR_INTPO_DA C_SYNC_N_CD _0 10F4h POL_INTPO_DA C_SYNC_N_CD _1 10F5h OVR_SEL_INTP O_DAC_SYNC_ N_CD_1 OVR_INTPO_DA C_SYNC_N_CD _1 11A4h POL_INTPO_FB AB_PKDET_0...

Page 992: ...403h READ_INTPO_R XA_PKDET_0 1404h READ_INTPO_R XA_PKDET_1 1405h READ_INTPO_R XA_PKDET_2 1406h READ_INTPO_R XA_PKDET_3 1407h READ_INTPO_R XB_PKDET_0 1408h READ_INTPO_R XB_PKDET_1 1409h READ_INTPO_R XB_PKDET_2 140Ah READ_INTPO_R XB_PKDET_3 140Bh READ_INTPO_R XC_PKDET_0 140Ch READ_INTPO_R XC_PKDET_1 140Dh READ_INTPO_R XC_PKDET_2 140Eh READ_INTPO_R XC_PKDET_3 140Fh READ_INTPO_R XD_PKDET_0 1410h READ_...

Page 993: ..._PKDET_0 1456h READ_INTPO_F BCD_PKDET_1 1457h READ_INTPO_F BCD_PKDET_2 1458h READ_INTPO_F BCD_PKDET_3 17D0h READ_INTPI_S PIB2_CS_N 17D1h READ_INTPI_S PIB2_CLK 17D6h READ_INTPI_R XAB_DSA_GAIN _0 17D7h READ_INTPI_R XAB_DSA_GAIN _1 17D8h READ_INTPI_R XAB_DSA_GAIN _2 17D9h READ_INTPI_R XAB_DSA_GAIN _3 17DAh READ_INTPI_R XAB_DSA_GAIN _4 17DBh READ_INTPI_R XAB_DSA_GAIN _5 17DCh READ_INTPI_R XAB_DSA_GAIN...

Page 994: ..._R XB_DSA_GAIN_ 2 17ECh READ_INTPI_R XC_DSA_GAIN_ 0 17EDh READ_INTPI_R XC_DSA_GAIN_ 1 17EEh READ_INTPI_R XC_DSA_GAIN_ 2 17EFh READ_INTPI_R XD_DSA_GAIN_ 0 17F0h READ_INTPI_R XD_DSA_GAIN_ 1 17F1h READ_INTPI_R XD_DSA_GAIN_ 2 17F6h READ_INTPI_S PIB1_CS_N 17F7h READ_INTPI_S PIB1_CLK 17F8h READ_INTPI_A DC_SYNC_N_A B_0 17F9h READ_INTPI_A DC_SYNC_N_A B_1 17FAh READ_INTPI_A DC_SYNC_N_A B_2 17FBh READ_INTPI...

Page 995: ...READ_INTPI_R XC_ALC_INPUT _0_B0 180Ch READ_INTPI_R XC_ALC_INPUT _1_B0 180Dh READ_INTPI_R XC_ALC_INPUT _2_B0 180Eh READ_INTPI_R XD_ALC_INPUT _0_B0 180Fh READ_INTPI_R XD_ALC_INPUT _1_B0 1810h READ_INTPI_R XD_ALC_INPUT _2_B0 1811h READ_INTPI_G LOBAL_PDN 1812h READ_INTPI_TX _FB_LOOP_0 1813h READ_INTPI_TX _FB_LOOP_1 1814h READ_INTPI_TX _FB_LOOP_2 1815h READ_INTPI_TX _FB_LOOP_3 181Ah READ_INTPI_FB _NCO_...

Page 996: ...SA_LATCH 182Ah READ_INTPI_S YS_REF_ALIGN 182Bh READ_INTPI_R XA_ALC_INPUT _0_B1 182Ch READ_INTPI_R XA_ALC_INPUT _1_B1 182Dh READ_INTPI_R XA_ALC_INPUT _2_B1 182Eh READ_INTPI_R XB_ALC_INPUT _0_B1 182Fh READ_INTPI_R XB_ALC_INPUT _1_B1 1830h READ_INTPI_R XB_ALC_INPUT _2_B1 1831h READ_INTPI_R XC_ALC_INPUT _0_B1 1832h READ_INTPI_R XC_ALC_INPUT _1_B1 1833h READ_INTPI_R XC_ALC_INPUT _2_B1 1834h READ_INTPI_...

Page 997: ...h READ_INTPI_FB AB_AGC_PIN_F REEZE 1844h READ_INTPI_FB CD_AGC_PIN_F REEZE 1845h READ_INTPI_T DD_EN_RXA 1846h READ_INTPI_T DD_EN_RXB 1847h READ_INTPI_T DD_EN_RXC 1848h READ_INTPI_T DD_EN_RXD 1849h READ_INTPI_R X_GAIN_SW_0 184Ah READ_INTPI_R X_GAIN_SW_1 184Bh READ_INTPI_R X_GAIN_SW_2 184Ch READ_INTPI_R X_GAIN_SW_3 184Dh READ_INTPI_G PIO_PKDET_WI N_RXA 184Eh READ_INTPI_G PIO_PKDET_WI N_RXB 184Fh READ...

Page 998: ...TPI_TX _NCOSEL_2 1862h READ_INTPI_TX _NCOSEL_3 1880h TEST_REG1 7 0 1881h TEST_REG1 15 8 1882h TEST_REG1 23 16 1883h TEST_REG1 31 24 1884h TEST_REG0 7 0 1885h TEST_REG0 15 8 1886h TEST_REG0 23 16 1887h TEST_REG0 31 24 2 16 1 Register 200h offset 200h reset 1h Figure 2 2264 Register 200h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_0 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2280 Regis...

Page 999: ... Reset Description 1 0 ODRIV_DS_GPIO_ 0 R W 0h output buffer drive strength 2 16 4 Register 204h offset 204h reset 1h Figure 2 2267 Register 204h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_1 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2283 Register 204 Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _1 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull ...

Page 1000: ...6 5 4 3 2 1 0 PULL_CTRL_GPIO_2 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2286 Register 208 Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _2 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 8 Register 209h offset 209h reset 2h Figure 2 2271 Register 209h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_2 R W 2h LEGEND R W Read Wr...

Page 1001: ...pe Reset Description 2 0 PULL_CTRL_GPIO _3 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 11 Register 20Dh offset 20Dh reset 2h Figure 2 2274 Register 20Dh 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_3 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2290 Register 20D Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_3 R W 2h Input bu...

Page 1002: ...et 211h reset 2h Figure 2 2277 Register 211h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_4 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2293 Register 211 Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_4 R W 2h Input buffer signal strength 2 16 15 Register 212h offset 212h reset 0h Figure 2 2278 Register 212h 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_4 R W 0h LEGEND R W Read Wri...

Page 1003: ...riptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_5 R W 2h Input buffer signal strength 2 16 18 Register 216h offset 216h reset 0h Figure 2 2281 Register 216h 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_5 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2297 Register 216 Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 5 R W 0h output buffer drive strength 2 1...

Page 1004: ...5 4 3 2 1 0 ODRIV_DS_GPIO_6 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2300 Register 21A Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 6 R W 0h output buffer drive strength 2 16 22 Register 21Ch offset 21Ch reset 1h Figure 2 2285 Register 21Ch 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_7 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2...

Page 1005: ... Reset Description 1 0 ODRIV_DS_GPIO_ 7 R W 0h output buffer drive strength 2 16 25 Register 220h offset 220h reset 1h Figure 2 2288 Register 220h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_8 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2304 Register 220 Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _8 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull...

Page 1006: ...6 5 4 3 2 1 0 PULL_CTRL_GPIO_9 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2307 Register 224 Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _9 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 29 Register 225h offset 225h reset 2h Figure 2 2292 Register 225h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_9 R W 2h LEGEND R W Read W...

Page 1007: ... Reset Description 2 0 PULL_CTRL_GPIO _10 R W 3h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 32 Register 229h offset 229h reset 2h Figure 2 2295 Register 229h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_10 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2311 Register 229 Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_1 0 R W 2h Input ...

Page 1008: ... 22Dh reset 2h Figure 2 2298 Register 22Dh 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_11 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2314 Register 22D Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_1 1 R W 2h Input buffer signal strength 2 16 36 Register 22Eh offset 22Eh reset 0h Figure 2 2299 Register 22Eh 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_11 R W 0h LEGEND R W Read W...

Page 1009: ...ptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_1 2 R W 2h Input buffer signal strength 2 16 39 Register 232h offset 232h reset 0h Figure 2 2302 Register 232h 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_12 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2318 Register 232 Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 12 R W 0h output buffer drive strength 2...

Page 1010: ... 4 3 2 1 0 ODRIV_DS_GPIO_13 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2321 Register 236 Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 13 R W 0h output buffer drive strength 2 16 43 Register 238h offset 238h reset 1h Figure 2 2306 Register 238h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_14 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2...

Page 1011: ...ield Type Reset Description 1 0 ODRIV_DS_GPIO_ 14 R W 0h output buffer drive strength 2 16 46 Register 23Ch offset 23Ch reset 3h Figure 2 2309 Register 23Ch 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_15 R W 3h LEGEND R W Read Write W Write only n value after reset Table 2 2325 Register 23C Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _15 R W 3h Unused as this is fixed IO 2 16 47 Regi...

Page 1012: ...ster 240h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_16 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2328 Register 240 Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _16 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 50 Register 241h offset 241h reset 2h Figure 2 2313 Register 241h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_16 R W 2h LE...

Page 1013: ... Reset Description 2 0 PULL_CTRL_GPIO _17 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 53 Register 245h offset 245h reset 2h Figure 2 2316 Register 245h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_17 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2332 Register 245 Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_1 7 R W 2h Input ...

Page 1014: ... 249h reset 2h Figure 2 2319 Register 249h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_18 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2335 Register 249 Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_1 8 R W 2h Input buffer signal strength 2 16 57 Register 24Ah offset 24Ah reset 0h Figure 2 2320 Register 24Ah 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_18 R W 0h LEGEND R W Read W...

Page 1015: ...ptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_1 9 R W 2h Input buffer signal strength 2 16 60 Register 24Eh offset 24Eh reset 0h Figure 2 2323 Register 24Eh 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_19 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2339 Register 24E Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 19 R W 0h output buffer drive strength 2...

Page 1016: ... 4 3 2 1 0 ODRIV_DS_GPIO_20 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2342 Register 252 Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 20 R W 0h output buffer drive strength 2 16 64 Register 254h offset 254h reset 1h Figure 2 2327 Register 254h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_21 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2...

Page 1017: ...Reset Description 1 0 ODRIV_DS_GPIO_ 21 R W 0h output buffer drive strength 2 16 67 Register 258h offset 258h reset 1h Figure 2 2330 Register 258h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_22 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2346 Register 258 Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _22 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pu...

Page 1018: ...5 4 3 2 1 0 PULL_CTRL_GPIO_23 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2349 Register 25C Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _23 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 71 Register 25Dh offset 25Dh reset 2h Figure 2 2334 Register 25Dh 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_23 R W 2h LEGEND R W Read ...

Page 1019: ..._CTRL_GPIO _24 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 74 Register 261h offset 261h reset 2h Figure 2 2337 Register 261h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_24 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2353 Register 261 Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_2 4 R W 2h Input buffer signal strength Unus...

Page 1020: ...0 Register 265h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_25 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2356 Register 265 Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_2 5 R W 2h Input buffer signal strength Unused as this is fixed IO 2 16 78 Register 266h offset 266h reset 0h Figure 2 2341 Register 266h 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_25 R W 0h LEGEND R W Read W...

Page 1021: ...ptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_2 6 R W 2h Input buffer signal strength 2 16 81 Register 26Ah offset 26Ah reset 0h Figure 2 2344 Register 26Ah 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_26 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2360 Register 26A Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 26 R W 0h output buffer drive strength 2...

Page 1022: ... 4 3 2 1 0 ODRIV_DS_GPIO_27 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2363 Register 26E Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 27 R W 0h output buffer drive strength 2 16 85 Register 270h offset 270h reset 1h Figure 2 2348 Register 270h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_28 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2...

Page 1023: ...Reset Description 1 0 ODRIV_DS_GPIO_ 28 R W 0h output buffer drive strength 2 16 88 Register 274h offset 274h reset 1h Figure 2 2351 Register 274h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_29 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2367 Register 274 Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _29 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pu...

Page 1024: ...ULL_CTRL_GPIO_30 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2370 Register 278 Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _30 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 92 Register 279h offset 279h reset 2h Figure 2 2355 Register 279h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_30 R W 2h LEGEND R W Read Write W Write...

Page 1025: ...Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _31 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 95 Register 27Dh offset 27Dh reset 2h Figure 2 2358 Register 27Dh 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_31 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2374 Register 27D Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_3 1...

Page 1026: ... Register 281h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_32 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2377 Register 281 Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_3 2 R W 2h Input buffer signal strength Unused as this is fixed IO 2 16 99 Register 282h offset 282h reset 0h Figure 2 2362 Register 282h 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_32 R W 0h LEGEND R W Read Wr...

Page 1027: ...ptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_3 3 R W 2h Input buffer signal strength 2 16 102 Register 286h offset 286h reset 0h Figure 2 2365 Register 286h 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_33 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2381 Register 286 Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 33 R W 0h output buffer drive strength ...

Page 1028: ... 4 3 2 1 0 ODRIV_DS_GPIO_34 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2384 Register 28A Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 34 R W 0h output buffer drive strength 2 16 106 Register 28Ch offset 28Ch reset 1h Figure 2 2369 Register 28Ch 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_35 R W 1h LEGEND R W Read Write W Write only n value after reset Table ...

Page 1029: ...eset Description 1 0 ODRIV_DS_GPIO_ 35 R W 0h output buffer drive strength 2 16 109 Register 290h offset 290h reset 1h Figure 2 2372 Register 290h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_36 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2388 Register 290 Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _36 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pu...

Page 1030: ...ULL_CTRL_GPIO_37 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2391 Register 294 Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _37 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 113 Register 295h offset 295h reset 2h Figure 2 2376 Register 295h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_37 R W 2h LEGEND R W Read Write W Writ...

Page 1031: ...tion 2 0 PULL_CTRL_GPIO _38 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 116 Register 299h offset 299h reset 2h Figure 2 2379 Register 299h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_38 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2395 Register 299 Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_3 8 R W 2h Input buffer signal...

Page 1032: ... 29Dh reset 2h Figure 2 2382 Register 29Dh 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_39 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2398 Register 29D Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_3 9 R W 2h Input buffer signal strength 2 16 120 Register 29Eh offset 29Eh reset 0h Figure 2 2383 Register 29Eh 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_39 R W 0h LEGEND R W Read ...

Page 1033: ...ptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_4 0 R W 2h Input buffer signal strength 2 16 123 Register 2A2h offset 2A2h reset 0h Figure 2 2386 Register 2A2h 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_40 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2402 Register 2A2 Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 40 R W 0h output buffer drive strength ...

Page 1034: ... 4 3 2 1 0 ODRIV_DS_GPIO_41 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2405 Register 2A6 Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 41 R W 0h output buffer drive strength 2 16 127 Register 2A8h offset 2A8h reset 1h Figure 2 2390 Register 2A8h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_42 R W 1h LEGEND R W Read Write W Write only n value after reset Table ...

Page 1035: ...eset Description 1 0 ODRIV_DS_GPIO_ 42 R W 0h output buffer drive strength 2 16 130 Register 2ACh offset 2ACh reset 1h Figure 2 2393 Register 2ACh 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_43 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2409 Register 2AC Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _43 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pu...

Page 1036: ...5 4 3 2 1 0 PULL_CTRL_GPIO_44 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2412 Register 2B0 Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _44 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 134 Register 2B1h offset 2B1h reset 2h Figure 2 2397 Register 2B1h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_44 R W 2h LEGEND R W Read...

Page 1037: ... Reset Description 2 0 PULL_CTRL_GPIO _45 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 137 Register 2B5h offset 2B5h reset 2h Figure 2 2400 Register 2B5h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_45 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2416 Register 2B5 Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_4 5 R W 2h Input...

Page 1038: ... 2B9h reset 2h Figure 2 2403 Register 2B9h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_46 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2419 Register 2B9 Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_4 6 R W 2h Input buffer signal strength 2 16 141 Register 2BAh offset 2BAh reset 0h Figure 2 2404 Register 2BAh 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_46 R W 0h LEGEND R W Read ...

Page 1039: ...ptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_4 7 R W 2h Input buffer signal strength 2 16 144 Register 2BEh offset 2BEh reset 0h Figure 2 2407 Register 2BEh 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_47 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2423 Register 2BE Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 47 R W 0h output buffer drive strength ...

Page 1040: ... 4 3 2 1 0 ODRIV_DS_GPIO_48 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2426 Register 2C2 Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 48 R W 0h output buffer drive strength 2 16 148 Register 2C4h offset 2C4h reset 1h Figure 2 2411 Register 2C4h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_49 R W 1h LEGEND R W Read Write W Write only n value after reset Table ...

Page 1041: ...eset Description 1 0 ODRIV_DS_GPIO_ 49 R W 0h output buffer drive strength 2 16 151 Register 2C8h offset 2C8h reset 1h Figure 2 2414 Register 2C8h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_50 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2430 Register 2C8 Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _50 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pu...

Page 1042: ...5 4 3 2 1 0 PULL_CTRL_GPIO_51 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2433 Register 2CC Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _51 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 155 Register 2CDh offset 2CDh reset 2h Figure 2 2418 Register 2CDh 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_51 R W 2h LEGEND R W Read...

Page 1043: ... Reset Description 2 0 PULL_CTRL_GPIO _52 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 158 Register 2D1h offset 2D1h reset 2h Figure 2 2421 Register 2D1h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_52 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2437 Register 2D1 Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_5 2 R W 2h Input...

Page 1044: ... 2D5h reset 2h Figure 2 2424 Register 2D5h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_53 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2440 Register 2D5 Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_5 3 R W 2h Input buffer signal strength 2 16 162 Register 2D6h offset 2D6h reset 0h Figure 2 2425 Register 2D6h 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_53 R W 0h LEGEND R W Read ...

Page 1045: ...ptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_5 4 R W 2h Input buffer signal strength 2 16 165 Register 2DAh offset 2DAh reset 0h Figure 2 2428 Register 2DAh 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_54 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2444 Register 2DA Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 54 R W 0h output buffer drive strength ...

Page 1046: ... 4 3 2 1 0 ODRIV_DS_GPIO_55 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2447 Register 2DE Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 55 R W 0h output buffer drive strength 2 16 169 Register 2E0h offset 2E0h reset 1h Figure 2 2432 Register 2E0h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_56 R W 1h LEGEND R W Read Write W Write only n value after reset Table ...

Page 1047: ...eset Description 1 0 ODRIV_DS_GPIO_ 56 R W 0h output buffer drive strength 2 16 172 Register 2E4h offset 2E4h reset 1h Figure 2 2435 Register 2E4h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_57 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2451 Register 2E4 Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _57 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pu...

Page 1048: ...5 4 3 2 1 0 PULL_CTRL_GPIO_58 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2454 Register 2E8 Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _58 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 176 Register 2E9h offset 2E9h reset 2h Figure 2 2439 Register 2E9h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_58 R W 2h LEGEND R W Read...

Page 1049: ... Reset Description 2 0 PULL_CTRL_GPIO _59 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 179 Register 2EDh offset 2EDh reset 2h Figure 2 2442 Register 2EDh 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_59 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2458 Register 2ED Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_5 9 R W 2h Input...

Page 1050: ... 2F1h reset 2h Figure 2 2445 Register 2F1h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_60 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2461 Register 2F1 Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_6 0 R W 2h Input buffer signal strength 2 16 183 Register 2F2h offset 2F2h reset 0h Figure 2 2446 Register 2F2h 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_60 R W 0h LEGEND R W Read ...

Page 1051: ...ptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_6 1 R W 2h Input buffer signal strength 2 16 186 Register 2F6h offset 2F6h reset 0h Figure 2 2449 Register 2F6h 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_61 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2465 Register 2F6 Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 61 R W 0h output buffer drive strength ...

Page 1052: ... 4 3 2 1 0 ODRIV_DS_GPIO_62 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2468 Register 2FA Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 62 R W 0h output buffer drive strength 2 16 190 Register 2FCh offset 2FCh reset 1h Figure 2 2453 Register 2FCh 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_63 R W 1h LEGEND R W Read Write W Write only n value after reset Table ...

Page 1053: ...eset Description 1 0 ODRIV_DS_GPIO_ 63 R W 0h output buffer drive strength 2 16 193 Register 300h offset 300h reset 1h Figure 2 2456 Register 300h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_64 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2472 Register 300 Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _64 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pu...

Page 1054: ...5 4 3 2 1 0 PULL_CTRL_GPIO_65 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2475 Register 304 Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _65 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 197 Register 305h offset 305h reset 2h Figure 2 2460 Register 305h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_65 R W 2h LEGEND R W Read...

Page 1055: ... Reset Description 2 0 PULL_CTRL_GPIO _66 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 200 Register 309h offset 309h reset 2h Figure 2 2463 Register 309h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_66 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2479 Register 309 Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_6 6 R W 2h Input...

Page 1056: ... 30Dh reset 2h Figure 2 2466 Register 30Dh 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_67 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2482 Register 30D Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_6 7 R W 2h Input buffer signal strength 2 16 204 Register 30Eh offset 30Eh reset 0h Figure 2 2467 Register 30Eh 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_67 R W 0h LEGEND R W Read ...

Page 1057: ...ptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_6 8 R W 2h Input buffer signal strength 2 16 207 Register 312h offset 312h reset 0h Figure 2 2470 Register 312h 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_68 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2486 Register 312 Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 68 R W 0h output buffer drive strength ...

Page 1058: ... 4 3 2 1 0 ODRIV_DS_GPIO_69 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2489 Register 316 Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 69 R W 0h output buffer drive strength 2 16 211 Register 318h offset 318h reset 1h Figure 2 2474 Register 318h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_70 R W 1h LEGEND R W Read Write W Write only n value after reset Table ...

Page 1059: ...eset Description 1 0 ODRIV_DS_GPIO_ 70 R W 0h output buffer drive strength 2 16 214 Register 31Ch offset 31Ch reset 1h Figure 2 2477 Register 31Ch 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_71 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2493 Register 31C Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _71 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pu...

Page 1060: ...5 4 3 2 1 0 PULL_CTRL_GPIO_72 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2496 Register 320 Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _72 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 218 Register 321h offset 321h reset 2h Figure 2 2481 Register 321h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_72 R W 2h LEGEND R W Read...

Page 1061: ... Reset Description 2 0 PULL_CTRL_GPIO _73 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 221 Register 325h offset 325h reset 2h Figure 2 2484 Register 325h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_73 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2500 Register 325 Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_7 3 R W 2h Input...

Page 1062: ... 329h reset 2h Figure 2 2487 Register 329h 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_74 R W 2h LEGEND R W Read Write W Write only n value after reset Table 2 2503 Register 329 Field Descriptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_7 4 R W 2h Input buffer signal strength 2 16 225 Register 32Ah offset 32Ah reset 0h Figure 2 2488 Register 32Ah 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_74 R W 0h LEGEND R W Read ...

Page 1063: ...ptions Bit Field Type Reset Description 1 0 IBUF_ST_GPIO_7 5 R W 2h Input buffer signal strength 2 16 228 Register 32Eh offset 32Eh reset 0h Figure 2 2491 Register 32Eh 7 6 5 4 3 2 1 0 ODRIV_DS_GPIO_75 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2507 Register 32E Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 75 R W 0h output buffer drive strength ...

Page 1064: ... 4 3 2 1 0 ODRIV_DS_GPIO_76 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2510 Register 332 Field Descriptions Bit Field Type Reset Description 1 0 ODRIV_DS_GPIO_ 76 R W 0h output buffer drive strength 2 16 232 Register 334h offset 334h reset 1h Figure 2 2495 Register 334h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_77 R W 1h LEGEND R W Read Write W Write only n value after reset Table ...

Page 1065: ...eset Description 1 0 ODRIV_DS_GPIO_ 77 R W 0h output buffer drive strength 2 16 235 Register 338h offset 338h reset 1h Figure 2 2498 Register 338h 7 6 5 4 3 2 1 0 PULL_CTRL_GPIO_78 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2514 Register 338 Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _78 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pu...

Page 1066: ...5 4 3 2 1 0 PULL_CTRL_GPIO_79 R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2517 Register 33C Field Descriptions Bit Field Type Reset Description 2 0 PULL_CTRL_GPIO _79 R W 1h Bit 0 indicates Pull up enable Bit 1 Indicates Pull value Bit 2 is unused 2 16 239 Register 33Dh offset 33Dh reset 2h Figure 2 2502 Register 33Dh 7 6 5 4 3 2 1 0 IBUF_ST_GPIO_79 R W 2h LEGEND R W Read...

Page 1067: ...GPIO 0 both input and output are not selected can be used for analog 1 input mode 2 output mode 3 shouldnt be used 2 16 242 Register 403h offset 403h reset 0h Figure 2 2505 Register 403h 7 6 5 4 3 2 1 0 ACTIV_BIR_DIR_CTRL_GPIO_0 reserved R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2521 Register 403 Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_D...

Page 1068: ... 2523 Register 407 Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_1 R W 0h Control to indicate whether the GPIO_1 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use the IO for 3 pin SPI B2 SDIO 5 Use the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 245 Register 408h offset 408h rese...

Page 1069: ...e the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 247 Register 40Ch offset 40Ch reset 1h Figure 2 2510 Register 40Ch 7 6 5 4 3 2 1 0 reserved reserved BUF_DIR_CTRL_GPIO_3 R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2526 Register 40C Field Descriptions Bit Field Type Reset Description 7...

Page 1070: ...d Write W Write only n value after reset Table 2 2528 Register 410 Field Descriptions Bit Field Type Reset Description 7 5 reserved R W 0h 4 2 reserved R W 0h 1 0 BUF_DIR_CTRL_G PIO_4 R W 1h Controls the direction of GPIO 0 both input and output are not selected can be used for analog 1 input mode 2 output mode 3 shouldnt be used 2 16 250 Register 413h offset 413h reset 0h Figure 2 2513 Register 4...

Page 1071: ...ister 417h offset 417h reset 0h Figure 2 2515 Register 417h 7 6 5 4 3 2 1 0 ACTIV_BIR_DIR_CTRL_GPIO_5 reserved R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2531 Register 417 Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_5 R W 0h Control to indicate whether the GPIO_5 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use the ...

Page 1072: ...41B Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_6 R W 0h Control to indicate whether the GPIO_6 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use the IO for 3 pin SPI B2 SDIO 5 Use the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 255 Register 41Ch offset 41Ch reset 1h Figure 2 2...

Page 1073: ...e the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 257 Register 420h offset 420h reset 1h Figure 2 2520 Register 420h 7 6 5 4 3 2 1 0 reserved reserved BUF_DIR_CTRL_GPIO_8 R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2536 Register 420 Field Descriptions Bit Field Type Reset Description 7...

Page 1074: ...d Write W Write only n value after reset Table 2 2538 Register 424 Field Descriptions Bit Field Type Reset Description 7 5 reserved R W 0h 4 2 reserved R W 0h 1 0 BUF_DIR_CTRL_G PIO_9 R W 1h Controls the direction of GPIO 0 both input and output are not selected can be used for analog 1 input mode 2 output mode 3 shouldnt be used 2 16 260 Register 427h offset 427h reset 0h Figure 2 2523 Register 4...

Page 1075: ...ster 42Bh offset 42Bh reset 0h Figure 2 2525 Register 42Bh 7 6 5 4 3 2 1 0 ACTIV_BIR_DIR_CTRL_GPIO_10 reserved R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2541 Register 42B Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_10 R W 0h Control to indicate whether the GPIO_10 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use th...

Page 1076: ...2F Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_11 R W 0h Control to indicate whether the GPIO_11 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use the IO for 3 pin SPI B2 SDIO 5 Use the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 265 Register 430h offset 430h reset 1h Figure 2 ...

Page 1077: ...e the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 267 Register 434h offset 434h reset 1h Figure 2 2530 Register 434h 7 6 5 4 3 2 1 0 reserved reserved BUF_DIR_CTRL_GPIO_13 R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2546 Register 434 Field Descriptions Bit Field Type Reset Description ...

Page 1078: ...d Write W Write only n value after reset Table 2 2548 Register 438 Field Descriptions Bit Field Type Reset Description 7 5 reserved R W 0h 4 2 reserved R W 0h 1 0 BUF_DIR_CTRL_G PIO_14 R W 1h Controls the direction of GPIO 0 both input and output are not selected can be used for analog 1 input mode 2 output mode 3 shouldnt be used 2 16 270 Register 43Bh offset 43Bh reset 0h Figure 2 2533 Register ...

Page 1079: ...ster 43Fh offset 43Fh reset 0h Figure 2 2535 Register 43Fh 7 6 5 4 3 2 1 0 ACTIV_BIR_DIR_CTRL_GPIO_15 reserved R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2551 Register 43F Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_15 R W 0h Control to indicate whether the GPIO_15 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use th...

Page 1080: ...43 Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_16 R W 0h Control to indicate whether the GPIO_16 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use the IO for 3 pin SPI B2 SDIO 5 Use the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 275 Register 444h offset 444h reset 1h Figure 2 ...

Page 1081: ...e the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 277 Register 448h offset 448h reset 1h Figure 2 2540 Register 448h 7 6 5 4 3 2 1 0 reserved reserved BUF_DIR_CTRL_GPIO_18 R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2556 Register 448 Field Descriptions Bit Field Type Reset Description ...

Page 1082: ...d Write W Write only n value after reset Table 2 2558 Register 44C Field Descriptions Bit Field Type Reset Description 7 5 reserved R W 0h 4 2 reserved R W 0h 1 0 BUF_DIR_CTRL_G PIO_19 R W 1h Controls the direction of GPIO 0 both input and output are not selected can be used for analog 1 input mode 2 output mode 3 shouldnt be used 2 16 280 Register 44Fh offset 44Fh reset 0h Figure 2 2543 Register ...

Page 1083: ...ster 453h offset 453h reset 0h Figure 2 2545 Register 453h 7 6 5 4 3 2 1 0 ACTIV_BIR_DIR_CTRL_GPIO_20 reserved R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2561 Register 453 Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_20 R W 0h Control to indicate whether the GPIO_20 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use th...

Page 1084: ...57 Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_21 R W 0h Control to indicate whether the GPIO_21 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use the IO for 3 pin SPI B2 SDIO 5 Use the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 285 Register 458h offset 458h reset 1h Figure 2 ...

Page 1085: ...e the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 287 Register 45Ch offset 45Ch reset 1h Figure 2 2550 Register 45Ch 7 6 5 4 3 2 1 0 reserved reserved BUF_DIR_CTRL_GPIO_23 R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2566 Register 45C Field Descriptions Bit Field Type Reset Description ...

Page 1086: ...e after reset Table 2 2568 Register 460 Field Descriptions Bit Field Type Reset Description 7 5 reserved R W 0h 4 2 reserved R W 0h 1 0 BUF_DIR_CTRL_G PIO_24 R W 1h Controls the direction of GPIO 0 both input and output are not selected can be used for analog 1 input mode 2 output mode 3 shouldnt be used Unused as this is fixed IO 2 16 290 Register 463h offset 463h reset 0h Figure 2 2553 Register ...

Page 1087: ...ster 467h offset 467h reset 0h Figure 2 2555 Register 467h 7 6 5 4 3 2 1 0 ACTIV_BIR_DIR_CTRL_GPIO_25 reserved R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2571 Register 467 Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_25 R W 0h Control to indicate whether the GPIO_26 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use th...

Page 1088: ...6B Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_26 R W 0h Control to indicate whether the GPIO_26 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use the IO for 3 pin SPI B2 SDIO 5 Use the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 295 Register 46Ch offset 46Ch reset 1h Figure 2 ...

Page 1089: ...e the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 297 Register 470h offset 470h reset 1h Figure 2 2560 Register 470h 7 6 5 4 3 2 1 0 reserved reserved BUF_DIR_CTRL_GPIO_28 R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2576 Register 470 Field Descriptions Bit Field Type Reset Description ...

Page 1090: ...d Write W Write only n value after reset Table 2 2578 Register 474 Field Descriptions Bit Field Type Reset Description 7 5 reserved R W 0h 4 2 reserved R W 0h 1 0 BUF_DIR_CTRL_G PIO_29 R W 1h Controls the direction of GPIO 0 both input and output are not selected can be used for analog 1 input mode 2 output mode 3 shouldnt be used 2 16 300 Register 477h offset 477h reset 0h Figure 2 2563 Register ...

Page 1091: ...ster 47Bh offset 47Bh reset 0h Figure 2 2565 Register 47Bh 7 6 5 4 3 2 1 0 ACTIV_BIR_DIR_CTRL_GPIO_30 reserved R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2581 Register 47B Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_30 R W 0h Control to indicate whether the GPIO_30 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use th...

Page 1092: ...iptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_31 R W 0h Control to indicate whether the GPIO_31 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use the IO for 3 pin SPI B2 SDIO 5 Use the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 305 Register 480h offset 480h reset 1h Figure 2 2568 Register ...

Page 1093: ...4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO Unused as this is fixed IO 0 0 reserved R W 0h 2 16 307 Register 484h offset 484h reset 1h Figure 2 2570 Register 484h 7 6 5 4 3 2 1 0 reserved reserved BUF_DIR_CTRL_GPIO_33 R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2586 Register 484 Field Descriptions Bit Field Type Rese...

Page 1094: ...d Write W Write only n value after reset Table 2 2588 Register 488 Field Descriptions Bit Field Type Reset Description 7 5 reserved R W 0h 4 2 reserved R W 0h 1 0 BUF_DIR_CTRL_G PIO_34 R W 1h Controls the direction of GPIO 0 both input and output are not selected can be used for analog 1 input mode 2 output mode 3 shouldnt be used 2 16 310 Register 48Bh offset 48Bh reset 0h Figure 2 2573 Register ...

Page 1095: ...ster 48Fh offset 48Fh reset 0h Figure 2 2575 Register 48Fh 7 6 5 4 3 2 1 0 ACTIV_BIR_DIR_CTRL_GPIO_35 reserved R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2591 Register 48F Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_35 R W 0h Control to indicate whether the GPIO_35 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use th...

Page 1096: ...iptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_36 R W 0h Control to indicate whether the GPIO_36 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use the IO for 3 pin SPI B2 SDIO 5 Use the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 315 Register 494h offset 494h reset 1h Figure 2 2578 Register ...

Page 1097: ...DO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO Unused as this is fixed IO 0 0 reserved R W 0h 2 16 317 Register 498h offset 498h reset 1h Figure 2 2580 Register 498h 7 6 5 4 3 2 1 0 reserved reserved BUF_DIR_CTRL_GPIO_38 R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2596 Register 498 Field Descriptions Bit Field Type Reset Description ...

Page 1098: ...EGEND R W Read Write W Write only n value after reset Table 2 2598 Register 49C Field Descriptions Bit Field Type Reset Description 7 5 reserved R W 0h 4 2 reserved R W 0h 1 0 BUF_DIR_CTRL_G PIO_39 R W 1h Controls the direction of GPIO 0 both input and output are not selected can be used for analog 1 input mode 2 output mode 3 shouldnt be used 2 16 320 Register 49Fh offset 49Fh reset 0h Figure 2 2...

Page 1099: ...ster 4A3h offset 4A3h reset 0h Figure 2 2585 Register 4A3h 7 6 5 4 3 2 1 0 ACTIV_BIR_DIR_CTRL_GPIO_40 reserved R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2601 Register 4A3 Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_40 R W 0h Control to indicate whether the GPIO_40 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use th...

Page 1100: ...A7 Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_41 R W 0h Control to indicate whether the GPIO_41 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use the IO for 3 pin SPI B2 SDIO 5 Use the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 325 Register 4A8h offset 4A8h reset 1h Figure 2 ...

Page 1101: ...e the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 327 Register 4ACh offset 4ACh reset 1h Figure 2 2590 Register 4ACh 7 6 5 4 3 2 1 0 reserved reserved BUF_DIR_CTRL_GPIO_43 R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2606 Register 4AC Field Descriptions Bit Field Type Reset Description ...

Page 1102: ...d Write W Write only n value after reset Table 2 2608 Register 4B0 Field Descriptions Bit Field Type Reset Description 7 5 reserved R W 0h 4 2 reserved R W 0h 1 0 BUF_DIR_CTRL_G PIO_44 R W 1h Controls the direction of GPIO 0 both input and output are not selected can be used for analog 1 input mode 2 output mode 3 shouldnt be used 2 16 330 Register 4B3h offset 4B3h reset 0h Figure 2 2593 Register ...

Page 1103: ...ster 4B7h offset 4B7h reset 0h Figure 2 2595 Register 4B7h 7 6 5 4 3 2 1 0 ACTIV_BIR_DIR_CTRL_GPIO_45 reserved R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2611 Register 4B7 Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_45 R W 0h Control to indicate whether the GPIO_45 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use th...

Page 1104: ...BB Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_46 R W 0h Control to indicate whether the GPIO_46 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use the IO for 3 pin SPI B2 SDIO 5 Use the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 335 Register 4BCh offset 4BCh reset 1h Figure 2 ...

Page 1105: ...e the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 337 Register 4C0h offset 4C0h reset 1h Figure 2 2600 Register 4C0h 7 6 5 4 3 2 1 0 reserved reserved BUF_DIR_CTRL_GPIO_48 R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2616 Register 4C0 Field Descriptions Bit Field Type Reset Description ...

Page 1106: ...d Write W Write only n value after reset Table 2 2618 Register 4C4 Field Descriptions Bit Field Type Reset Description 7 5 reserved R W 0h 4 2 reserved R W 0h 1 0 BUF_DIR_CTRL_G PIO_49 R W 1h Controls the direction of GPIO 0 both input and output are not selected can be used for analog 1 input mode 2 output mode 3 shouldnt be used 2 16 340 Register 4C7h offset 4C7h reset 0h Figure 2 2603 Register ...

Page 1107: ...ster 4CBh offset 4CBh reset 0h Figure 2 2605 Register 4CBh 7 6 5 4 3 2 1 0 ACTIV_BIR_DIR_CTRL_GPIO_50 reserved R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2621 Register 4CB Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_50 R W 0h Control to indicate whether the GPIO_50 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use th...

Page 1108: ...CF Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_51 R W 0h Control to indicate whether the GPIO_51 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use the IO for 3 pin SPI B2 SDIO 5 Use the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 345 Register 4D0h offset 4D0h reset 1h Figure 2 ...

Page 1109: ...e the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 347 Register 4D4h offset 4D4h reset 1h Figure 2 2610 Register 4D4h 7 6 5 4 3 2 1 0 reserved reserved BUF_DIR_CTRL_GPIO_53 R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2626 Register 4D4 Field Descriptions Bit Field Type Reset Description ...

Page 1110: ...d Write W Write only n value after reset Table 2 2628 Register 4D8 Field Descriptions Bit Field Type Reset Description 7 5 reserved R W 0h 4 2 reserved R W 0h 1 0 BUF_DIR_CTRL_G PIO_54 R W 1h Controls the direction of GPIO 0 both input and output are not selected can be used for analog 1 input mode 2 output mode 3 shouldnt be used 2 16 350 Register 4DBh offset 4DBh reset 0h Figure 2 2613 Register ...

Page 1111: ...ster 4DFh offset 4DFh reset 0h Figure 2 2615 Register 4DFh 7 6 5 4 3 2 1 0 ACTIV_BIR_DIR_CTRL_GPIO_55 reserved R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2631 Register 4DF Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_55 R W 0h Control to indicate whether the GPIO_55 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use th...

Page 1112: ...E3 Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_56 R W 0h Control to indicate whether the GPIO_56 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use the IO for 3 pin SPI B2 SDIO 5 Use the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 355 Register 4E4h offset 4E4h reset 1h Figure 2 ...

Page 1113: ...e the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 357 Register 4E8h offset 4E8h reset 1h Figure 2 2620 Register 4E8h 7 6 5 4 3 2 1 0 reserved reserved BUF_DIR_CTRL_GPIO_58 R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2636 Register 4E8 Field Descriptions Bit Field Type Reset Description ...

Page 1114: ...d Write W Write only n value after reset Table 2 2638 Register 4EC Field Descriptions Bit Field Type Reset Description 7 5 reserved R W 0h 4 2 reserved R W 0h 1 0 BUF_DIR_CTRL_G PIO_59 R W 1h Controls the direction of GPIO 0 both input and output are not selected can be used for analog 1 input mode 2 output mode 3 shouldnt be used 2 16 360 Register 4EFh offset 4EFh reset 0h Figure 2 2623 Register ...

Page 1115: ...ster 4F3h offset 4F3h reset 0h Figure 2 2625 Register 4F3h 7 6 5 4 3 2 1 0 ACTIV_BIR_DIR_CTRL_GPIO_60 reserved R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2641 Register 4F3 Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_60 R W 0h Control to indicate whether the GPIO_60 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use th...

Page 1116: ...F7 Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_61 R W 0h Control to indicate whether the GPIO_61 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use the IO for 3 pin SPI B2 SDIO 5 Use the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 365 Register 4F8h offset 4F8h reset 1h Figure 2 ...

Page 1117: ...e the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 367 Register 4FCh offset 4FCh reset 1h Figure 2 2630 Register 4FCh 7 6 5 4 3 2 1 0 reserved reserved BUF_DIR_CTRL_GPIO_63 R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2646 Register 4FC Field Descriptions Bit Field Type Reset Description ...

Page 1118: ...d Write W Write only n value after reset Table 2 2648 Register 500 Field Descriptions Bit Field Type Reset Description 7 5 reserved R W 0h 4 2 reserved R W 0h 1 0 BUF_DIR_CTRL_G PIO_64 R W 1h Controls the direction of GPIO 0 both input and output are not selected can be used for analog 1 input mode 2 output mode 3 shouldnt be used 2 16 370 Register 503h offset 503h reset 0h Figure 2 2633 Register ...

Page 1119: ...ster 507h offset 507h reset 0h Figure 2 2635 Register 507h 7 6 5 4 3 2 1 0 ACTIV_BIR_DIR_CTRL_GPIO_65 reserved R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2651 Register 507 Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_65 R W 0h Control to indicate whether the GPIO_65 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use th...

Page 1120: ...0B Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_66 R W 0h Control to indicate whether the GPIO_66 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use the IO for 3 pin SPI B2 SDIO 5 Use the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 375 Register 50Ch offset 50Ch reset 1h Figure 2 ...

Page 1121: ...e the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 377 Register 510h offset 510h reset 1h Figure 2 2640 Register 510h 7 6 5 4 3 2 1 0 reserved reserved BUF_DIR_CTRL_GPIO_68 R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2656 Register 510 Field Descriptions Bit Field Type Reset Description ...

Page 1122: ...d Write W Write only n value after reset Table 2 2658 Register 514 Field Descriptions Bit Field Type Reset Description 7 5 reserved R W 0h 4 2 reserved R W 0h 1 0 BUF_DIR_CTRL_G PIO_69 R W 1h Controls the direction of GPIO 0 both input and output are not selected can be used for analog 1 input mode 2 output mode 3 shouldnt be used 2 16 380 Register 517h offset 517h reset 0h Figure 2 2643 Register ...

Page 1123: ...ster 51Bh offset 51Bh reset 0h Figure 2 2645 Register 51Bh 7 6 5 4 3 2 1 0 ACTIV_BIR_DIR_CTRL_GPIO_70 reserved R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2661 Register 51B Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_70 R W 0h Control to indicate whether the GPIO_70 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use th...

Page 1124: ...1F Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_71 R W 0h Control to indicate whether the GPIO_71 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use the IO for 3 pin SPI B2 SDIO 5 Use the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 385 Register 520h offset 520h reset 1h Figure 2 ...

Page 1125: ...e the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 387 Register 524h offset 524h reset 1h Figure 2 2650 Register 524h 7 6 5 4 3 2 1 0 reserved reserved BUF_DIR_CTRL_GPIO_73 R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2666 Register 524 Field Descriptions Bit Field Type Reset Description ...

Page 1126: ...d Write W Write only n value after reset Table 2 2668 Register 528 Field Descriptions Bit Field Type Reset Description 7 5 reserved R W 0h 4 2 reserved R W 0h 1 0 BUF_DIR_CTRL_G PIO_74 R W 1h Controls the direction of GPIO 0 both input and output are not selected can be used for analog 1 input mode 2 output mode 3 shouldnt be used 2 16 390 Register 52Bh offset 52Bh reset 0h Figure 2 2653 Register ...

Page 1127: ...ster 52Fh offset 52Fh reset 0h Figure 2 2655 Register 52Fh 7 6 5 4 3 2 1 0 ACTIV_BIR_DIR_CTRL_GPIO_75 reserved R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2671 Register 52F Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_75 R W 0h Control to indicate whether the GPIO_75 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use th...

Page 1128: ...33 Field Descriptions Bit Field Type Reset Description 3 1 ACTIV_BIR_DIR_C TRL_GPIO_76 R W 0h Control to indicate whether the GPIO_76 needs dynamic ouptu t enabling 0 to 3 Static direction 4 Use the IO for 3 pin SPI B2 SDIO 5 Use the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 395 Register 534h offset 534h reset 1h Figure 2 ...

Page 1129: ...e the IO for 4 pin SPI B2 SDO 6 Use the IO for 3 pin SPI B1 SDIO 7 use the IO for 4 pin SPI B1 SDO 0 0 reserved R W 0h 2 16 397 Register 538h offset 538h reset 1h Figure 2 2660 Register 538h 7 6 5 4 3 2 1 0 reserved reserved BUF_DIR_CTRL_GPIO_78 R W 0h R W 0h R W 1h LEGEND R W Read Write W Write only n value after reset Table 2 2676 Register 538 Field Descriptions Bit Field Type Reset Description ...

Page 1130: ...d Write W Write only n value after reset Table 2 2678 Register 53C Field Descriptions Bit Field Type Reset Description 7 5 reserved R W 0h 4 2 reserved R W 0h 1 0 BUF_DIR_CTRL_G PIO_79 R W 1h Controls the direction of GPIO 0 both input and output are not selected can be used for analog 1 input mode 2 output mode 3 shouldnt be used 2 16 400 Register 53Fh offset 53Fh reset 0h Figure 2 2663 Register ...

Page 1131: ...L_INT BIPI_SPIB1_S DI OVR_INTBIPI_ SPIB1_SDI R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2681 Register 701 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTBIPI _SPIB1_SDI R W 1h control to select whether the input function intbipi_spib1_sdi needs to be overriden ot not 1 indicates override 0 0 OVR_INTBIPI_SPI B1_SDI R W 0h override value for intb...

Page 1132: ...08h offset 708h reset 0h Figure 2 2668 Register 708h 7 6 5 4 3 2 1 0 POL_INTBIPO_ SPIB1_SDO R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2684 Register 708 Field Descriptions Bit Field Type Reset Description 0 0 POL_INTBIPO_SPI B1_SDO R W 0h polarity control for intbipo_spib1_sdo 0 indicates pass through from GPIO when selected 1 indicates inverted signal 2 16 406 Register ...

Page 1133: ...after reset Table 2 2687 Register 70D Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTBIP O_SPIB2_SDO R W 1h control to select whether the input function intbipo_spib2_sdo needs to be overriden ot not 1 indicates override 0 0 OVR_INTBIPO_SP IB2_SDO R W 0h override value for intbipo_spib2_sdo when ovr_sel_intbipo_spib2_sdo is made high 2 16 409 Register 800h offset 800h reset 0h ...

Page 1134: ...TPI_SP IB2_CLK R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2690 Register 804 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_SPIB2 _CLK R W 0h select control for intpi_spib2_clk 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_SPIB2 _CLK R W 0h polarity control for intpi_spi...

Page 1135: ...INT PI_RXAB_DSA _GAIN_0 OVR_INTPI_R XAB_DSA_GAI N_0 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2693 Register 819 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ RXAB_DSA_GAIN _0 R W 1h control to select whether the input function intpi_rxab_dsa_gain_0 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_RXAB _DSA_GAIN_0 R W 0h ove...

Page 1136: ...AIN _2 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2696 Register 820 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_RXAB _DSA_GAIN_2 R W 0h select control for intpi_rxab_dsa_gain_2 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_RXAB _DSA_GAIN_2 R W 0h polarity control for...

Page 1137: ...INT PI_RXAB_DSA _GAIN_3 OVR_INTPI_R XAB_DSA_GAI N_3 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2699 Register 825 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ RXAB_DSA_GAIN _3 R W 1h control to select whether the input function intpi_rxab_dsa_gain_3 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_RXAB _DSA_GAIN_3 R W 0h ove...

Page 1138: ...AIN _5 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2702 Register 82C Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_RXAB _DSA_GAIN_5 R W 0h select control for intpi_rxab_dsa_gain_5 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_RXAB _DSA_GAIN_5 R W 0h polarity control for...

Page 1139: ... PI_RXAB_DSA _GAINSEL OVR_INTPI_R XAB_DSA_GAI NSEL R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2705 Register 831 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ RXAB_DSA_GAIN SEL R W 1h control to select whether the input function intpi_rxab_dsa_gainsel needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_RXAB _DSA_GAINSEL R W 0h o...

Page 1140: ...A_GAIN _0 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2708 Register 838 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_RXCD _DSA_GAIN_0 R W 0h select control for intpi_rxcd_dsa_gain_0 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_RXCD _DSA_GAIN_0 R W 0h polarity control ...

Page 1141: ...INT PI_RXCD_DSA _GAIN_1 OVR_INTPI_R XCD_DSA_GAI N_1 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2711 Register 83D Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ RXCD_DSA_GAIN _1 R W 1h control to select whether the input function intpi_rxcd_dsa_gain_1 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_RXCD _DSA_GAIN_1 R W 0h ove...

Page 1142: ...AIN _3 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2714 Register 844 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_RXCD _DSA_GAIN_3 R W 0h select control for intpi_rxcd_dsa_gain_3 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_RXCD _DSA_GAIN_3 R W 0h polarity control for...

Page 1143: ...INT PI_RXCD_DSA _GAIN_4 OVR_INTPI_R XCD_DSA_GAI N_4 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2717 Register 849 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ RXCD_DSA_GAIN _4 R W 1h control to select whether the input function intpi_rxcd_dsa_gain_4 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_RXCD _DSA_GAIN_4 R W 0h ove...

Page 1144: ...EL R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2720 Register 850 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_RXCD _DSA_GAINSEL R W 0h select control for intpi_rxcd_dsa_gainsel 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_RXCD _DSA_GAINSEL R W 0h polarity control for ...

Page 1145: ...SEL_INT PI_RXCD_DSA _GAINLEN OVR_INTPI_R XCD_DSA_GAI NLEN R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2723 Register 855 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ RXCD_DSA_GAIN LEN R W 1h control to select whether the input function intpi_rxcd_dsa_gainlen needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_RXCD _DSA_GAINLEN R...

Page 1146: ...AIN_ 1 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2726 Register 85C Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_RXA_ DSA_GAIN_1 R W 0h select control for intpi_rxa_dsa_gain_1 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_RXA_ DSA_GAIN_1 R W 0h polarity control for in...

Page 1147: ...SEL_INT PI_RXA_DSA_ GAIN_2 OVR_INTPI_R XA_DSA_GAIN _2 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2729 Register 861 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ RXA_DSA_GAIN_2 R W 1h control to select whether the input function intpi_rxa_dsa_gain_2 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_RXA_ DSA_GAIN_2 R W 0h overr...

Page 1148: ...AIN_ 1 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2732 Register 868 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_RXB_ DSA_GAIN_1 R W 0h select control for intpi_rxb_dsa_gain_1 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_RXB_ DSA_GAIN_1 R W 0h polarity control for in...

Page 1149: ...SEL_INT PI_RXB_DSA_ GAIN_2 OVR_INTPI_R XB_DSA_GAIN _2 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2735 Register 86D Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ RXB_DSA_GAIN_2 R W 1h control to select whether the input function intpi_rxb_dsa_gain_2 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_RXB_ DSA_GAIN_2 R W 0h overr...

Page 1150: ...AIN_ 1 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2738 Register 874 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_RXC_ DSA_GAIN_1 R W 0h select control for intpi_rxc_dsa_gain_1 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_RXC_ DSA_GAIN_1 R W 0h polarity control for in...

Page 1151: ...EL_INT PI_RXC_DSA_ GAIN_2 OVR_INTPI_R XC_DSA_GAIN _2 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2741 Register 879 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ RXC_DSA_GAIN_ 2 R W 1h control to select whether the input function intpi_rxc_dsa_gain_2 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_RXC_ DSA_GAIN_2 R W 0h overr...

Page 1152: ...AIN_ 1 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2744 Register 880 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_RXD_ DSA_GAIN_1 R W 0h select control for intpi_rxd_dsa_gain_1 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_RXD_ DSA_GAIN_1 R W 0h polarity control for in...

Page 1153: ...3 2 1 0 OVR_SEL_INT PI_RXD_DSA_ GAIN_2 OVR_INTPI_R XD_DSA_GAIN _2 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2747 Register 885 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ RXD_DSA_GAIN_ 2 R W 1h control to select whether the input function intpi_rxd_dsa_gain_2 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_RXD_ DSA_GAIN_2...

Page 1154: ...TPI_SP IB1_CLK R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2750 Register 89C Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_SPIB1 _CLK R W 0h select control for intpi_spib1_clk 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_SPIB1 _CLK R W 0h polarity control for intpi_spi...

Page 1155: ...INT PI_ADC_SYNC _N_AB_0 OVR_INTPI_A DC_SYNC_N_ AB_0 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2753 Register 8A1 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ ADC_SYNC_N_AB _0 R W 1h control to select whether the input function intpi_adc_sync_n_ab_0 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_ADC_ SYNC_N_AB_0 R W 0h ove...

Page 1156: ..._A B_2 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2756 Register 8A8 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_ADC_ SYNC_N_AB_2 R W 0h select control for intpi_adc_sync_n_ab_2 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_ADC_ SYNC_N_AB_2 R W 0h polarity control for...

Page 1157: ...INT PI_ADC_SYNC _N_CD_0 OVR_INTPI_A DC_SYNC_N_ CD_0 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2759 Register 8AD Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ ADC_SYNC_N_CD _0 R W 1h control to select whether the input function intpi_adc_sync_n_cd_0 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_ADC_ SYNC_N_CD_0 R W 0h ove...

Page 1158: ..._C D_2 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2762 Register 8B4 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_ADC_ SYNC_N_CD_2 R W 0h select control for intpi_adc_sync_n_cd_2 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_ADC_ SYNC_N_CD_2 R W 0h polarity control for...

Page 1159: ...3 2 1 0 OVR_SEL_INT PI_TDD_EN_T XA OVR_INTPI_T DD_EN_TXA R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2765 Register 8B9 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ TDD_EN_TXA R W 1h control to select whether the input function intpi_tdd_en_txa needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_TDD_ EN_TXA R W 0h override value...

Page 1160: ...D D_EN_TXC R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2768 Register 8C0 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_TDD_ EN_TXC R W 0h select control for intpi_tdd_en_txc 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_TDD_ EN_TXC R W 0h polarity control for intpi_tdd_...

Page 1161: ... 1 0 OVR_SEL_INT PI_TDD_EN_T XD OVR_INTPI_T DD_EN_TXD R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2771 Register 8C5 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ TDD_EN_TXD R W 1h control to select whether the input function intpi_tdd_en_txd needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_TDD_ EN_TXD R W 0h override value fo...

Page 1162: ...D_EN_FBCD R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2774 Register 8CC Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_TDD_ EN_FBCD R W 0h select control for intpi_tdd_en_fbcd 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_TDD_ EN_FBCD R W 0h polarity control for intpi_td...

Page 1163: ...0 OVR_SEL_INT PI_GLOBAL_P DN OVR_INTPI_G LOBAL_PDN R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2777 Register 905 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ GLOBAL_PDN R W 1h control to select whether the input function intpi_global_pdn needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_GLOB AL_PDN R W 0h override value for o...

Page 1164: ...B_LOOP_1 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2780 Register 90C Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_TX_FB _LOOP_1 R W 0h select control for intpi_tx_fb_loop_1 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_TX_FB _LOOP_1 R W 0h polarity control for intpi_...

Page 1165: ...0 OVR_SEL_INT PI_TX_FB_LO OP_2 OVR_INTPI_TX _FB_LOOP_2 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2783 Register 911 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ TX_FB_LOOP_2 R W 1h control to select whether the input function intpi_tx_fb_loop_2 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_TX_F B_LOOP_2 R W 0h override v...

Page 1166: ...END R W Read Write W Write only n value after reset Table 2 2786 Register 954 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_RXA_ AGC_PIN_FREEZ E R W 0h select control for intpi_rxa_agc_pin_freeze 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_RXA_ AGC_PIN_FREEZ E R W 0h polarity control for intpi_rxa_ag...

Page 1167: ...offset 959h reset 2h Figure 2 2773 Register 959h 7 6 5 4 3 2 1 0 OVR_SEL_INT PI_RXB_AGC_ PIN_FREEZE OVR_INTPI_R XB_AGC_PIN_ FREEZE R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2789 Register 959 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ RXB_AGC_PIN_F REEZE R W 1h control to select whether the input function intpi_rxb_agc_pin_freeze needs ...

Page 1168: ...eeds to be overriden ot not 1 indicates override 0 0 OVR_INTPI_RXC_ AGC_PIN_FREEZ E R W 0h override value for ovr_sel_intpi_rxc_agc_pin_freeze is made high 2 16 513 Register 960h offset 960h reset 0h Figure 2 2776 Register 960h 7 6 5 4 3 2 1 0 SEL_INTPI_RXD_AGC_PIN_FR EEZE POL_INTPI_RX D_AGC_PIN_F REEZE R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2792 Register 960 ...

Page 1169: ... Bit Field Type Reset Description 2 1 SEL_INTPI_FBAB_ AGC_PIN_FREEZ E R W 0h select control for intpi_fbab_agc_pin_freeze 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_FBAB _AGC_PIN_FREEZ E R W 0h polarity control for intpi_fbab_agc_pin_freeze 0 indicates pass through from GPIO when selected 1 indicates inverted signal 2 ...

Page 1170: ... 3 2 1 0 OVR_SEL_INT PI_FBCD_AGC _PIN_FREEZE OVR_INTPI_FB CD_AGC_PIN_ FREEZE R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2797 Register 9D1 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ FBCD_AGC_PIN_ FREEZE R W 1h control to select whether the input function intpi_fbcd_agc_pin_freeze needs to be overriden ot not 1 indicates override 0 0 OVR_...

Page 1171: ...D D_EN_RXB R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2800 Register 9D8 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_TDD_ EN_RXB R W 0h select control for intpi_tdd_en_rxb 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_TDD_ EN_RXB R W 0h polarity control for intpi_tdd_...

Page 1172: ...3 2 1 0 OVR_SEL_INT PI_TDD_EN_R XC OVR_INTPI_T DD_EN_RXC R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2803 Register 9DD Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ TDD_EN_RXC R W 1h control to select whether the input function intpi_tdd_en_rxc needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_TDD_ EN_RXC R W 0h override value...

Page 1173: ..._0 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2806 Register 9E4 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_RX_G AIN_SW_0 R W 0h select control for intpi_rx_gain_sw_0 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_RX_G AIN_SW_0 R W 0h polarity control for intpi_rx_gai...

Page 1174: ...0 OVR_SEL_INT PI_RX_GAIN_S W_1 OVR_INTPI_R X_GAIN_SW_1 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2809 Register 9E9 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ RX_GAIN_SW_1 R W 1h control to select whether the input function intpi_rx_gain_sw_1 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_RX_G AIN_SW_1 R W 0h override v...

Page 1175: ...AIN_SW_3 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2812 Register 9F0 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_RX_G AIN_SW_3 R W 0h select control for intpi_rx_gain_sw_3 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_RX_G AIN_SW_3 R W 0h polarity control for intpi_...

Page 1176: ...0 OVR_SEL_INT PI_TX_GAIN_S W_0 OVR_INTPI_TX _GAIN_SW_0 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2815 Register A0D Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ TX_GAIN_SW_0 R W 1h control to select whether the input function intpi_tx_gain_sw_0 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_TX_G AIN_SW_0 R W 0h override v...

Page 1177: ...AIN_SW_2 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2818 Register A14 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_TX_G AIN_SW_2 R W 0h select control for intpi_tx_gain_sw_2 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_TX_G AIN_SW_2 R W 0h polarity control for intpi_...

Page 1178: ... 1 0 OVR_SEL_INT PI_TX_GAIN_S W_3 OVR_INTPI_TX _GAIN_SW_3 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2821 Register A19 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ TX_GAIN_SW_3 R W 1h control to select whether the input function intpi_tx_gain_sw_3 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_TX_G AIN_SW_3 R W 0h overrid...

Page 1179: ..._NCOSEL_1 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2824 Register A20 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_FB_N COSEL_1 R W 0h select control for intpi_fb_ncosel_1 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_FB_N COSEL_1 R W 0h polarity control for intpi_fb...

Page 1180: ... 1 0 OVR_SEL_INT PI_FB_NCOSE L_2 OVR_INTPI_FB _NCOSEL_2 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2827 Register A25 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ FB_NCOSEL_2 R W 1h control to select whether the input function intpi_fb_ncosel_2 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_FB_N COSEL_2 R W 0h override val...

Page 1181: ..._NCOSEL_0 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2830 Register A2C Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_RX_N COSEL_0 R W 0h select control for intpi_rx_ncosel_0 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_RX_N COSEL_0 R W 0h polarity control for intpi_rx...

Page 1182: ... 1 0 OVR_SEL_INT PI_RX_NCOSE L_1 OVR_INTPI_R X_NCOSEL_1 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2833 Register A31 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ RX_NCOSEL_1 R W 1h control to select whether the input function intpi_rx_ncosel_1 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_RX_N COSEL_1 R W 0h override val...

Page 1183: ..._NCOSEL_3 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2836 Register A38 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_RX_N COSEL_3 R W 0h select control for intpi_rx_ncosel_3 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_RX_N COSEL_3 R W 0h polarity control for intpi_rx...

Page 1184: ... 1 0 OVR_SEL_INT PI_TX_NCOSE L_0 OVR_INTPI_TX _NCOSEL_0 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2839 Register A3D Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ TX_NCOSEL_0 R W 1h control to select whether the input function intpi_tx_ncosel_0 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPI_TX_N COSEL_0 R W 0h override val...

Page 1185: ..._NCOSEL_2 R W 0h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2842 Register A44 Field Descriptions Bit Field Type Reset Description 2 1 SEL_INTPI_TX_N COSEL_2 R W 0h select control for intpi_tx_ncosel_2 0 indicates take from parallel GPIO 1 indicates take from Serial LVDS GPIO 2 indicates take from Serdes GPIO 0 0 POL_INTPI_TX_N COSEL_2 R W 0h polarity control for intpi_tx...

Page 1186: ...6 Register A49h offset A49h reset 2h Figure 2 2829 Register A49h 7 6 5 4 3 2 1 0 OVR_SEL_INT PI_TX_NCOSE L_3 OVR_INTPI_TX _NCOSEL_3 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2845 Register A49 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPI_ TX_NCOSEL_3 R W 1h control to select whether the input function intpi_tx_ncosel_3 needs to be override...

Page 1187: ...0 OVR_SEL_INT PO_SPIB1_SD O OVR_INTPO_S PIB1_SDO R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2848 Register 1005 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPO_ SPIB1_SDO R W 1h control to select whether the input function intpo_spib1_sdo needs to be overriden ot not 1 indicates override 0 0 OVR_INTPO_SPIB 1_SDO R W 0h override value for intpo...

Page 1188: ...et 106Ch reset 0h Figure 2 2835 Register 106Ch 7 6 5 4 3 2 1 0 POL_INTPO_R XA_PKDET_0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2851 Register 106C Field Descriptions Bit Field Type Reset Description 0 0 POL_INTPO_RXA_ PKDET_0 R W 0h polarity control for intpo_rxa_pkdet_0 0 indicates pass through from GPIO when selected 1 indicates inverted signal 2 16 573 Register 106Dh...

Page 1189: ...EL_INT PO_RXA_PKD ET_1 OVR_INTPO_R XA_PKDET_1 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2854 Register 1071 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPO_ RXA_PKDET_1 R W 1h control to select whether the input function intpo_rxa_pkdet_1 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPO_RXA _PKDET_1 R W 0h override value for in...

Page 1190: ...8h offset 1078h reset 0h Figure 2 2841 Register 1078h 7 6 5 4 3 2 1 0 POL_INTPO_R XA_PKDET_3 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2857 Register 1078 Field Descriptions Bit Field Type Reset Description 0 0 POL_INTPO_RXA_ PKDET_3 R W 0h polarity control for intpo_rxa_pkdet_3 0 indicates pass through from GPIO when selected 1 indicates inverted signal 2 16 579 Registe...

Page 1191: ...EL_INT PO_RXB_PKD ET_0 OVR_INTPO_R XB_PKDET_0 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2860 Register 107D Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPO_ RXB_PKDET_0 R W 1h control to select whether the input function intpo_rxb_pkdet_0 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPO_RXB _PKDET_0 R W 0h override value for in...

Page 1192: ...4h offset 1084h reset 0h Figure 2 2847 Register 1084h 7 6 5 4 3 2 1 0 POL_INTPO_R XB_PKDET_2 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2863 Register 1084 Field Descriptions Bit Field Type Reset Description 0 0 POL_INTPO_RXB_ PKDET_2 R W 0h polarity control for intpo_rxb_pkdet_2 0 indicates pass through from GPIO when selected 1 indicates inverted signal 2 16 585 Registe...

Page 1193: ...EL_INT PO_RXB_PKD ET_3 OVR_INTPO_R XB_PKDET_3 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2866 Register 1089 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPO_ RXB_PKDET_3 R W 1h control to select whether the input function intpo_rxb_pkdet_3 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPO_RXB _PKDET_3 R W 0h override value for in...

Page 1194: ...0h offset 1090h reset 0h Figure 2 2853 Register 1090h 7 6 5 4 3 2 1 0 POL_INTPO_R XC_PKDET_1 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2869 Register 1090 Field Descriptions Bit Field Type Reset Description 0 0 POL_INTPO_RXC _PKDET_1 R W 0h polarity control for intpo_rxc_pkdet_1 0 indicates pass through from GPIO when selected 1 indicates inverted signal 2 16 591 Registe...

Page 1195: ...EL_INT PO_RXC_PKD ET_2 OVR_INTPO_R XC_PKDET_2 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2872 Register 1095 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPO_ RXC_PKDET_2 R W 1h control to select whether the input function intpo_rxc_pkdet_2 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPO_RXC _PKDET_2 R W 0h override value for in...

Page 1196: ...Ch offset 109Ch reset 0h Figure 2 2859 Register 109Ch 7 6 5 4 3 2 1 0 POL_INTPO_R XD_PKDET_0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2875 Register 109C Field Descriptions Bit Field Type Reset Description 0 0 POL_INTPO_RXD _PKDET_0 R W 0h polarity control for intpo_rxd_pkdet_0 0 indicates pass through from GPIO when selected 1 indicates inverted signal 2 16 597 Registe...

Page 1197: ...EL_INT PO_RXD_PKD ET_1 OVR_INTPO_R XD_PKDET_1 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2878 Register 10A1 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPO_ RXD_PKDET_1 R W 1h control to select whether the input function intpo_rxd_pkdet_1 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPO_RXD _PKDET_1 R W 0h override value for in...

Page 1198: ...8h offset 10A8h reset 0h Figure 2 2865 Register 10A8h 7 6 5 4 3 2 1 0 POL_INTPO_R XD_PKDET_3 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2881 Register 10A8 Field Descriptions Bit Field Type Reset Description 0 0 POL_INTPO_RXD _PKDET_3 R W 0h polarity control for intpo_rxd_pkdet_3 0 indicates pass through from GPIO when selected 1 indicates inverted signal 2 16 603 Registe...

Page 1199: ... 3 2 1 0 OVR_SEL_INT PO_ALARM_1 OVR_INTPO_A LARM_1 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2884 Register 10BD Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPO_ ALARM_1 R W 1h control to select whether the input function intpo_alarm_1 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPO_ALA RM_1 R W 0h override value for intpo_ala...

Page 1200: ...71 Register 10C4h 7 6 5 4 3 2 1 0 POL_INTPO_D AC_SYNC_N_ AB_0 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2887 Register 10C4 Field Descriptions Bit Field Type Reset Description 0 0 POL_INTPO_DAC _SYNC_N_AB_0 R W 0h polarity control for intpo_dac_sync_n_ab_0 0 indicates pass through from GPIO when selected 1 indicates inverted signal 2 16 609 Register 10C5h offset 10C5h re...

Page 1201: ...YN C_N_AB_1 OVR_INTPO_D AC_SYNC_N_ AB_1 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2890 Register 10C9 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPO_ DAC_SYNC_N_AB _1 R W 1h control to select whether the input function intpo_dac_sync_n_ab_1 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPO_DAC _SYNC_N_AB_1 R W 0h override value...

Page 1202: ...set 10F4h reset 0h Figure 2 2877 Register 10F4h 7 6 5 4 3 2 1 0 POL_INTPO_D AC_SYNC_N_ CD_1 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2893 Register 10F4 Field Descriptions Bit Field Type Reset Description 0 0 POL_INTPO_DAC _SYNC_N_CD_1 R W 0h polarity control for intpo_dac_sync_n_cd_1 0 indicates pass through from GPIO when selected 1 indicates inverted signal 2 16 615 ...

Page 1203: ...NT PO_FBAB_PK DET_0 OVR_INTPO_F BAB_PKDET_0 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2896 Register 11A5 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPO_ FBAB_PKDET_0 R W 1h control to select whether the input function intpo_fbab_pkdet_0 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPO_FBA B_PKDET_0 R W 0h override value for i...

Page 1204: ...h offset 11ACh reset 0h Figure 2 2883 Register 11ACh 7 6 5 4 3 2 1 0 POL_INTPO_F BAB_PKDET_2 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2899 Register 11AC Field Descriptions Bit Field Type Reset Description 0 0 POL_INTPO_FBAB _PKDET_2 R W 0h polarity control for intpo_fbab_pkdet_2 0 indicates pass through from GPIO when selected 1 indicates inverted signal 2 16 621 Regis...

Page 1205: ...NT PO_FBAB_PK DET_3 OVR_INTPO_F BAB_PKDET_3 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2902 Register 11B1 Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPO_ FBAB_PKDET_3 R W 1h control to select whether the input function intpo_fbab_pkdet_3 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPO_FBA B_PKDET_3 R W 0h override value for i...

Page 1206: ...h offset 11B8h reset 0h Figure 2 2889 Register 11B8h 7 6 5 4 3 2 1 0 POL_INTPO_F BCD_PKDET_1 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2905 Register 11B8 Field Descriptions Bit Field Type Reset Description 0 0 POL_INTPO_FBC D_PKDET_1 R W 0h polarity control for intpo_fbcd_pkdet_1 0 indicates pass through from GPIO when selected 1 indicates inverted signal 2 16 627 Regis...

Page 1207: ...NT PO_FBCD_PK DET_2 OVR_INTPO_F BCD_PKDET_2 R W 1h R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 2908 Register 11BD Field Descriptions Bit Field Type Reset Description 1 1 OVR_SEL_INTPO_ FBCD_PKDET_2 R W 1h control to select whether the input function intpo_fbcd_pkdet_2 needs to be overriden ot not 1 indicates override 0 0 OVR_INTPO_FBC D_PKDET_2 R W 0h override value for i...

Page 1208: ...ates override 0 0 OVR_INTPO_FBC D_PKDET_3 R W 0h override value for intpo_fbcd_pkdet_3 when ovr_sel_intpo_fbcd_pkdet_3 is made high 2 16 632 Register 13E9h offset 13E9h reset 0h Figure 2 2895 Register 13E9h 7 6 5 4 3 2 1 0 READ_INTPO_ SPIB1_SDO R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2911 Register 13E9 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPO_S...

Page 1209: ... 7 6 5 4 3 2 1 0 READ_INTPO_ RXA_PKDET_1 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2914 Register 1404 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPO_RX A_PKDET_1 R 0h read only register for function intpo_rxa_pkdet_1 2 16 636 Register 1405h offset 1405h reset 0h Figure 2 2899 Register 1405h 7 6 5 4 3 2 1 0 READ_INTPO_ RXA_PKDET_2 R 0h LEGEND R W Read W...

Page 1210: ...escription 0 0 READ_INTPO_RX B_PKDET_0 R 0h read only register for function intpo_rxb_pkdet_0 2 16 639 Register 1408h offset 1408h reset 0h Figure 2 2902 Register 1408h 7 6 5 4 3 2 1 0 READ_INTPO_ RXB_PKDET_1 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2918 Register 1408 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPO_RX B_PKDET_1 R 0h read only register ...

Page 1211: ... 7 6 5 4 3 2 1 0 READ_INTPO_ RXC_PKDET_0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2921 Register 140B Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPO_RX C_PKDET_0 R 0h read only register for function intpo_rxc_pkdet_0 2 16 643 Register 140Ch offset 140Ch reset 0h Figure 2 2906 Register 140Ch 7 6 5 4 3 2 1 0 READ_INTPO_ RXC_PKDET_1 R 0h LEGEND R W Read W...

Page 1212: ...escription 0 0 READ_INTPO_RX C_PKDET_3 R 0h read only register for function intpo_rxc_pkdet_3 2 16 646 Register 140Fh offset 140Fh reset 0h Figure 2 2909 Register 140Fh 7 6 5 4 3 2 1 0 READ_INTPO_ RXD_PKDET_0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2925 Register 140F Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPO_RX D_PKDET_0 R 0h read only register ...

Page 1213: ...er 1412h 7 6 5 4 3 2 1 0 READ_INTPO_ RXD_PKDET_3 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2928 Register 1412 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPO_RX D_PKDET_3 R 0h read only register for function intpo_rxd_pkdet_3 2 16 650 Register 1417h offset 1417h reset 0h Figure 2 2913 Register 1417h 7 6 5 4 3 2 1 0 READ_INTPO_ ALARM_1 R 0h LEGEND R W Re...

Page 1214: ...PO_DA C_SYNC_N_AB_0 R 0h read only register for function intpo_dac_sync_n_ab_0 2 16 653 Register 141Ah offset 141Ah reset 0h Figure 2 2916 Register 141Ah 7 6 5 4 3 2 1 0 READ_INTPO_ DAC_SYNC_N _AB_1 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2932 Register 141A Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPO_DA C_SYNC_N_AB_1 R 0h read only register for fu...

Page 1215: ...dac_sync_n_cd_0 2 16 656 Register 1425h offset 1425h reset 0h Figure 2 2919 Register 1425h 7 6 5 4 3 2 1 0 READ_INTPO_ DAC_SYNC_N _CD_1 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2935 Register 1425 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPO_DA C_SYNC_N_CD_1 R 0h read only register for function intpo_dac_sync_n_cd_1 2 16 657 Register 1433h offset 143...

Page 1216: ...6 659 Register 143Dh offset 143Dh reset 0h Figure 2 2922 Register 143Dh 7 6 5 4 3 2 1 0 READ_INTPO_ AVS_SENSOR _OUT R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2938 Register 143D Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPO_AV S_SENSOR_OUT R 0h read only register for function intpo_avs_sensor_out 2 16 660 Register 143Eh offset 143Eh reset 0h Figure 2 2...

Page 1217: ...ab_pkdet_0 2 16 662 Register 1452h offset 1452h reset 0h Figure 2 2925 Register 1452h 7 6 5 4 3 2 1 0 READ_INTPO_ FBAB_PKDET_ 1 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2941 Register 1452 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPO_FB AB_PKDET_1 R 0h read only register for function intpo_fbab_pkdet_1 2 16 663 Register 1453h offset 1453h reset 0h Fi...

Page 1218: ...ab_pkdet_3 2 16 665 Register 1455h offset 1455h reset 0h Figure 2 2928 Register 1455h 7 6 5 4 3 2 1 0 READ_INTPO_ FBCD_PKDET _0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2944 Register 1455 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPO_FB CD_PKDET_0 R 0h read only register for function intpo_fbcd_pkdet_0 2 16 666 Register 1456h offset 1456h reset 0h Fi...

Page 1219: ...o_fbcd_pkdet_2 2 16 668 Register 1458h offset 1458h reset 0h Figure 2 2931 Register 1458h 7 6 5 4 3 2 1 0 READ_INTPO_ FBCD_PKDET _3 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2947 Register 1458 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPO_FB CD_PKDET_3 R 0h read only register for function intpo_fbcd_pkdet_3 2 16 669 Register 17D0h offset 17D0h reset 0...

Page 1220: ...6 671 Register 17D6h offset 17D6h reset 0h Figure 2 2934 Register 17D6h 7 6 5 4 3 2 1 0 READ_INTPI_ RXAB_DSA_G AIN_0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2950 Register 17D6 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXA B_DSA_GAIN_0 R 0h read only register for function intpi_rxab_dsa_gain_0 2 16 672 Register 17D7h offset 17D7h reset 0h Figure ...

Page 1221: ...gain_2 2 16 674 Register 17D9h offset 17D9h reset 0h Figure 2 2937 Register 17D9h 7 6 5 4 3 2 1 0 READ_INTPI_ RXAB_DSA_G AIN_3 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2953 Register 17D9 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXA B_DSA_GAIN_3 R 0h read only register for function intpi_rxab_dsa_gain_3 2 16 675 Register 17DAh offset 17DAh reset ...

Page 1222: ...n_5 2 16 677 Register 17DCh offset 17DCh reset 0h Figure 2 2940 Register 17DCh 7 6 5 4 3 2 1 0 READ_INTPI_ RXAB_DSA_G AINSEL R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2956 Register 17DC Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXA B_DSA_GAINSEL R 0h read only register for function intpi_rxab_dsa_gainsel 2 16 678 Register 17DDh offset 17DDh reset ...

Page 1223: ...gain_0 2 16 680 Register 17DFh offset 17DFh reset 0h Figure 2 2943 Register 17DFh 7 6 5 4 3 2 1 0 READ_INTPI_ RXCD_DSA_G AIN_1 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2959 Register 17DF Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXC D_DSA_GAIN_1 R 0h read only register for function intpi_rxcd_dsa_gain_1 2 16 681 Register 17E0h offset 17E0h reset ...

Page 1224: ...gain_3 2 16 683 Register 17E2h offset 17E2h reset 0h Figure 2 2946 Register 17E2h 7 6 5 4 3 2 1 0 READ_INTPI_ RXCD_DSA_G AIN_4 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2962 Register 17E2 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXC D_DSA_GAIN_4 R 0h read only register for function intpi_rxcd_dsa_gain_4 2 16 684 Register 17E3h offset 17E3h reset ...

Page 1225: ...gainsel 2 16 686 Register 17E5h offset 17E5h reset 0h Figure 2 2949 Register 17E5h 7 6 5 4 3 2 1 0 READ_INTPI_ RXCD_DSA_G AINLEN R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2965 Register 17E5 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXC D_DSA_GAINLEN R 0h read only register for function intpi_rxcd_dsa_gainlen 2 16 687 Register 17E6h offset 17E6h re...

Page 1226: ..._gain_1 2 16 689 Register 17E8h offset 17E8h reset 0h Figure 2 2952 Register 17E8h 7 6 5 4 3 2 1 0 READ_INTPI_ RXA_DSA_GAI N_2 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2968 Register 17E8 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXA _DSA_GAIN_2 R 0h read only register for function intpi_rxa_dsa_gain_2 2 16 690 Register 17E9h offset 17E9h reset 0h...

Page 1227: ..._gain_1 2 16 692 Register 17EBh offset 17EBh reset 0h Figure 2 2955 Register 17EBh 7 6 5 4 3 2 1 0 READ_INTPI_ RXB_DSA_GAI N_2 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2971 Register 17EB Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXB _DSA_GAIN_2 R 0h read only register for function intpi_rxb_dsa_gain_2 2 16 693 Register 17ECh offset 17ECh reset 0h...

Page 1228: ..._gain_1 2 16 695 Register 17EEh offset 17EEh reset 0h Figure 2 2958 Register 17EEh 7 6 5 4 3 2 1 0 READ_INTPI_ RXC_DSA_GAI N_2 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2974 Register 17EE Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXC _DSA_GAIN_2 R 0h read only register for function intpi_rxc_dsa_gain_2 2 16 696 Register 17EFh offset 17EFh reset 0h...

Page 1229: ...rxd_dsa_gain_1 2 16 698 Register 17F1h offset 17F1h reset 0h Figure 2 2961 Register 17F1h 7 6 5 4 3 2 1 0 READ_INTPI_ RXD_DSA_GAI N_2 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2977 Register 17F1 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXD _DSA_GAIN_2 R 0h read only register for function intpi_rxd_dsa_gain_2 2 16 699 Register 17F6h offset 17F6h r...

Page 1230: ...6 701 Register 17F8h offset 17F8h reset 0h Figure 2 2964 Register 17F8h 7 6 5 4 3 2 1 0 READ_INTPI_A DC_SYNC_N_ AB_0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2980 Register 17F8 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_ADC _SYNC_N_AB_0 R 0h read only register for function intpi_adc_sync_n_ab_0 2 16 702 Register 17F9h offset 17F9h reset 0h Figure ...

Page 1231: ...n_ab_2 2 16 704 Register 17FBh offset 17FBh reset 0h Figure 2 2967 Register 17FBh 7 6 5 4 3 2 1 0 READ_INTPI_A DC_SYNC_N_ CD_0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2983 Register 17FB Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_ADC _SYNC_N_CD_0 R 0h read only register for function intpi_adc_sync_n_cd_0 2 16 705 Register 17FCh offset 17FCh reset ...

Page 1232: ...ster 17FEh 7 6 5 4 3 2 1 0 READ_INTPI_T DD_EN_TXA R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2986 Register 17FE Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_TDD _EN_TXA R 0h read only register for function intpi_tdd_en_txa 2 16 708 Register 17FFh offset 17FFh reset 0h Figure 2 2971 Register 17FFh 7 6 5 4 3 2 1 0 READ_INTPI_T DD_EN_TXB R 0h LEGEND R W ...

Page 1233: ...escription 0 0 READ_INTPI_TDD _EN_TXD R 0h read only register for function intpi_tdd_en_txd 2 16 711 Register 1802h offset 1802h reset 0h Figure 2 2974 Register 1802h 7 6 5 4 3 2 1 0 READ_INTPI_T DD_EN_FBAB R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2990 Register 1802 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_TDD _EN_FBAB R 0h read only register fo...

Page 1234: ...ter 1805h offset 1805h reset 0h Figure 2 2977 Register 1805h 7 6 5 4 3 2 1 0 READ_INTPI_ RXA_ALC_INP UT_0_B0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2993 Register 1805 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXA _ALC_INPUT_0_B 0 R 0h read only register for function intpi_rxa_alc_input_0_b0 2 16 715 Register 1806h offset 1806h reset 0h Figure 2...

Page 1235: ...0 2 16 717 Register 1808h offset 1808h reset 0h Figure 2 2980 Register 1808h 7 6 5 4 3 2 1 0 READ_INTPI_ RXB_ALC_INP UT_0_B0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2996 Register 1808 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXB _ALC_INPUT_0_B 0 R 0h read only register for function intpi_rxb_alc_input_0_b0 2 16 718 Register 1809h offset 1809h r...

Page 1236: ...0 2 16 720 Register 180Bh offset 180Bh reset 0h Figure 2 2983 Register 180Bh 7 6 5 4 3 2 1 0 READ_INTPI_ RXC_ALC_INP UT_0_B0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 2999 Register 180B Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXC _ALC_INPUT_0_B 0 R 0h read only register for function intpi_rxc_alc_input_0_b0 2 16 721 Register 180Ch offset 180Ch r...

Page 1237: ...0 2 16 723 Register 180Eh offset 180Eh reset 0h Figure 2 2986 Register 180Eh 7 6 5 4 3 2 1 0 READ_INTPI_ RXD_ALC_INP UT_0_B0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3002 Register 180E Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXD _ALC_INPUT_0_B 0 R 0h read only register for function intpi_rxd_alc_input_0_b0 2 16 724 Register 180Fh offset 180Fh r...

Page 1238: ...intpi_rxd_alc_input_2_b0 2 16 726 Register 1811h offset 1811h reset 0h Figure 2 2989 Register 1811h 7 6 5 4 3 2 1 0 READ_INTPI_ GLOBAL_PDN R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3005 Register 1811 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_GLO BAL_PDN R 0h read only register for function intpi_global_pdn 2 16 727 Register 1812h offset 1812h rese...

Page 1239: ...7 6 5 4 3 2 1 0 READ_INTPI_T X_FB_LOOP_2 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3008 Register 1814 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_TX_ FB_LOOP_2 R 0h read only register for function intpi_tx_fb_loop_2 2 16 730 Register 1815h offset 1815h reset 0h Figure 2 2993 Register 1815h 7 6 5 4 3 2 1 0 READ_INTPI_T X_FB_LOOP_3 R 0h LEGEND R W Rea...

Page 1240: ...A _ALC_INPUT_3_B 0 R 0h read only register for function intpi_rxa_alc_input_3_b0 2 16 733 Register 181Ch offset 181Ch reset 0h Figure 2 2996 Register 181Ch 7 6 5 4 3 2 1 0 READ_INTPI_ RXB_ALC_INP UT_3_B0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3012 Register 181C Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXB _ALC_INPUT_3_B 0 R 0h read only regist...

Page 1241: ...3_b0 2 16 736 Register 181Fh offset 181Fh reset 0h Figure 2 2999 Register 181Fh 7 6 5 4 3 2 1 0 READ_INTPI_I NTERRUPT0_ TOPMCU R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3015 Register 181F Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_INTE RRUPT0_TOPMC U R 0h read only register for function intpi_interrupt0_topcm4 2 16 737 Register 1820h offset 1820h r...

Page 1242: ..._topcm4 2 16 739 Register 1822h offset 1822h reset 0h Figure 2 3002 Register 1822h 7 6 5 4 3 2 1 0 READ_INTPI_I NTERRUPT3_ TOPMCU R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3018 Register 1822 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_INTE RRUPT3_TOPMC U R 0h read only register for function intpi_interrupt3_topcm4 2 16 740 Register 1823h offset 1823...

Page 1243: ...742 Register 1825h offset 1825h reset 0h Figure 2 3005 Register 1825h 7 6 5 4 3 2 1 0 READ_INTPI_ RXA_AGC_PIN _FREEZE R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3021 Register 1825 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXA _AGC_PIN_FREEZ E R 0h read only register for function intpi_rxa_agc_pin_freeze 2 16 743 Register 1826h offset 1826h reset 0h...

Page 1244: ..._pin_freeze 2 16 745 Register 1828h offset 1828h reset 0h Figure 2 3008 Register 1828h 7 6 5 4 3 2 1 0 READ_INTPI_ RXD_AGC_PIN _FREEZE R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3024 Register 1828 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXD _AGC_PIN_FREEZ E R 0h read only register for function intpi_rxd_agc_pin_freeze 2 16 746 Register 1829h offs...

Page 1245: ...48 Register 182Bh offset 182Bh reset 0h Figure 2 3011 Register 182Bh 7 6 5 4 3 2 1 0 READ_INTPI_ RXA_ALC_INP UT_0_B1 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3027 Register 182B Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXA _ALC_INPUT_0_B 1 R 0h read only register for function intpi_rxa_alc_input_0_b1 2 16 749 Register 182Ch offset 182Ch reset 0h ...

Page 1246: ...1 2 16 751 Register 182Eh offset 182Eh reset 0h Figure 2 3014 Register 182Eh 7 6 5 4 3 2 1 0 READ_INTPI_ RXB_ALC_INP UT_0_B1 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3030 Register 182E Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXB _ALC_INPUT_0_B 1 R 0h read only register for function intpi_rxb_alc_input_0_b1 2 16 752 Register 182Fh offset 182Fh r...

Page 1247: ...1 2 16 754 Register 1831h offset 1831h reset 0h Figure 2 3017 Register 1831h 7 6 5 4 3 2 1 0 READ_INTPI_ RXC_ALC_INP UT_0_B1 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3033 Register 1831 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXC _ALC_INPUT_0_B 1 R 0h read only register for function intpi_rxc_alc_input_0_b1 2 16 755 Register 1832h offset 1832h r...

Page 1248: ...1 2 16 757 Register 1834h offset 1834h reset 0h Figure 2 3020 Register 1834h 7 6 5 4 3 2 1 0 READ_INTPI_ RXD_ALC_INP UT_0_B1 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3036 Register 1834 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXD _ALC_INPUT_0_B 1 R 0h read only register for function intpi_rxd_alc_input_0_b1 2 16 758 Register 1835h offset 1835h r...

Page 1249: ...1 2 16 760 Register 1837h offset 1837h reset 0h Figure 2 3023 Register 1837h 7 6 5 4 3 2 1 0 READ_INTPI_ RXA_ALC_INP UT_3_B1 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3039 Register 1837 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXA _ALC_INPUT_3_B 1 R 0h read only register for function intpi_rxa_alc_input_3_b1 2 16 761 Register 1838h offset 1838h r...

Page 1250: ...3_b1 2 16 763 Register 183Ah offset 183Ah reset 0h Figure 2 3026 Register 183Ah 7 6 5 4 3 2 1 0 READ_INTPI_ RXD_ALC_INP UT_3_B1 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3042 Register 183A Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RXD _ALC_INPUT_3_B 1 R 0h read only register for function intpi_rxd_alc_input_3_b1 2 16 764 Register 183Bh offset 183B...

Page 1251: ...ut_1 2 16 766 Register 183Dh offset 183Dh reset 0h Figure 2 3029 Register 183Dh 7 6 5 4 3 2 1 0 READ_INTPI_F BAB_ALC_INP UT_2 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3045 Register 183D Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_FBA B_ALC_INPUT_2 R 0h read only register for function intpi_fbab_alc_input_2 2 16 767 Register 183Eh offset 183Eh reset...

Page 1252: ...ut_1 2 16 769 Register 1840h offset 1840h reset 0h Figure 2 3032 Register 1840h 7 6 5 4 3 2 1 0 READ_INTPI_F BCD_ALC_INP UT_2 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3048 Register 1840 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_FBC D_ALC_INPUT_2 R 0h read only register for function intpi_fbcd_alc_input_2 2 16 770 Register 1841h offset 1841h reset...

Page 1253: ...772 Register 1843h offset 1843h reset 0h Figure 2 3035 Register 1843h 7 6 5 4 3 2 1 0 READ_INTPI_F BAB_AGC_PIN _FREEZE R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3051 Register 1843 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_FBA B_AGC_PIN_FRE EZE R 0h read only register for function intpi_fbab_agc_pin_freeze 2 16 773 Register 1844h offset 1844h reset...

Page 1254: ...6h 7 6 5 4 3 2 1 0 READ_INTPI_T DD_EN_RXB R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3054 Register 1846 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_TDD _EN_RXB R 0h read only register for function intpi_tdd_en_rxb 2 16 776 Register 1847h offset 1847h reset 0h Figure 2 3039 Register 1847h 7 6 5 4 3 2 1 0 READ_INTPI_T DD_EN_RXC R 0h LEGEND R W Read Wri...

Page 1255: ...ption 0 0 READ_INTPI_RX_ GAIN_SW_0 R 0h read only register for function intpi_rx_gain_sw_0 2 16 779 Register 184Ah offset 184Ah reset 0h Figure 2 3042 Register 184Ah 7 6 5 4 3 2 1 0 READ_INTPI_ RX_GAIN_SW_ 1 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3058 Register 184A Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RX_ GAIN_SW_1 R 0h read only register ...

Page 1256: ... Register 184Dh offset 184Dh reset 0h Figure 2 3045 Register 184Dh 7 6 5 4 3 2 1 0 READ_INTPI_ GPIO_PKDET_ WIN_RXA R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3061 Register 184D Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_GPI O_PKDET_WIN_R XA R 0h read only register for function intpi_gpio_pkdet_win_rxa 2 16 783 Register 184Eh offset 184Eh reset 0h Fi...

Page 1257: ...2 16 785 Register 1850h offset 1850h reset 0h Figure 2 3048 Register 1850h 7 6 5 4 3 2 1 0 READ_INTPI_ GPIO_PKDET_ WIN_RXD R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3064 Register 1850 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_GPI O_PKDET_WIN_R XD R 0h read only register for function intpi_gpio_pkdet_win_rxd 2 16 786 Register 1851h offset 1851h res...

Page 1258: ...pi_gpio_pkdet_win_fbcd 2 16 788 Register 1853h offset 1853h reset 0h Figure 2 3051 Register 1853h 7 6 5 4 3 2 1 0 READ_INTPI_T X_GAIN_SW_0 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3067 Register 1853 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_TX_ GAIN_SW_0 R 0h read only register for function intpi_tx_gain_sw_0 2 16 789 Register 1854h offset 1854h ...

Page 1259: ... 7 6 5 4 3 2 1 0 READ_INTPI_T X_GAIN_SW_3 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3070 Register 1856 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_TX_ GAIN_SW_3 R 0h read only register for function intpi_tx_gain_sw_3 2 16 792 Register 1857h offset 1857h reset 0h Figure 2 3055 Register 1857h 7 6 5 4 3 2 1 0 READ_INTPI_F B_NCOSEL_0 R 0h LEGEND R W Rea...

Page 1260: ...escription 0 0 READ_INTPI_FB_ NCOSEL_2 R 0h read only register for function intpi_fb_ncosel_2 2 16 795 Register 185Ah offset 185Ah reset 0h Figure 2 3058 Register 185Ah 7 6 5 4 3 2 1 0 READ_INTPI_F B_NCOSEL_3 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3074 Register 185A Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_FB_ NCOSEL_3 R 0h read only register ...

Page 1261: ..._rx_ncosel_1 2 16 798 Register 185Dh offset 185Dh reset 0h Figure 2 3061 Register 185Dh 7 6 5 4 3 2 1 0 READ_INTPI_ RX_NCOSEL_ 2 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3077 Register 185D Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_RX_ NCOSEL_2 R 0h read only register for function intpi_rx_ncosel_2 2 16 799 Register 185Eh offset 185Eh reset 0h Fig...

Page 1262: ... 7 6 5 4 3 2 1 0 READ_INTPI_T X_NCOSEL_1 R 0h LEGEND R W Read Write W Write only n value after reset Table 2 3080 Register 1860 Field Descriptions Bit Field Type Reset Description 0 0 READ_INTPI_TX_ NCOSEL_1 R 0h read only register for function intpi_tx_ncosel_1 2 16 802 Register 1861h offset 1861h reset 0h Figure 2 3065 Register 1861h 7 6 5 4 3 2 1 0 READ_INTPI_T X_NCOSEL_2 R 0h LEGEND R W Read W...

Page 1263: ...et Description 7 0 TEST_REG1 7 0 R W 0h 2 16 805 Register 1881h offset 1881h reset 0h Figure 2 3068 Register 1881h 7 6 5 4 3 2 1 0 TEST_REG1 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 3084 Register 1881 Field Descriptions Bit Field Type Reset Description 7 0 TEST_REG1 15 8 R W 0h 2 16 806 Register 1882h offset 1882h reset 0h Figure 2 3069 Register 1882h 7 6 5 4 3 2 ...

Page 1264: ... 7 0 R W 0h 2 16 809 Register 1885h offset 1885h reset 0h Figure 2 3072 Register 1885h 7 6 5 4 3 2 1 0 TEST_REG0 15 8 R W 0h LEGEND R W Read Write W Write only n value after reset Table 2 3088 Register 1885 Field Descriptions Bit Field Type Reset Description 7 0 TEST_REG0 15 8 R W 0h 2 16 810 Register 1886h offset 1886h reset 0h Figure 2 3073 Register 1886h 7 6 5 4 3 2 1 0 TEST_REG0 23 16 R W 0h L...

Page 1265: ...1265 SBAU337 May 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated Serial Interface Register Maps Table 2 3090 Register 1887 Field Descriptions Bit Field Type Reset Description 7 0 TEST_REG0 31 24 R W 0h ...

Page 1266: ...rising edge of SCLK Data is output from the device on the falling edge of SCLK The SPI registers except for global register GLOBAL0 and GLOBAL1 are reset by writing a 1 to GLOBAL_SOFT_RESET in global register GLOBAL0 Each read write operation is framed by signal SDEN Serial Data Enable Bar asserted low The first two bytes is the instruction cycle which identifies the following data transfer cycle ...

Page 1267: ...SDEN SDI SDO A15 A14 A13 A2 A1 A0 D7 D1 D2 D3 D4 D5 D6 D0 1 4 3 2 15 14 16 17 23 22 21 20 19 18 24 D7 D1 D2 D3 D4 D5 D6 D0 SCLK Addr N Addr N 1 ascending Addr N 1 descending 25 31 30 29 28 27 26 32 R W www ti com Appendix A 1267 SBAU337 May 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated Appendix SPI Interface Figure A 3 SPI Streaming Write Example Figure A 4 SPI S...

Page 1268: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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