IO Wrap Register Map
1155
SBAU337 – May 2020
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.16.473 Register 8A0h (offset = 8A0h) [reset = 0h]
Figure 2-2736. Register 8A0h
7
6
5
4
3
2
1
0
SEL_INTPI_ADC_SYNC_N_AB_
0
POL_INTPI_AD
C_SYNC_N_A
B_0
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2752. Register 8A0 Field Descriptions
Bit
Field
Type
Reset
Description
2-1
SEL_INTPI_ADC_
SYNC_N_AB_0
R/W
0h
select control for intpi_adc_sync_n_ab_0. 0 indicates take
from parallel GPIO 1 indicates take from Serial LVDS GPIO 2
indicates take from Serdes GPIO
0-0
POL_INTPI_ADC_
SYNC_N_AB_0
R/W
0h
polarity control for intpi_adc_sync_n_ab_0. 0 indicates pass
through from GPIO when selected 1 indicates inverted signal
2.16.474 Register 8A1h (offset = 8A1h) [reset = 2h]
Figure 2-2737. Register 8A1h
7
6
5
4
3
2
1
0
OVR_SEL_INT
PI_ADC_SYNC
_N_AB_0
OVR_INTPI_A
DC_SYNC_N_
AB_0
R/W-1h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2753. Register 8A1 Field Descriptions
Bit
Field
Type
Reset
Description
1-1
OVR_SEL_INTPI_
ADC_SYNC_N_AB
_0
R/W
1h
control to select whether the input function
intpi_adc_sync_n_ab_0 needs to be overriden ot not. 1
indicates override.
0-0
OVR_INTPI_ADC_
SYNC_N_AB_0
R/W
0h
override value for ovr_sel_intpi_adc_sync_n_ab_0 is made
high
2.16.475 Register 8A4h (offset = 8A4h) [reset = 0h]
Figure 2-2738. Register 8A4h
7
6
5
4
3
2
1
0
SEL_INTPI_ADC_SYNC_N_AB_
1
POL_INTPI_AD
C_SYNC_N_A
B_1
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2754. Register 8A4 Field Descriptions
Bit
Field
Type
Reset
Description
2-1
SEL_INTPI_ADC_
SYNC_N_AB_1
R/W
0h
select control for intpi_adc_sync_n_ab_1. 0 indicates take
from parallel GPIO 1 indicates take from Serial LVDS GPIO 2
indicates take from Serdes GPIO
0-0
POL_INTPI_ADC_
SYNC_N_AB_1
R/W
0h
polarity control for intpi_adc_sync_n_ab_1. 0 indicates pass
through from GPIO when selected 1 indicates inverted signal