Contents
vi
2−1.
ADSDeSer-50EVM Overview
2-2
2−2.
Default and Alternate Configurations for Programming the ADSDeSer-50EVM
2-3
2−3.
Default Configurations for FPGA Pins on the ADSDeSer-50EVM
2-4
2−4.
Output Connectors for the ADSDeSer-50EVM
2-5
2−5.
Orientation of Ground Connections for the ADSDeSer-50EVM
2-5
3−1.
ADSDeSer-50EVM—Layer 1 (Top)
3-2
3−2.
ADSDeSer-50EVM—Layer 2 (Power)
3-3
3−3.
ADSDeSer-50EVM—Layer 3 (Mid Signal)
3-4
3−4.
ADSDeSer-50EVM—Layer 4 (Ground)
3-5
3−5.
ADSDeSer-50EVM—Layer 5 (Bottom)
3-6
3−6.
ADSDeSer-50EVM—Schematic
3-7
1−1.
A/D Converter Models Supported by the ADSDeSer-50EVM
1-2
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3−1.
Bill of Materials
3-8
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Summary of Contents for ADSDeSer-50EVM
Page 1: ...January 2004 User s Guide SBAU091 High Speed Converter Products...
Page 19: ...Board Layout 3 2 3 1 Board Layout Figure 3 1 ADSDeSer 50EVM Layer 1 Top...
Page 20: ...Board Layout 3 3 Schematic and Layout Figure 3 2 ADSDeSer 50EVM Layer 2 Power...
Page 21: ...Board Layout 3 4 Figure 3 3 ADSDeSer 50EVM Layer 3 Mid Signal...
Page 22: ...Board Layout 3 5 Schematic and Layout Figure 3 4 ADSDeSer 50EVM Layer 4 Ground...
Page 23: ...Board Layout 3 6 Figure 3 5 ADSDeSer 50EVM Layer 5 Bottom...