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FPGA and PROM Bypass and Configuration
2-3
Board Configuration
2.1.3
FPGA and PROM Bypass and Configuration
J11 and J12 can be used to bypass the PROM and/or bypass the FPGA when
programming. The following diagram shows the default and different configu-
rations for programming.
Figure 2−2.
Default and Alternate Configurations for Programming the ADSDeSer-50EVM
J 11
J 12
PROM Bypass
FPGA Bypass
PROM
Normal Configuration
(default) and
Orientation
J 11
J 12
PROM Bypass
FPGA Bypass
PROM Bypassed
J 11
J 12
PROM Bypass
FPGA Bypass
FPGA Bypassed
J 11
J 12
PROM Bypass
FPGA Bypass
PROM and FPGA
Bypassed
Summary of Contents for ADSDeSer-50EVM
Page 1: ...January 2004 User s Guide SBAU091 High Speed Converter Products...
Page 19: ...Board Layout 3 2 3 1 Board Layout Figure 3 1 ADSDeSer 50EVM Layer 1 Top...
Page 20: ...Board Layout 3 3 Schematic and Layout Figure 3 2 ADSDeSer 50EVM Layer 2 Power...
Page 21: ...Board Layout 3 4 Figure 3 3 ADSDeSer 50EVM Layer 3 Mid Signal...
Page 22: ...Board Layout 3 5 Schematic and Layout Figure 3 4 ADSDeSer 50EVM Layer 4 Ground...
Page 23: ...Board Layout 3 6 Figure 3 5 ADSDeSer 50EVM Layer 5 Bottom...