FPGA Configuration Pins
2-4
2.1.4
FPGA Configuration Pins
JP1 is used to program the FPGA. The following diagram shows the default
configuration. Further information on the different modes is available in the Xi-
linx Virtex II Handbook.
Figure 2−3.
Default Configurations for FPGA Pins on the ADSDeSer-50EVM
JP1
HSWAP_EN
M2
M1
M0
2.1.5
Pushbuttons
The ADSDeSer-50EVM has two pushbuttons. S1 (PROGRAM) is used to
download from the PROM to the FPGA. When the program is finished down-
loading, indicator DS2 will turn on. S2 (FPGA_RST) is used to reset the down-
loaded program in the FPGA.
Summary of Contents for ADSDeSer-50EVM
Page 1: ...January 2004 User s Guide SBAU091 High Speed Converter Products...
Page 19: ...Board Layout 3 2 3 1 Board Layout Figure 3 1 ADSDeSer 50EVM Layer 1 Top...
Page 20: ...Board Layout 3 3 Schematic and Layout Figure 3 2 ADSDeSer 50EVM Layer 2 Power...
Page 21: ...Board Layout 3 4 Figure 3 3 ADSDeSer 50EVM Layer 3 Mid Signal...
Page 22: ...Board Layout 3 5 Schematic and Layout Figure 3 4 ADSDeSer 50EVM Layer 4 Ground...
Page 23: ...Board Layout 3 6 Figure 3 5 ADSDeSer 50EVM Layer 5 Bottom...