Texas Instruments ADSDeSer-50EVM User Manual Download Page 21 | Manualshive

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Texas Instruments ADSDeSer-50EVM User Manual Download Page 21

Board Layout

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Figure 3−3. ADSDeSer-50EVM—Layer 3 (Mid Signal)

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Summary of Contents for ADSDeSer-50EVM

Page 1: ...January 2004 User s Guide SBAU091 High Speed Converter Products...

Page 2: ...ute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual pro...

Page 3: ...handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s r...

Page 4: ...here is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 60 C The EVM is design...

Page 5: ...he document revision which is current at the time of the writing of this User s Guide To obtain a copy of the following TI documents visit our website at http www ti com or call the Texas In struments...

Page 6: ...suant to sub part J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equip ment in other environments may cause interf...

Page 7: ...onfiguration 2 1 2 1 I O Connectors 2 2 2 1 1 Input 2 2 2 1 2 JTAG 2 2 2 1 3 FPGA and PROM Bypass and Configuration 2 3 2 1 4 FPGA Configuration Pins 2 4 2 1 5 Pushbuttons 2 4 2 1 6 Output Connectors...

Page 8: ...ctors for the ADSDeSer 50EVM 2 5 2 5 Orientation of Ground Connections for the ADSDeSer 50EVM 2 5 3 1 ADSDeSer 50EVM Layer 1 Top 3 2 3 2 ADSDeSer 50EVM Layer 2 Power 3 3 3 3 ADSDeSer 50EVM Layer 3 Mid...

Page 9: ...r 50EVM is an evaluation fixture designed for the ADS527x family of data converters It is an eight channel LVDS deserializer Topic Page 1 1 Introduction 1 2 1 2 Features 1 2 1 3 Power Supply 1 3 1 4 I...

Page 10: ...embedded a synchronous clock out put is provided separately along with the eight channels of data The ADSDeSer 50EVM evaluation board will support the analog to digital converter ADC models listed in...

Page 11: ...he main board power and a 1 8V to 3 3V supply for the output driver supply An onboard regulator supplies 1 5V to power the FPGA 1 4 Indicators There are two LEDs on the board DS1 is used to show the b...

Page 12: ...2 1 Board Configuration This chapter describes the inputs controls and circuit design of the ADSDeSer 50EVM in detail Topic Page 2 1 I O Connectors 2 2 2 2 Start up Sequence 2 6 Chapter 2...

Page 13: ...50EVM Overview JTAG BYPASS PINS PROGRAM PUSHBUTTON INP UT CONFIGURATION PINS FPGA RESET PUSHBUTTON 2 1 1 Input The input connector Con1 is used to connect one of the ADS527xEVM LVDS output converter...

Page 14: ...lowing diagram shows the default and different configu rations for programming Figure 2 2 Default and Alternate Configurations for Programming the ADSDeSer 50EVM J 11 J 12 PROM Bypass FPGA Bypass PROM...

Page 15: ...is available in the Xi linx Virtex II Handbook Figure 2 3 Default Configurations for FPGA Pins on the ADSDeSer 50EVM JP1 HSWAP_EN M2 M1 M0 2 1 5 Pushbuttons The ADSDeSer 50EVM has two pushbuttons S1 P...

Page 16: ...ADS527x through a serial interface Refer to the respective ADS527x datasheet and the ADS527xEVM for more details If the standard configuration for the data converter is used then the following diagra...

Page 17: ...ply power to the ADSDeSer 50EVM board and look for the Power On DS1 LED and DS2 LED to illuminate If DS2 does not illuminate press the Program S1 pushbutton If no LEDs illuminate contact TI customer s...

Page 18: ...ic diagram and bill of materials for the ADSDeSer 50EVM Note Board layouts are not to scale These are intended to show how the board is laid out they are not intended to be used for manufacturing ADSS...

Page 19: ...Board Layout 3 2 3 1 Board Layout Figure 3 1 ADSDeSer 50EVM Layer 1 Top...

Page 20: ...Board Layout 3 3 Schematic and Layout Figure 3 2 ADSDeSer 50EVM Layer 2 Power...

Page 21: ...Board Layout 3 4 Figure 3 3 ADSDeSer 50EVM Layer 3 Mid Signal...

Page 22: ...Board Layout 3 5 Schematic and Layout Figure 3 4 ADSDeSer 50EVM Layer 4 Ground...

Page 23: ...Board Layout 3 6 Figure 3 5 ADSDeSer 50EVM Layer 5 Bottom...

Page 24: ...V C C O _2 H 11 V C C O _2 G 11 BANK0 B A N K 2 BANK4 BANK 6 XC2V250 6FG256C U2B G N D T1 6 G N D T1 G N D R 15 G N D R 2 G N D P1 4 G N D P3 G N D L11 G N D L6 G N D K1 0 G N D K9 G N D K8 G N D K7 G...

Page 25: ...sistor R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 3 47 F AVX TAJA476K004R 3216 size Tantalum Capacitor C1 C2 C4 3 330 0603 Chip Resistor R1 R2 R3 R4 1 CLK 0 1 Terminal strip Square J13 1 DTC114EET1 On Se...

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