Texas Instruments ADS1282, Manual

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System Clock
(f )
CLK
SYNC
DRDY
t
CSHD
t
SCSU
t
SYNC
1/f
DATA
t
SPWH
t
SPWL
System Clock
(f )
CLK
SYNC Command
SYNC Pin
DRDY
(Pulse-Sync)
t
SPWL
New Data
Ready
t
CSHD
t
SPWH
DRDY
(Continuous-Sync)
DOUT
New Data
Ready
t
DR
t
SCSU
t
DR
ADS1282
www.ti.com SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015
9.18 Pulse-Sync Mode Continuous-Sync Mode (continued)
In Pulse-sync mode, the ADS1282 stops and restarts
Note that a SYNC clock input should be applied after
the conversion process when a sync event occurs (by
the Continuous-Sync mode is set. The first rising
pin or command). When the sync event occurs, the
edge of SYNC then causes a synchronization.
device resets the internal memory; DRDY goes high
(pulse SYNC mode) otherwise in Continuous SYNC
mode, DRDY continues to toggle, and after the digital
filter has settled, new conversion data are available,
as shown in
Figure 47 and Table 10 .
Note that resynchronization occurs on the next rising
CLK edge after the rising edge of the SYNC pin or
after the eighth rising SCLK edge for opcode SYNC
commands. To be effective, the SYNC opcode should
be broadcast to all devices simultaneously.
9.19 Continuous-Sync Mode
In Continuous-sync mode, either a single sync pulse
or a continuous clock may be applied. When a single
sync pulse is applied (rising edge), the device
behaves similar to the Pulse-sync mode. However, in
this mode, DRDY continues to toggle unaffected but
Figure 47. Pulse-Sync Timing, Continuous-Sync
the DOUT output is held low until data are ready, 63
Timing with Single Sync
DRDY periods later. When the conversion data are
non-zero, new conversion data are ready (as shown
in
Figure 47 ).
When a continuous clock is applied to the SYNC pin,
the period must be an integral multiple of the output
data rate or the device re-synchronizes. Note that
synchronization results in the restarting of the digital
filter and an interruption of 63 readings (refer to
Table 10 ).
When the sync input is first applied, the device re-
synchronizes (under the condition t
SYNC
≠ N/f
DATA
).
DRDY continues to output but DOUT is held low until
the new data are ready. Then, if SYNC is applied
again and the period matches an integral multiple of
Figure 48. Continuous-Sync Timing with Sync
the output data rate, the device freely runs without re-
Clock
synchronization. Note that the phase of the applied
clock and output data rate (DRDY) are not matched
because of the initial delay of DRDY after SYNC is
first
applied. Figure 48 shows the timing for
Continuous-Sync mode.
Table 10. Pulse-Sync Timing for Figure 47 and Figure 48
PARAMETER DESCRIPTION MIN MAX UNITS
t
SYNC
SYNC period
(1)
1 Infinite n/f
DATA
t
CSHD
CLK to SYNC hold time to not latch on CLK edge 10 ns
t
SCSU
SYNC to CLK setup time to latch on CLK edge 10 ns
t
SPWH, L
SYNC pulse width, high or low 2 1/f
CLK
Time for data ready (SINC filter) See Appendix , Table 35
t
DR
Time for data ready (FIR filter) 62.98046875/f
DATA
+ 468/f
CLK
(1) Continuous-Sync mode; a free-running SYNC clock input without causing re-synchronization.
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