CLK
SYNC
MCLK
(1)
M0
M1
t
MCD0, 1
t
SCSU
t
CSHD
t
CMD
t
SYMD
ESD
Diodes
ESD
Diodes
11.5pF
R
= 85k
W
(f
= 1.024MHz)
EFF
MOD
AVDD
AVSS
VREFP
VREFN
R
=
EFF
f
C
´
MOD
X
1
SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015
9.12 Modulator Output Mode
9.13 Voltage Reference Inputs
(VREFP, VREFN)
The modulator digital stream output is accessible
directly, bypassing and disabling the internal digital
The voltage reference for the ADS1282 is the
filter. The modulator output mode is activated by
differential voltage between VREFP and VREFN:
setting the CONFIG0 register bits FILTR[1:0] = 00.
V
REF
= VREFP – VREFN. The reference inputs use a
Pins M0 and M1 then become the modulator data
structure similar to that of the analog inputs with the
outputs and the MCLK becomes the modulator clock
circuitry of the reference inputs shown in
.
output. When not in the modulator mode, these pins
The
average
load
presented
by
the
switched
are inputs and must be tied.
capacitor reference input can be modeled with an
effective differential impedance of R
EFF
= t
SAMPLE
/C
IN
The modulator output is composed of three signals:
(t
SAMPLE
= 1/f
MOD
). Note that the effective impedance
one output for the modulator clock (MCLK) and two
of the reference inputs loads the external reference.
outputs for the modulator data (M0 and M1). The
modulator clock output rate is f
MOD
(f
CLK
/ 4).
Synchronization resets the MCLK phase, as shown in
. The SYNC input is latched on the rising
edge of CLK. The MCLK resets and the next rising
edge of MCLK occurs three or five CLK periods later,
as shown in
The modulator output data are two bits wide, which
must be merged together before being filtered. Use
the time domain equation of
to merge the
data outputs.
Figure 36. Simplified Reference Input Circuit
(1) MCLK = f
CLK
/ 4.
Figure 35. Modulator Mode Timing
Table 4. Modulator Output Timing For
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
t
MCD0, 1
MCLK rising edge to M0, M1 valid propagation delay
(1)
100
ns
CLK rising edge to MCLK rising edge reset time (after
t
CMD
3
1/f
CLK
synchronization)
t
CSHD
CLK to SYNC hold time to not latch on CLK edge
10
ns
t
SCSU
SYNC to CLK setup time to latch on CLK edge
10
ns
t
SYMD
SYNC to stable bit stream
16
1/f
MOD
(1)
Load on M0 and M1 = 20pF || 100k
Ω
.
Copyright © 2007–2015, Texas Instruments Incorporated
17
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