0
20
40
Frequency (Hz)
35
30
25
20
15
10
5
GroupDelay(1/f
)
D
A
T
A
60
80
100
120
140
160
180
200
Linear Phase Filter
Minimum Phase Filter
HPF[1:0] = 65,536 1
-
cos
+ sin
1
w
-
N
N
w
cos
w
N
1
2
-
SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015
Group Delay and Step Response (continued)
Group Delay and Step Response (continued)
9.15.2 Minimum Phase Response
9.15.3 HPF Stage
The minimum phase filter provides a short delay from
The last stage of the ADS1282 filter block is a first-
the arrival of an input signal to the output, but the
order HPF implemented as an IIR structure. This filter
relationship (phase) is not constant versus frequency,
stage blocks dc signals and rolls off low-frequency
as shown in
. The filter phase is selected by
components below the cut-off frequency. The transfer
the PHS bit, as
shows.
function for the filter is shown in
of the
The high-pass corner frequency is programmed by
registers HPF[1:0], in hexadecimal.
is
used to set the high-pass corner frequency.
lists example values for the high-pass filter.
(9)
Where:
HPF = High-pass filter register value (converted
to hexadecimal)
ω
N
= 2
π
f
HP
/f
DATA
(normalized frequency,
radians)
Figure 44. FIR Group Delay (f
DATA
= 500Hz)
f
HP
= High-pass corner frequency (Hz)
f
DATA
= Data rate (Hz)
Table 8. FIR Phase Selection
Table 9. High-Pass Filter Value Examples
PHS BIT
FILTER PHASE
f
HP
(Hz)
DATA RATE (SPS)
HPF[1:0]
0
Linear
0.5
250
0337h
1
Minimum
1.0
500
0337h
1.0
1000
019Ah
Copyright © 2007–2015, Texas Instruments Incorporated
21
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